viterbi block

1. Viterbi Coder Decoder for 802.11n
Report 1
Dung Nguyen
EMLab

2. Content
1. Convolutional coding
2. Viterbi Algorithm
 Register Exchange (RE)
 Trace Back (TB)
 Compare RE and TB
3. TB in detail
 Hardware architecture
 Modules in detail
4. Remaining problems

3. 1. Convolutional coder 802.11n
o Constrain length K = 7
o 64 States
o Generator Polynomial: G1 = 133, G2 = 175
(in Matlab G1 = 155, G2 = 137)
o Possible punctured code (r = 2/3 ; r = 3/4)
Page 1570 standard 2012

4. 1. Convolutional coder 802.11n
Punctured code matrix
R = 3/4
R = 2/3

5. 2. Viterbi Algorithm
 Register Exchange (RE)
 Trace Back (TB)
 Compare RE and TB

6. 2. Viterbi Algorithm
Register Exchange (RE)
 Use one register
for each state
 Register capable:
K*TBlength

7. 2. Viterbi Algorithm
Trace Back (TB)
 Store Previous state and corresponding Input of
each state
 Ex.
Trace back: 2  1  2  1  0  2  3  1  0

8. 2. Viterbi Algorithm
Register Exchange Trace-Back
+ Large area
+ More power consumption
+ Hard to routing
+ Simple block
+ Decode delay smaller
+ No need to trace back
+ Save area
+ Save power
+ More complicate
+ More TB length delay clock
+ Have to trace back

9. 3. Trace Back in detail
Hardware architecture of TB
Puncture
Code
Process

10. 3. Trace Back in detail
Hardware architecture of TB

11. 3. Trace Back in detail
Hamming Distance Computation Module
Schematic diagram
Hamming Distance Calculation
Can Implement by LUTs

12. 3. Trace Back in detail
Hardware architecture of TB

13. 3. Trace Back in detail
ACS Module
SM: State Metric (PM)
BM: Branch metric
SMq delay 1 Clk feedback to Adder
+ To Find Min
+ Feedback to Adder
Mux 2:1
1 bit
16 bits
16 bits
16 bits
BM 2bits (hard) / 3bits (Soft)

14. 3. Trace Back in detail
Share ACS between multiple
state
Use parallel processing
 Save logic element but
need control circuit
 Reduce System delay
 Simple hardware
implementation
 Save power
ACS Module

15. 3. Trace Back in detail
Hardware architecture of TB

16. 3. Trace Back in detail
Minimum Value Choice Module
 64 inputs (16bit wide each)
 Find minimum value
 Constrain: Time to find min value < TB length
Add1
Add0
Adds of min value out
Find Min of 4 values

17. 3. Trace Back in detail
Minimum Value Choice Module
Trade off: Logic element > < Delay implement
Find min 64
 Clk: 3  7
 Compare: 63 (16bits)
 Mux: 89
Find Min of 8values
Add0
Add1
Add2
MinValue

18. 3. Trace Back in detail
Hardware architecture of TB

19. 3. Trace Back in detail
Survivor Path Storage and Management Module
1 0 1 0 11
1 0 1 0 1 0
State 42
State 53
LSBMSB
t = T-1 t = T
1 0 1 0 1 1
State 43
Input
bit = 1
Selected path
0
Write to Ram
corresponding to
State 53
With two input code bit  have to
write 64 bits (64 states) to RAM

20. 3. Trace Back in detail
Survivor Path Storage and Management Module
T = 0
1 36 37 72 73 108
T = 36
1 36 37 72 73 108
T = 70
1 36 37 70 72 73 108
T = 37
1 36 37 72 73 108
tb1
wr2
T = 69
1 36 37 69 72 73 108
tb1 wr2
wr2
Start t = 0
End WR RAM1
Start find min R1
Start WR RAM2
End find min R1
Start TB R1
New data
Idle
Trace-Back

21. 3. Trace Back in detail
Survivor Path Storage and Management Module
T = 72
1 34 36 37 72 73 108
tb1
T = 73
1 33 36 37 72 73 108
tb1
wr2
wr3
T = 105
1 36 37 72 73 105 108
dc1 wr3tb2
T = 109
1 4 5 36 37 69 72 73 106 108
T = 106
1 36 37 72 73 106 108
dc1 tb2 wr3
dc1wr1 tb2
End WR R2
Start find min R2
Start WR R3
End TB R1
End find min R2
Start DC R1
Start TB R2
New data
Idle
Trace-Back

22. 3. Trace Back in detail
Hardware architecture of TB

23. 3. Trace Back in detail
Trace Back Module
Find Min
Value
•
•
•
64 paths
16 bits
•
•
6 bits addr
x x x x x x
Trace Back Reg
State begin Trace-Back

24. 3. Trace Back in detail
Trace Back Module
x x x x x x
RAM Mux
64:1
•
•
6 bit Ctrl
•
•
Ctrl Read
•
•
•
•
64 bits
Trace Back Reg
Trace-Back

25. 3. Trace Back in detail
Trace Back Module
x x x x x x
RAM Mux
64:1
•
•
6 bit Ctrl
•
•
Ctrl Read
•
•
•
•
64 bits
Trace Back Reg
Decode and Output
Output

26. 4. Remaining problems
Hard vs Soft decoding
Affect to
 LUTs of Hamming distance computation
 Bit-Width of PM signal (ACS & Minimum choice)

27. 4. Remaining problems
Punctured decoding
Affect to
 LUTs of Hamming distance computation
 Frequency of Decode circuit

28. 4. Remaining problems
 Switch between Traceback and Decode in TraceBackReg
 Manipulate with RAM
 Design control signal
 Change Clk when code rate is changed

31. Future
 Imlement gen code in SystemVue and port to FPGA
 Design and test in FPGA each module
 Manipulate with RAM in ML403 board
 Design control signal