The document discusses state transition diagrams and the various states of the 8085 microprocessor. It provides details on the T1-T6 states which represent the clock cycles, as well as the TRESET, THALT, TWAIT, and THOLD states. The TRESET state occurs when the reset signal is active, THALT occurs after HLT instruction execution, TWAIT inserts extra cycles for slow memory/I/O, and THOLD occurs when the HOLD signal requests DMA access. Transition diagrams are shown for the THALT and THOLD states to illustrate the different state changes.

1. State Transition
Diagram

2. What is State Transition Diagram?
 The state transition diagram represents the microprocessor’s internal
operations, which consists of circle to represent the states and directed
line segments to represent transitions between the states.
 A 8085 microprocessor generally have 10 states i.e. T1, T2, T3, T4, T5 ,T6
,TWAIT, TRESET, THALT, and THOLD.
 T1 to T6 represents the 6 clock cycles of the processor, as usually a machine
cycle consists of 3 to 6 T-states and rest of the states are the different
states achieved by the microprocessor dues to various control signals, e.g.
on receiving RESET signal processor in the TRESET state and similarly on
receiving HOLD signal it is in the THOLD state.
 The next state in the state transition diagram is decided by many of the
control signals i.e. INTERRUPT SIGNALS, HOLD, RESETIN , HALT, READY.

3. States of 8085
 When the 8085 switched on or the RESETIN control signal is low, then the
microprocessor is in the TRESET state and remains in this state until the RESETIN
signal remains low.
 When RESETIN become 1, then the microprocessor will go into the T1 state of a
machine cycle.
 Whenever the HLT instruction executes the microprocessor enters into the
THALT state.
 8085 microprocessor remains in the Twait state until READY pin is low. This
usually happens when the microprocessor in interacting with the slow memory,
in which microprocessor has to wait for some clock cycles until the memory is
ready with data.
 When there is high on the HOLD pin of 8085 the microprocessor enters into
the THOLD state. HOLD pin become HIGH when DMA wants to access the buses.

4. THALT state
 Whenever the HLT instruction executes, the 8085 enters into the THALT
state.
 When the current fetched instruction is HLT, then in T4 state the control
unit decodes the opcode of HLT and set an internal HALT flip-flop of
microprocessor. After T4 the microprocessor enters into the T1 state of the
next machine cycle.
 After entering into the T1 cycle of next machine cycle, microprocessor
always checks the HALT flip-flip, which might be set in the pervious clock
cycle.
 If it is found set then, instead of entering into the T2 microprocessor
enters into the THALT state otherwise in the T2.
 Thus 5 T- states , T1 , T2, T3, T4 of the current machine cycle and T1 of the
next machine cycle, are required to reach the THALT state.

5. THALT state
 In the HALT state, the address and address/data buses along with RD, WR , IO/
M are placed in their high independence states (floated).
 There are only three ways to exit from a THALT state.
1. A low an RESETIN input of the 8085 resets the entire system and, comes out
of THALT state and enters into TRESET state and remains their as long as RESETIN
is active.
2. The second way to get out of the THALT state is to make the HOLD signal input
high. The processor then enters into the THOLD state, but when the HOLD pin
goes low again, the CPU returns to the THALT state.
3. The third method of coming out of a THALT state is when an interrupt signal is
active. This method works only if interrupts were enabled with an enable
interrupt (IE) instruction in the program before HALT instruction is executed.
Whenever interrupt comes microprocessor leaves the THALT state and start
executing the ISR.

6. Transition Diagram of THALT State

7. TWAIT State
 Sometimes µΡ is used with memories or I/O devices which have longer
access time. To accommodate long access time, the 8085A has a state
called the TWAIT state.
 If the µΡ doesn't enter into THALT state, then it proceeds into the T2 state of
the machine cycle. Here it cheeks the READY pin.
 If READY pin is low, means I/O devices or memory are not ready, so
processor has to wait, then the µΡ goes to the TWAIT state and remains
there until READY pin goes high. If READY line is high then the µΡ enters
into the T3 state.
 When the READY signal becomes logic ‘1’ the µΡ comes out of TWAIT state
and enters into T3 state and the current machine cycle continues, TWAIT
states continues to be inserted as long as READY is low.

8. State Transition Diagram of TWAIT state

9. HOLD State THOLD
 Before going to the T3 state from T2 state, after check for the READY pin, 8085
verifies whether the HOLD pin is high or not. If it is HIGH, the microprocessor sets
the HLDA flip-flop before enters into the T3 state.
 The µΡ enter in this state, if same external device wants direct memory access so
that a stirs of data can be transferred at a fast rate. The device requesting for DMA
makes the HOLD signal input high.
 There are two possibilities when HOLD signal become High.
1. The µΡ may be in the THALT state and then the HOLD signal input becomes high. In
this situation, the µΡ first sets the HLDA F/F. (HOLD acknowledge F/F) & then enters
the THOLD state.
2. the µΡ is executing same m/c cycle. While execution µΡ cheek the HOLD signal at
some unique points during a m/c cycle, usually after every 2 clock cycles i.e. after
T2 and T4.

10. HOLD State THOLD
 HOLD signal is asynchronous is nature. The µΡ synchronize this request and at
proper time in a m/c cycle by providing the HLDA signal by setting HLDA F/F- for the
requesting device. The THOLD state is entered after current m/c cycle is completed.
 The HOLD signal is checked during T2 state after (READY input has been checked)
and also during T4 state (provided if the concerned m/c cycle requires T5& T6 state,
also).
 If the HOLD signal is found high the HLDA F/F is set and the processor enter the
THOLD state after the current m/c cycle.
 The microprocessor exits the THOLD state when HOLD pin becomes 0 and continuous
its previous operation from the point at which it was suspended by the HOLD
request. On exiting the THOLD state, it resets the HLDA f/f and check for the HALT f/f.

11. Contd.
 If the HALT f/f is found to be set then the microprocessor enters into the THALT state
else enters into the T1 state of the next machine cycle.
 Before enter into the T1 state of the next machine cycle, microprocessor checks whether
it is the last machine cycle of the current instruction cycle or not. If it is the last machine
cycle then check for the interrupt otherwise enters into the T1 state of next machine
cycle.
 Microprocessor does not check for the interrupt request until the end of the instruction
cycle, however it checks for the HOLD signal after every machine cycle and enters into
THOLD state at the end of current machine cycle if the signal is active.

12. Transition diagram of THOLD state