This document provides an overview of the RISC-V instruction set architecture (ISA) and ecosystem. It describes the origins and design of the RISC-V ISA, including its modular nature and standard extensions. It also summarizes the current hardware landscape, including various RISC-V CPU cores and SoCs, and the software landscape, such as simulators, toolchains, operating systems, and resources for working with RISC-V. The document concludes by suggesting areas like QEMU and LLVM that could benefit from volunteer software development time.