Advances in Verification Methodologies Workshop

Advances inVerification
Methodologies
Workshop at BMS college – June 2016
As part ofTEQIP
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Verification with System
Verilog
Ramdas M
ExperiencedVerification Engineer, Applied Micro
17+ years experience, Author, OnlineTeacher, Blogger

Introduction - Instructor
▪ ExperiencedVerification Engineer with 17 years of experience
▪ Applied Micro, Intel, IBM, C-DOT
▪ OnlineTeacher
▪ www.verificationexcellence.in
▪ FREE online courses on SystemVerilog, Assertions, Coverage,
UVM
▪ Author
▪ Cracking Digital VLSIVerification Interviews: Interview
Success
▪ Quora Blogger
▪ 200+ answers and 5 blogs, Most viewed writer inVLSI topics

Agenda – Day 1
▪ Day 1 - Morning ( 9 - 11)
▪ Introduction to SV - 10 mins
▪ Building blocks - 30 mins
▪ Language constructs -50
mins
▪ Exercise/Quiz/Q&A - 30
mins
▪ Day 1 - Morning ( 11.15 - 1)
▪ Threads and Inter process
communication
▪ Exercises/Quiz/Q& A
▪ Day 1 – Noon (2-4)
▪ SystemVerilog Classes
▪ Exercises/Quiz/Q& A

Agenda – Day 2
▪ Day 2 - Morning ( 9 - 11)
▪ Interfaces/Virtual Interfaces
▪ Randomization and
Constraints
▪ Exercise/Quiz/Q&A
▪ Day 2 -Noon ( 2-4)
▪ Lab Exercises

Introduction to
SystemVerilog
Ramdas M

What is SystemVerilog
▪ SystemVerilog is a combined hardware description language
and hardware verification language
▪ SystemVerilog is an extensive set of enhancements to IEEE
1364Verilog-2001 standards
▪ It has features inherited fromVerilog HDL,VHDL,C,C++
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History and evolution of SV
▪ Verilog (IEEE standard 1364)
▪ Began in 1983 as a proprietary language
▪ Opened to the public in 1992
▪ Became an IEEE standard in 1995 (updated in 2001 and 2005)
▪ Between 1983 and 2005 design sizes increased dramatically!
▪ SystemVerilog (IEEE standard 1800)
▪ Originally intended to be the 2005 update toVerilog
▪ Contains hundreds of enhancements and extensions toVerilog
▪ Published in 2005 as a separate document
▪ Officially supersededVerilog in 2009
▪ Updated with more features in 2012 (IEEE 1800 2012 standard)

SystemVerilog – UserView
▪ SVD -SystemVerilog for Design
▪ Features supporting Design
▪ SVTB – SystemVerilog forTest benches
▪ Test bench specific Features
▪ SVA – SystemVerilogAssertions
▪ Features for temporal and concurrent assertions
▪ SVDPI – SV Direct Programming Interface
▪ For better C/C++ integration
▪ SVAPI – SV Application Programming Interface
▪ For better Coverage/Assertion integration
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Verilog to SystemVerilog

What isVerification ?
▪ Process of demonstrating functional correctness of a
design.
6/17/2016 Verification with System Verilog 11

SystemVerilog forVerification
▪ Where do we really use SystemVerilog
Language inVerification ?
▪ Building Test bench components
▪ Stimulus generators, drivers
▪ Monitors, Checkers,Assertions
▪ Coverage
▪ Reference Models
▪ Test cases

A VerificationTest bench

Basic Building Blocks
Srividhya TP

Agenda
▪ What is coding for Design /Validation
▪ Delta overVerilog
▪ What should u Know in SystemVerilog
▪ UVM/System C

SystemVerilog Enhancements
▪ Goal
▪ Model More functionality in fewer lines of code
▪ Reduce redundancy
▪ Reduce risk of coding errors

How do u handle any HDL/Language
▪ U google 
▪ Design :Synthesizability
▪ What constructs are synthesizable
▪ What construct converts to what real logic?
▪ What are the diff optimized ways of coding?
▪ Coding for Performance, Power
▪ Macros that optimize place and route
▪ Latency, Different frequencies- FIFO Design, Standard library
components
▪ Coding for FPGAs, Silicon debug
▪ Documentation; Specification
▪ Project independence

Verification Mindset
▪ What is architecting forTestbench? Find Bugs known and unknown?
▪ How?
▪ Formal/ assertions
▪ Coverage
▪ How to eliminate Human dependency over generations
▪ What is a right construct?
▪ Simulation time..
▪ Hierarchy porting
▪ UVM – refer slide 9
▪ Error Scenarios
▪ Conferences

Common mistakes - Design
▪ Coding? Instead ofArchitecting -- Clarity
▪ IP based approach?
▪ Assumptions not coded?
▪ Latency unknown
▪ Scaleability

Common Mistakes -Verification
▪ Out of the Box thinking
▪ Architecting?
▪ Thinking Beyond the Spec
▪ Hard coding
▪ Scope for scalabilityTest /Testbench
▪ Human dependency
▪ EnhancingTB for feature is recoding/patching?
▪ Auto code generation
▪ TB randomness

Design/Verification Building blocks
▪ Modules
▪ Interfaces
▪ Subroutines (Tasks, Functions)
▪ Packages
▪ Configurations
▪ Hierarchy

Modules
▪ Basic building block for design/verification
▪ Ports with declarations (input, output )
▪ Data declarations – nets, variables, structures
▪ Constants, user defined types
▪ Class definitions
▪ Import from packages
▪ Sub routine definition
▪ Instantiation of other modules, interfaces,
▪ Instantiation of class objects
▪ Continuous assignments

Module example

Module Instance and Port
connections
▪ InVerilog, port connections must be named
▪ Very verbose and redundant info
▪ SV adds .name and .* shortcuts
▪ .name connects a port to a net of same name
▪ .* automatically connects all ports and nets with same name

Interfaces
▪ A named bundle of nets or variables
▪ Encapsulates communication between blocks
▪ Connectivity - Port list and signals
▪ Functionality – Functions and tasks
▪ An instantiation of interface can be used to connect
between multiple modules.
▪ A single name can replace a list of port

Interface example
▪ How do we abstract signal between two design blocks
like below?

Interface Example
▪ Advantages
▪ Simplifies complex bus definitions and interconnections
▪ Ensures consistency through out design and verification
blocks

Interface - Another Example

Interface Example

Tasks and Functions - Usage
▪ Tasks
▪ Tasks can enable other tasks and functions
▪ Tasks may execute in non-zero simulation time.
▪ Tasks may have zero or more arguments of type
input, output and inout.

Synthesizable Variable types
▪ New useful synthesizable types
▪ logic - 4 state variable, user defined size (replaces reg)
▪ reg doesn’t always infer register
▪ Use of logic makes less confusion s in code
▪ enum – variable with specified set of legal values
▪ int - 32 bit 2 state variable ( can replace integer in for loops)
▪ Avoid using 2 state variables in synthesizable code

Simplified port type rules
▪ Traditional verilog has strict and confusing port type rules
▪ Inputs must be declared wire
▪ Outputs must be
▪ reg if driven from procedural statement
▪ wire if driven by continuous statement
▪ wire if connected to module instances
▪ SystemVerilog makes it easy
▪ Declare all as logic

Tasks and Functions - Usage
▪ Functions
▪ Function can enable other functions only. Task
cannot be called from functions.
▪ Functions should execute in zero simulation time.
▪ Functions have only one return value but System
Verilog also allows functions to have input, output or
inout types.
▪

Tasks

Functions

Argument passing
▪ Pass by value
▪ Each argument is copied to the subroutine area
▪ Pass by reference
▪ A reference to the original argument is passed instead of
copying

Packages
▪ Provides a declaration space that can be shared by
building blocks
▪ Supports declaration of nets, variables, tasks,
functions, classes, parameters etc
▪ Declarations can be imported to other building blocks
by importing package

Package: Example

Structure of a Design or Test bench code
Packages
Module/Program
always blocks/initial
blocks/processes
Parameters/defines, type defines, structs
etc useful across files
•Contains declarations
•functions/tasks, data types, objects etc
•Contains concurrent processes/blocks
•module instance, continuous assign,
always blocks etc
•Contains sequential code
•If then else, case etc -> control constructs
•Repeat/for loops/do..while -> loops
•Blocking/non-blocking assignments etc

Language Constructs
-DataTypes
Ramdas M

Data Types
▪ Nets
▪ Can be written by one or more continuous
assignments
▪ No procedural assignment allowed
▪ Used to model physical connections (e.g. wires)
▪ Multiple drivers will result in a value based on net
type

Data Types
▪ Variables
▪ Can be written by one or more procedural assignments
▪ Or can be written by “one” continuous assignment
▪ Last write determines the value
▪ Normally declared as
▪ <data type> instance
▪ E.g. logic abc;
▪ e.g. int value;
▪ 2 state vs. 4 state variables
▪ Values = 0, 1, x and Z

DataTypes
▪ 2 valued data types
▪ bit (1 bit)
▪ byte (8bits)
▪ shortint (16 bit)
▪ int (32 bits)
▪ 4 valued data types
▪ logic (1bit)
▪ integer (32 bit)
▪ Time (64 bit)

Integer DataType

Signed/UnsignedTypes
▪ byte, shortint, int, integer and longint defaults to signed
▪ Use unsigned to represent unsigned integer value
▪ time, bit, reg and logic defaults to unsigned
▪ Use signed to represent signed values
▪ Signedness can be explicitly defined as follows:

Vectors
▪ Vectors are packed array of scalars
▪ Both MSB and LSB needs to be constant integer expressions
▪ Cannot be x (unknown) or z( high impedance)

Strings
• String – ordered collection of characters
• If not initialized defaults to empty string - “ “

Strings - operators
Str1 == Str2 Equality
Str1 != Str2 Inequality
<, <=, >, >= Comparison
{Str1, Str2, … Strn} Concatenation
Str1[index] indexing – return 0 if out
of range

String Methods
• len
• putc
• getc
• toupper
• tolower
• compare
• icompare
• substr
• atoi, atohex,
atoct, atobin
• atoreal
• itoa
• hextoa
• octtoa
• bintoa
• realtoa

User defined types
▪ A typedef can be used to give a user defined name to an
existing type

EnumeratedTypes
▪ An enumerated type defines a set of named values.
▪ Defaults to “int” if data type declaration missing

Defining new data types as enums
▪ A type name can be given to a enumerated type to create a
new data type
▪ Ranges in elements
▪ Creates 5 elements sub0, sub1, sub2, sub3, sub4 and 3
elements jmp6, jmp7, jmp8

Other data types
▪ void data type represents nonexistent data. Usually
used for functions with no return values
▪ chandle data type represents storage for pointers
passed using DPI
▪ class - A variable that can hold handle to a class
object
▪ event – Provides a way of synchronization of two ore
more concurrently active process
▪ Constant data types - parameters (evaluated
elaboration time) and const (set during simulation)

Other data types
▪ Aggregate Data types (Will explain in later section)
▪ Structures
▪ Unions
▪ Arrays
▪ Dynamic , Associative arrays
▪ Queues

Operators and
Expressions
Ramdas

Operators
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Operators

Operators
▪ Similar to other languages
▪ For more specifics refer to LRM Chapter 11
▪ As this needs to be used as a reference

Loops and Flow
control
Ramdas

Loops and Flow Control
▪ If-else-if
▪ case/casex/casez
▪ forever
▪ repeat
▪ while
▪ do..while
▪ foreach

Examples - Loops
for (int i; i < arr.size();
j+=2, i++) begin
arr[i] += 200;
arr[i]--;
end
1)x = 0;
while (x) begin
$display(“%d”, x);
x--;
end
2) do
begin
$display(“%d”, x);
x--;
end
while (x);

forever
▪ Continuous execution, without end
▪ Used with timing controls
▪ Usually last statement in some block
initial : clock_drive
begin
clk = 1’b0;
forever #10 clk = ~clk;
end : clock_drive

repeat
▪ Repeat a block ‘x’ times, no conditional test
▪ repeat (expr) statement
▪ Example
x = 0;
repeat (16)
begin
$display(“%d”, x++);
end

case/casez/casex
▪ case:
▪ 4-value exact matching.
▪ No don’t cares allowed

case/casez/casex
▪ casez/casex:
▪ Allows don’t care to be specified
▪ Useful for priority decoders
▪ casez will handle z as don’t care
▪ casex will handle both z and x as don’t care
▪ Not so commonly used in verification/testbench

Arrays

Fixed Size Arrays
Declaring fixed-size arrays
▪ int values[0:15]; // 16 ints [0]..[15]
▪ int styles[16]; // 16 ints [0]..[15]
Multi Dimensional
▪ int memarray [0:7][0:3]; //Verbose declaration
▪ memarray[7][3] = 1; // Set last array element
▪ int testarray [8][4]; // Compact declaration

Packed Arrays
▪ An array that represents a contiguous set of bits
▪ Can access subfields of array as elements
▪ Can be made of only single bit data types – bit, logic,
reg or enumerated types
▪ E.g.: bit [7:0] data //packed array of 8 bits

Unpacked Arrays
▪ Unpacked arrays need not be set as contiguous bits in
memory
▪ real latency [7:0]; // unpacked array of real types
▪ Unpacked arrays can be made of any data types
▪ Class record_c;
▪ record_c table[7:0] // unpacked array of objects

Packed and Unpacked Arrays

Dynamic Arrays
▪ An array whose size can be changed at run time
▪ Uninitialized size will be zero

Dynamic Arrays

Dynamic Array - Methods
function int size() Returns the current size of the array
int addr[ ] = new[256];
int j = addr.size(); // j = 256
function void delete() Empties array contents and zero-sizes it
int addr[ ] = new[256];
addr.delete();
Resizing
<array> = new[<size>](<src_array>);
dyn= new[j * 2](fix);

ArrayAssignments

Associative Arrays
• Associative arrays are used when the size of the
array is not known or the data is sparse.
• Syntax:
data_type array_name [index_type];

Associative Array Methods
Function Use
num() / size() Returns number of entries
delete(<index>) Index for delete optional. When
specified used to delete given index
else whole array.
exists (<index>) Returns 1 if element exists at index
else 0
first (<index>), last (<index>) assigns to the given index variable the
value of the first/last (smallest/largest)
index in the associative array.
It returns 0 if the array is empty, and 1
otherwise.
next (<index>), prev (<index>) finds the entry whose index is
greater/smaller than the given index.

Example : Printing an associative
array

Queues
▪ A queue is a variable size, ordered collection of
homogeneous elements
▪ Can grow or shrink in size
▪ Few examples

Queue Operators
▪ Q[ a : b ] yields a queue with b - a + 1 elements.
▪ If a > b , resultant queue will be an empty queue
▪ If a = b, resultant queue will be a single element queue
▪ If either a or b are 4-state expressions containing X or Z
values, it yields the empty queue {}.
▪ Q[ a : b ] where a < 0 is the same as Q[ 0 : b ].
▪ Q[ a : b ] where b > $ is the same as Q[ a : $ ].

Queue Methods

Queues - Examples
item = q1[0]; // read leftmost ( first ) item from list
item = q1[$]; // read rightmost ( last ) item from list
n = q1.size; // determine number of items on q1
q1 = q1[1:$]; // delete leftmost ( first ) item of q1
q1 = q1[0:$-1]; // delete rightmost ( last ) item of q1
for (int i=0; i < q1.size; i++) // step through a list using integers
begin … end
q1 = { }; // clear the q1 list

Array locator methods
▪ Methods that allow searching through an array including
queues
▪ Returns a queue of matching entries

Array locator methods

Array locator - Examples

Array Ordering Methods
▪ reverse() reverses the order of the elements in the
array
▪ sort() sorts the array in ascending order
▪ rsort() sorts the array in descending order
▪ shuffle() randomizes the order of the elements in the
array

Array Ordering Methods -
Examples

Exercises

Process and Inter
Process Communication
Ramdas

Sequential vs Concurrent Blocks
▪ Sequential Block:
▪ A block of statements executed
in a sequential order
▪ It finishes the current
statement, then begins the next
▪ You always know the order in
which it actually executes the
statements
▪ The simulator exits the block
after finishing the last
statement
• Concurrent Block
– A block of statement(s) executed
concurrently (parallel) by a
simulator.
– It starts executing all statements
simultaneously
– You cannot know the order in
which it actually executes
statements scheduled for the same
simulation time
– The simulator exits the block after
finishing the latest statement.
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Examples
▪ Sequential block
▪ Concurrent block
▪ always procedures
▪ initial procedures
▪ final procedures
▪ fork..join blocks

initial procedure
▪ initial procedure executes only once
▪ It ends when the last statement finishes.
▪ Multiple initial procedures execute concurrently

final procedure
▪ Similar to initial procedure but executed at end of
simulation
▪ Unlike initial procedure, this executes in zero time
▪ No delays allowed

always procedure
▪ Four forms of always procedures supported
▪ always
▪ General purpose, needs a timing control
▪ always_comb
▪ Used for modelling combinational logic
▪ always_latch
▪ Used for modelling latched logic behavior
▪ always_ff
▪ Used to model synthesizable sequential logic behavior

Parallel Blocks
▪ Parallel blocks (Threads) are created via fork…join
▪ All threads execute concurrently
▪ Delay control for separate threads
▪ Highly useful to maximize stimulus interactions

Applications
▪ Testbenches need to model multiple concurrent
processes
▪ Providing inputs/stimulus to Design UnderTest
▪ Parallel stimulus on multiple interfaces
▪ Monitoring multiple inputs and outputs for
checking/logging
▪ Detecting timeout problems

fork
a;
b;
c;
join
join
fork
fork-join
fork
a;
b;
c;
join_any
fork
a;
b;
c;
join_none
Join_any
fork
Join_none
fork
fork-join_nonefork-join_any

Examples

Process Controls
▪ wait fork statement
▪ Blocks process execution flow until all immediate child
subprocesses completes

Process Controls
▪ disable fork statement
▪ Stops execution of all child sub processes

Mailboxes
▪ Mailbox is a communication mechanism that allows
messages to be exchanged between different processes.
▪ Data can be sent to a mailbox by one process and retrieved
by another

Mailbox Methods
6/17/2016 104
Method Use
new() Create a new mailbox.
put() Place a message in a mailbox.
get() Retrieve a message from mailbox.
try_get()/
try_peek()
Try to retrieve a message from the mailbox without
blocking.
try_put() Try to place a message in mailbox without blocking.
Useful only for bounded mailboxes.
peek() Copies a message from mailbox without actually
removing it.
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MailboxTypes
▪ Unbounded Mailboxes
▪ No restrictions placed on size of mailbox
▪ put() will never block.
▪ Eg: mailbox m = new ();
▪ Bounded Mailboxes
▪ Number of entries is determined when the mailbox is
created.
▪ Bound value should be positive.
▪ put() will be blocked if the mailbox is full.
▪ Eg: mailbox m = new (5); // mailbox of depth = 5

Mail box Example

Mail box Example
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Events
▪ Events are constructs that allow hand shake
between two processes
▪ Triggered using -> operator.
▪ Triggering unblocks all waiting processes
▪ @ is used to wait for an event

Event - example

EventVariables
6/17/2016 111
▪ Merging Events
▪ When one event variable
is assigned to another,
both merge into one
event variable.
▪ Executing -> on either one
of the events affects
processes waiting on
either event variable.
event a, b;
a = b;
-> a; // also triggers b
-> b; // also triggers a

Semaphores
▪ Semaphores are typically used for mutual exclusion, access
control to shared resources, and basic synchronization
▪ Can be described as counters used to control access to shared
resources by multiple processes [threads].
▪ e.g.: Multiple request drivers accessing a shared bus
▪ Implemented as a bucket with fixed number of keys
▪ Processes using semaphores must first procure a key before
executing
▪ All others must wait until a sufficient number of keys is returned
to the bucket.

Semaphore Methods
6/17/2016 113
▪ Semaphore provides following built-in methods:
Method Use
new() Create a semaphore with specified
number of keys.
put() Return one or more keys back.
get() Obtain one or more keys.
try_get() Try to get one or more keys without
blocking.

Semaphore example

SystemVerilog
Classes
Ramdas

What is OOP?
▪ OOP is object oriented programming
▪ Organize programs in same way as objects
are organized in real world
▪ Break programs in the same way
▪ Several Languages support OOP
▪ C++, Java, (SW) and System Verilog (HDL)

Class Basics
▪ A Class is a description of some group of
things that have something in common.
▪ Objects are individual instances of
“classes”.
▪ Example: A class might be “Automobile”.
Instances of the “Automobile” class
might be “Joe’s car”, “Bob’s car”, “Sally’s
truck”, etc.
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Classes
▪ Inheritance: (is-a relationship)
▪ Allows users to extend existing classes
▪ Eg. Extending the “Automobile” class to create
subclasses for “car”, “truck”, “van”, etc.
▪ When using inheritance, the sub-class “inherits” all
the parents public/protected data properties and
methods.

Classes
▪ Composition: (has-a relationship)
▪ Composition is used for the case where one
object HAS-A instance of another class.
▪ For example, an “Automobile” class might
have 4 instances of a “wheel” class

Inheritance vs Composition

Class Definition
classname;
<data_declarations>;
<task/func_decls>;
endclass

Class Instantiation
▪ Objects created and
Initialized via call to the
new Constructor Method
▪ All objects have built-in
new method
▪ Allocates storage for all data
properties
▪ User-defined new method
can initialize and/or do
other things
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122

Class Inheritance

Data Hiding and Encapsulation
Member type Properties
local • Can be accessed only within class
• Not visible in derived class
protected • Can be accessed only within class
• Visible in derived class
public • Can be accessed from class as well as outside
class using object reference
•Visible in derived class

Examples

Special handle - “this”
▪ Used to refer to current instance of this class
▪ Removes ambiguity as in below example.
▪ X is both a class member and argument to constructor

Static class properties
▪ Static properties/data members are “static” to all instances of
the class.
▪ Created only once and shared with all instances
▪ In above example, all instances of packet will share one value
for fileID.

Static class methods
▪ Can be called outside class without instantiation
▪ Cannot access non-static members
▪ Cannot access “this” handle
▪ Cannot be virtual

Super keyword
▪ super keyword is used from within a derived class to
access base class members/methods

Constant Class Properties
▪ const keyword may be used to make class properties
unchangeable.

Polymorphism
▪ Polymorphism:
▪ The ability to process objects differently
depending on their data type or class.

Polymorphism
▪ Subclass objects are also legal representation of base class
objects
▪ A Derived class object handle can be assigned to base class
pointer
▪ All overridden members in derived class will be hidden in this
case.
▪ Base class definitions will be called when using base class pointer

Casting
▪ A base class object handle cannot be assigned to a
derived class handle
▪ If the base class object handle refers to an object of
derived class, then $casting can be used.

Virtual Methods
▪ Used as prototype definition in base class
▪ A virtual method definition will override all of definitions
in all base classes
▪ Needs to have matching argument types, identical
qualifiers, directions
▪ “virtual” keyword is optional in derived classes

Virtual Method - Example

Abstract Classes
▪ The virtual keyword may be used on a class to
make the class “abstract”.
▪ An abstract class may not be instantiated. Users
must derive from abstract class for use.
▪ Useful as prototype class definition

pure virtual method
▪ Virtual method in an abstract class can be made as a
prototype with pure keyword
▪ An extended sub class has to provide a definition to
pure virtual method

Parameterized Class
▪ Allows Generic Class to be Instantiated as Objects of
Different Types

Typedef Class and Forward References
▪ Sometimes it is necessary to use a class before it has been
defined.
▪ e.g. If two classes need handles of each other

Overloading
▪ Overloading
▪ multiple methods in the same class with the
same name but different signatures
▪ SV Class doesn’t support

Overriding
▪ Overriding
▪ Two methods, one in a parent class and one in a
child class, that have the same signature
▪ lets you define a similar operation in different ways
for different object types.
▪ System Verilog supports overriding not overloading.

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