Quantum Computing in China: Progress on Superconducting Multi-Qubits System

In this deck from the 2018 Swiss HPC Conference, Alexander Ruebensaal from ABC Systems AG presents: NVMe Takes It All, SCSI Has To Fall. "NVMe has beome the main focus of storage developments when it comes to latency, bandwidth, IOPS. There is already a broad range of standard products available - server or network based." Watch the video: https://insidehpc.com/2018/06/video-nvme-takes-scsi-fall/ Learn more: http://www.abcsystems.ch/ and http://www.hpcadvisorycouncil.com/events/2018/swiss-workshop/agenda.php Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Memory, Big Data, NoSQL and Virtualization

Bigstep

In-memory processing has started to become the norm in large scale data handling. This is aclose to the metal analysis of highly important but often neglected aspects of memory accesstimes and how it impacts big data and NoSQL technologies.We cover aspects such as the TLB, the Transparent Huge Pages, the QPI Link, Hyperthreading and the impact of virtualization on high-memory footprint applications. We present benchmarks of various technologies ranging from Cloudera’s Impala to Couchbase and how they are impacted by the underlying hardware.The key takeaway is a better understanding of how to size a cluster, how to choose a cloud provider and an instance type for big data and NoSQL workloads and why not every core or GB of RAM is created equal.

Cassandra Performance Benchmark

Bigstep

The Economics of Scaling Cassandra - By Alex Bordei, Techie Product Manager at Bigstep This presentation was made during the "Cassandra Summit 2014" Event, in London. We benchmarked Cassandra on a number of configurations and we show what's the scaling profile. We test Cassandra on Docker as well as Cassandra's In-memory feature. Follow Alex on Twitter: @alexandrubordei Bigstep on Twitter: @BigStepInc If you have any questions, let us know at hello@bigstep.com and we'll do our best to answer. Stay informed: http://blog.bigstep.com/

Virtual net performance

This document summarizes virtual networking performance measurements and analysis. It finds that virtual networking introduces overhead compared to physical networking, with legacy emulated NICs performing worse than newer virtual NIC designs. Current work focuses on areas like multiqueue support, zero copy networking, and batching to improve performance. The document outlines future work areas and ways people can help, such as through testing, profiling, and developing optimizations.

Ovs perf

Madhu c

This document analyzes the performance of OpenVSwitch (OVS) using various tools. Key findings include: - DPDK-based OVS achieves 9.9 Gbps throughput for a single flow on one core, far surpassing standard and Linux bridge OVS. - Latency is lowest for direct NIC-NIC communication and increases for OVS and VM-based setups. - The OVS kernel flow cache supports up to 200,000 flows but throughput degrades by 5% at 2,048 flows due to misses. - Removing IPTables modules improves VM-OVS-VM throughput by up to 15%, and enabling VXLAN offload provides an additional 25

Geneve

Madhu c

This document discusses representing Geneve encapsulation metadata in OpenFlow flows. It proposes mapping each Geneve option to an OpenFlow experimenter OXM field, allowing multiple tun_metadata matches per flow. It outlines changes needed to OVS internals to support parsing variable length tun_metadata and indexing into the match field. Finally it discusses additional considerations like supporting large Geneve option payloads and handling critical vs. non-critical options.

DPACC Acceleration Progress and Demonstration

OPNFV

The session provides an update to on the DPACC project within the OPNFV with a brief discussion on APIs and implementation progress. This session will review the API definition progress and follow up with a demo highlighting a common application as the vNF running on top of the DPACC defined layers. The demo will highlight the use of both hardware and software acceleration utilizing the DPACC defined acceleration layers. The demonstrationIt will highlight the progress in optimizing performance and latency characteristics of a platform to realize the vision of NFV while meeting stringent requirements, particularly for certain workloads, required by carriers.

Service Function Chaining (SFC) is one of top 5 NFV use case. Supporting SFC in provider and enterprise networks requires performance assurance. Specifically, the Classifier and the Service Function Forwarder which are typically implemented in software such as virtual switches need to match line rate requirement. DPDK (Data Plane Development Kit) is an open source project comprising a set of libraries and drivers for fast packet processing. In this presentation, we will discuss our experiences accelerating SFC with DPDK. In addition, Telco and Datacenter carriers demands dynamic SFC that requires new SFC wire protocols (e.g. VxLAN-GPE and NSH) support in both data and control planes. We intend to share our experiences and future works of a high performance, NSH-aware SFC vertical solution with open-source ingredients: Openstack, Opendaylight, OpenvSwitch with DPDK acceleration.

The n00bs guide to ovs dpdk

markdgray

The document provides instructions for using DPDK and OVS-DPDK on Ubuntu 14.04 LTS. It begins by cloning the DPDK and OVS source code and checking out specific versions. It then builds DPDK and runs the testpmd application to verify basic packet forwarding. The document configures hugepages and binds NICs before starting testpmd. It provides output of the testpmd commands. Finally, it mentions setting up OVS-DPDK which involves the host and guest OS as well as Qemu and Fedora in a VM.

Развитие MX маршрутизаторов

The document provides an overview of updates to Juniper's MX platform, including new line cards and interface options for increased scale and performance. Key points include: - New MPC5E and MPC6E line cards that provide increased throughput and interface flexibility with options like 100G interfaces. - Software features for increased routing scale, virtualization support, and packet performance optimization techniques like "hypermode forwarding" and "turbo filters." - A next generation port extender architecture for simplifying management of satellite devices connected to MX routers. - EVPN and VXLAN support for using MX routers as data center gateways in multi-tenant cloud environments.

Performance challenges in software networking

Stephen Hemminger discusses performance challenges in software networking. He addresses myths about throughput limits and compares hardware and software approaches. Optimization requires analyzing bottlenecks like CPU cache usage and avoiding locks. While benchmarks use ideal conditions, real systems have bursty traffic, many rules, and limited resources. The performance of software networking depends on algorithms, CPU efficiency, and handling cache behavior.

VMworld 2013: Extreme Performance Series: Network Speed Ahead

VMworld

Playing BBR with a userspace network stack

Hajime Tazaki presented on using the Linux Kernel Library (LKL) to run a userspace network stack with TCP BBR. Initial benchmarks showed poor BBR performance with LKL due to imprecise timestamps. Improving the timestamp resolution and scheduler optimizations increased BBR throughput to be comparable to native Linux. Further work is needed to fully understand performance impacts and optimize for high-speed networks. LKL provides a reusable network stack across platforms but faces challenges with timing accuracy required for features like BBR.

A Baker's dozen of TCP

The document summarizes congestion control versus bufferbloat. It discusses TCP congestion control types like Reno, Vegas, CUBIC and HTCP. Problems with traditional TCP Reno include slow recovery times at high bandwidths. Delay based congestion control approaches like Vegas can be too sensitive. Hybrid approaches that combine loss-based and delay-based may help address issues but need further refinement. More real-world testing of congestion control algorithms is needed.

From virtual to high end HW routing for the adult

MarketingArrowECS_CZ

NUSE (Network Stack in Userspace) at #osio

This document describes Network Stack in Userspace (NUSE), which implements a full network stack as a userspace library. NUSE aims to allow faster evolution of network stacks outside the kernel and enable network protocol personalization. It works by patching the Linux kernel to include a new architecture, implementing the network stack components as a userspace library, and hijacking POSIX socket calls to redirect them to the NUSE implementation. Performance tests show NUSE adding only small overhead compared to kernel implementations. NUSE can also integrate with the ns-3 network simulator to enable controllable and reproducible network simulations using real protocol implementations.

Dpdk performance

FOSDEM15 SDN developer room talk DPDK performance How to not just do a demo with DPDK The Intel DPDK provides a platform for building high performance Network Function Virtualization applications. But it is hard to get high performance unless certain design tradeoffs are made. This talk focuses on the lessons learned in creating the Brocade vRouter using DPDK. It covers some of the architecture, locking and low level issues that all have to be dealt with to achieve 80 Million packets per second forwarding.

DPDK in Containers Hands-on Lab

Michelle Holley

This document provides an agenda and overview for a hands-on lab on using DPDK in containers. It introduces Linux containers and how they use fewer system resources than VMs. It discusses how containers still use the kernel network stack, which is not ideal for SDN/NFV usages, and how DPDK can be used in containers to address this. The hands-on lab section guides users through building DPDK and Open vSwitch, configuring them to work with containers, and running packet generation and forwarding using testpmd and pktgen Docker containers connected via Open vSwitch.

http server on user-level mTCP stack accelerated by DPDK

Linaro

Evolving Virtual Networking with IO Visor

Larry Lang

High Performance Networking Leveraging the DPDK and Growing Community

6WIND

dCUDA: Distributed GPU Computing with Hardware Overlap

Torsten Hoefler from ETH Zurich presented this deck at the Switzerland HPC Conference. "Over the last decade, CUDA and the underlying GPU hardware architecture have continuously gained popularity in various high-performance computing application domains such as climate modeling, computational chemistry, or machine learning. Despite this popularity, we lack a single coherent programming model for GPU clusters. We therefore introduce the dCUDA programming model, which implements device-side remote memory access with target notification. To hide instruction pipeline latencies, CUDA programs over-decompose the problem and over-subscribe the device by running many more threads than there are hardware execution units. Whenever a thread stalls, the hardware scheduler immediately proceeds with the execution of another thread ready for execution. This latency-hiding technique is key to make best use of the available hardware resources. With dCUDA, we apply latency hiding at cluster scale to automatically overlap computation and communication. Our benchmarks demonstrate perfect overlap for memory bandwidth-bound tasks and good overlap for compute-bound tasks." Watch the video presentation: http://wp.me/p3RLHQ-gCB

Решения NFV в контексте операторов связи

Juniper Networks' vMX product provides a virtualized routing platform that can run the same Junos operating system as physical MX routers. The vMX uses virtualized DPDK-accelerated packet processing called vTRIO to separate the control and data planes for high performance. It supports various hypervisor and container deployments and can scale throughput from 100Mbps up to multiple 10Gbps ports depending on vCPU and core allocation. The vMX is suited for applications such as virtual PE routers, DC gateways, cloud WAN routers, and route reflectors where service providers need a virtualized solution that leverages their existing Junos feature set.

Comprehensive XDP Off‌load-handling the Edge Cases

Netronome

While XDP is less complex to offload than other forms of kernel functionality due to the fact that it sits at the bottom of the stack, there are a number of items that lead to complexity when dealing with XDP offload. This talk will explore some of the ideas around how to implement these concepts as well as share some of the results we have seen while implementing offload on a 32 bit architecture.

Performance Tuning EC2 Instances

Brendan Gregg

Talk for AWS re:Invent 2014. Video: https://www.youtube.com/watch?v=7Cyd22kOqWc . Netflix tunes Amazon EC2 instances for maximum performance. In this session, you learn how Netflix configures the fastest possible EC2 instances, while reducing latency outliers. This session explores the various Xen modes (e.g., HVM, PV, etc.) and how they are optimized for different workloads. Hear how Netflix chooses Linux kernel versions based on desired performance characteristics and receive a firsthand look at how they set kernel tunables, including hugepages. You also hear about Netflix’s use of SR-IOV to enable enhanced networking and their approach to observability, which can exonerate EC2 issues and direct attention back to application performance.

A PCIe Congestion-Aware Performance Model for Densely Populated Accelerator S...

In this deck from the Switzerland HPC Conference, Maxime Martinasso from CSCS presents: Best Practices: A PCIe Congestion-Aware Performance Model for Densely Populated Accelerator Servers. "MeteoSwiss, the Swiss national weather forecast institute, has selected densely populated accelerator servers as their primary system to compute weather forecast simulation. Servers with multiple accelerator devices that are primarily connected by a PCI-Express (PCIe) network achieve a significantly higher energy efficiency. Memory transfers between accelerators in such a system are subjected to PCIe arbitration policies. In this paper, we study the impact of PCIe topology and develop a congestion-aware performance model for PCIe communication. We present an algorithm for computing congestion factors of every communication in a congestion graph that characterizes the dynamic usage of network resources by an application. Our model applies to any PCIe tree topology. Our validation results on two different topologies of 8 GPU devices demonstrate that our model achieves an accuracy of over 97% within the PCIe network. We demonstrate the model on a weather forecast application to identify the best algorithms for its communication patterns among GPUs." Watch the video: http://wp.me/p3RLHQ-gDi Learn more: http://www.hpcadvisorycouncil.com/events/2017/swiss-workshop/agenda.php Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Introduction to DPDK

Kernel TLV

DPDK is a set of drivers and libraries that allow applications to bypass the Linux kernel and access network interface cards directly for very high performance packet processing. It is commonly used for software routers, switches, and other network applications. DPDK can achieve over 11 times higher packet forwarding rates than applications using the Linux kernel network stack alone. While it provides best-in-class performance, DPDK also has disadvantages like reduced security and isolation from standard Linux services.

Virus, Vaccines, Genes and Quantum - 2020-06-18

Aritra Sarkar

This document discusses using a quantum computer to simulate DNA-based vaccines by indexing and aligning short DNA reads to a reference genome. It describes superimposing the reference genome segmented into short reads and evolving via controlled operations to the Hamming distance against the short read. The maximum probability entry indicates the alignment index. Steps include 1) superposing the indexed reference segments, 2) evolving via controlled operations to the Hamming distance, and 3) finding the maximum probability entry indicating the alignment index.

TCP congestion control

Shubham Jain

What's hot

Accelerate Service Function Chaining Vertical Solution with DPDK

OPNFV

The n00bs guide to ovs dpdk

markdgray

Развитие MX маршрутизаторов

Performance challenges in software networking

VMworld 2013: Extreme Performance Series: Network Speed Ahead

VMworld

Playing BBR with a userspace network stack

A Baker's dozen of TCP

From virtual to high end HW routing for the adult

MarketingArrowECS_CZ

NUSE (Network Stack in Userspace) at #osio

Dpdk performance

DPDK in Containers Hands-on Lab

Michelle Holley

http server on user-level mTCP stack accelerated by DPDK

Linaro

Evolving Virtual Networking with IO Visor

Larry Lang

High Performance Networking Leveraging the DPDK and Growing Community

6WIND

dCUDA: Distributed GPU Computing with Hardware Overlap

Решения NFV в контексте операторов связи

Comprehensive XDP Off‌load-handling the Edge Cases

Netronome

Performance Tuning EC2 Instances

Brendan Gregg

A PCIe Congestion-Aware Performance Model for Densely Populated Accelerator S...

Introduction to DPDK

Kernel TLV

What's hot (20)

Accelerate Service Function Chaining Vertical Solution with DPDK

The n00bs guide to ovs dpdk

Развитие MX маршрутизаторов

Performance challenges in software networking

VMworld 2013: Extreme Performance Series: Network Speed Ahead

Playing BBR with a userspace network stack

A Baker's dozen of TCP

From virtual to high end HW routing for the adult

NUSE (Network Stack in Userspace) at #osio

Dpdk performance

DPDK in Containers Hands-on Lab

http server on user-level mTCP stack accelerated by DPDK

Evolving Virtual Networking with IO Visor

High Performance Networking Leveraging the DPDK and Growing Community

dCUDA: Distributed GPU Computing with Hardware Overlap

Решения NFV в контексте операторов связи

Comprehensive XDP Off‌load-handling the Edge Cases

Performance Tuning EC2 Instances

A PCIe Congestion-Aware Performance Model for Densely Populated Accelerator S...

Introduction to DPDK

Similar to Quantum Computing in China: Progress on Superconducting Multi-Qubits System

Virus, Vaccines, Genes and Quantum - 2020-06-18

Aritra Sarkar

TCP congestion control

Shubham Jain

QX Simulator and quantum programming - 2020-04-28

Aritra Sarkar

This document discusses quantum computing simulation and quantum programming. It notes that directly simulating large quantum systems requires exponential resources, but that smart simulation techniques can reduce these requirements. It introduces the QX quantum computing simulator, including its syntax, functionality for noisy circuits, classical control, and parallelism. The document provides examples of simulating simple circuits and algorithms to demonstrate the QX simulator's capabilities.

Paris Quantum Computing & Technologies Meetup #1

Christophe Jurczak

Aritra Sarkar - Search and Optimisation Algorithms for Genomics on Quantum Ac...

Tom Hubregtsen

This document discusses using quantum computing to accelerate genomics algorithms. It proposes using quantum search and optimization algorithms to solve problems like genome assembly and alignment that are challenging for classical computers due to the large amount of genomic data. The document outlines algorithms like Grover's search and the Quantum Approximate Optimization Algorithm that could be applied and benchmarks their performance on test problems and real genomic data. It also discusses the software tools and computing platforms needed to develop and test these quantum genomics applications.

Quantum Computing

AntonChirayil

This document provides an overview of superconducting quantum processors. It discusses the history of quantum computing, how superconducting qubits work, common qubit types like transmon qubits, and how qubits are controlled with gates. It also describes the basics of superconducting quantum circuits including qubit layout, connection, and readout. Key components of quantum processors like the dilution refrigerator and examples like the D-Wave 2000Q are summarized. Applications of quantum computing and some concluding thoughts are also presented.

XPDS13: On Paravirualizing TCP - Congestion Control on Xen VMs - Luwei Cheng,...

The Linux Foundation

While datacenters are increasingly adopting VMs to provide elastic cloud services, they still rely on traditional TCP for congestion control. In this talk, I will first show that VM scheduling delays can heavily contaminate RTTs sensed by VM senders, preventing TCP from correctly learning the physical network condition. Focusing on the incast problem, which is commonly seen in large-scale distributed data processing such as MapReduce and web search, I find that the solutions that have been developed for *physical* clusters fall short in a Xen *virtual* cluster. Second, I will provide a concrete understanding of the problem, and reveal that the situations that when the sending VM is preempted versus when the receiving VM is preempted, are different. Third, I will introduce my recent attempts on paravirtualizing TCP to overcome the negative effect caused by VM scheduling delays.

開発者が語る NVIDIA cuQuantum SDK

NVIDIA Japan

A Robust UART Architecture Based on Recursive Running Sum Filter for Better N...

Kevin Mathew

This document describes a project to design a robust UART architecture using a recursive running sum filter for better noise performance. It discusses adding noise to communication channels to test noise performance. It then describes implementing a UART receiver using a recursive running sum filter to reduce noise while maintaining signal integrity. The UART design is tested on a Nexys3 Spartan-6 FPGA board in Xilinx ISE using VHDL. Simulation results at different noise levels show the filter is effective at reducing noise.

What is Quantum Computing and Why it is Important

Sasha Lazarevic

Resume_Karthik_Koneru_Analog_and_Mixed Signal

Arizona State University

Karthik Koneru is seeking an entry-level position in analog and mixed-signal design/verification starting in May 2015. He has a Master's degree in Electrical Engineering from Arizona State University and experience designing circuits including op-amps, voltage references, PLLs, ADCs, and LDO voltage regulators. His skills include Verilog, Cadence tools, and he has experience with projects involving PLLs, sigma-delta modulators, ADCs, and current references.

Resume_Karthik_Koneru_Analog_and_Mixed Signal

Arizona State University

IQM slide pitch deck

Kan Yuenyong

Computer network (13)

NYversity

This document summarizes key concepts about congestion control in TCP including: - TCP uses additive increase multiplicative decrease (AIMD) to dynamically adjust the congestion window size and maintain efficiency and fairness. - TCP has slow start and congestion avoidance states that govern how the congestion window is adjusted in response to acknowledgements. - TCP responds to packet loss through fast retransmit, fast recovery, and halving the congestion window size to reduce congestion according to protocols like Tahoe, Reno, and New Reno.

LF_OVS_17_OVS/OVS-DPDK connection tracking for Mobile usecases

LF_OpenvSwitch

1) Mobile networks today handle a large number of simultaneous short duration flows, with high call rates of 100k-200k connections per second. Statistics like call duration and bandwidth usage need to be tracked for each flow for billing purposes. 2) Testing was conducted injecting a 10Gbps mobile traffic profile of 1 million flows into OVS, with 200k flows created and destroyed per second. Key metrics measured were maximum throughput, latency, and jitter at different flow table sizes and core counts. 3) Conntrack performance was tested for OVS kernel and DPDK versions. For 100k flows, OVS kernel achieved 152k pps for 4-tuple matching while OVS-DPDK achieved

Quantum Computing and Qiskit

Pooja Mistry

The document discusses quantum computing and IBM's efforts in the field. It provides an overview of quantum computing concepts like superposition and entanglement. It describes IBM's superconducting qubit technology and how qubits can be controlled and entangled. The document outlines IBM's quantum computing platforms including the IBM Quantum Experience for experimenting with quantum circuits in the cloud. It encourages users to get involved with the Qiskit open source framework and global quantum computing community.

Advancements in the Real-Time Simulation of Large Active Distribution Systems...

OPAL-RT TECHNOLOGIES

This document discusses how real-time simulation technologies can help test phasor measurement units (PMUs) and PMU applications. It outlines different solvers for real-time digital simulators including real-time phasor simulation and electromagnetic transient simulation. It also discusses communication protocols supported by real-time simulators and gives examples of how utilities and researchers are using real-time simulators to develop and test PMUs, including simulating large distribution systems of over 750 nodes.

Planqc2020 codar

Yu Zhang

QCrypt

dalgetty

This project aims to considerably improve cryptography on both the key distribution level and the encryption level. Quantum Key Distribution (QKD) is a secure way to generate and distribute keys, which is based on the fundamental laws of quantum mechanics. However, existing systems are too slow. The new QKD system will be capable of producing keys at 1 Mbps rate, which means it will allow 1 MHz OTP encryption for high-level applications.

Pushing the limits of CAN - Scheduling frames with offsets provides a major p...

Nicolas Navet

Similar to Quantum Computing in China: Progress on Superconducting Multi-Qubits System (20)

Virus, Vaccines, Genes and Quantum - 2020-06-18

TCP congestion control

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Aritra Sarkar - Search and Optimisation Algorithms for Genomics on Quantum Ac...

Quantum Computing

XPDS13: On Paravirualizing TCP - Congestion Control on Xen VMs - Luwei Cheng,...

開発者が語る NVIDIA cuQuantum SDK

A Robust UART Architecture Based on Recursive Running Sum Filter for Better N...

What is Quantum Computing and Why it is Important

Resume_Karthik_Koneru_Analog_and_Mixed Signal

IQM slide pitch deck

Computer network (13)

LF_OVS_17_OVS/OVS-DPDK connection tracking for Mobile usecases

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Advancements in the Real-Time Simulation of Large Active Distribution Systems...

Planqc2020 codar

QCrypt

Pushing the limits of CAN - Scheduling frames with offsets provides a major p...

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Major Market Shifts in IT

The document discusses the top 5 technologies that all organizations must understand: digital transformation, quantum computing, IoT, 5G, and AI/HPC. It provides an overview of each technology including opportunities and threats to organizations. The document emphasizes that understanding these emerging technologies is mandatory as the information revolution changes many aspects of life and business.

Preparing to program Aurora at Exascale - Early experiences and future direct...

In this deck from IWOCL / SYCLcon 2020, Hal Finkel from Argonne National Laboratory presents: Preparing to program Aurora at Exascale - Early experiences and future directions. "Argonne National Laboratory’s Leadership Computing Facility will be home to Aurora, our first exascale supercomputer. Aurora promises to take scientific computing to a whole new level, and scientists and engineers from many different fields will take advantage of Aurora’s unprecedented computational capabilities to push the boundaries of human knowledge. In addition, Aurora’s support for advanced machine-learning and big-data computations will enable scientific workflows incorporating these techniques along with traditional HPC algorithms. Programming the state-of-the-art hardware in Aurora will be accomplished using state-of-the-art programming models. Some of these models, such as OpenMP, are long-established in the HPC ecosystem. Other models, such as Intel’s oneAPI, based on SYCL, are relatively-new models constructed with the benefit of significant experience. Many applications will not use these models directly, but rather, will use C++ abstraction libraries such as Kokkos or RAJA. Python will also be a common entry point to high-performance capabilities. As we look toward the future, features in the C++ standard itself will become increasingly relevant for accessing the extreme parallelism of exascale platforms. This presentation will summarize the experiences of our team as we prepare for Aurora, exploring how to port applications to Aurora’s architecture and programming models, and distilling the challenges and best practices we’ve developed to date. oneAPI/SYCL and OpenMP are both critical models in these efforts, and while the ecosystem for Aurora has yet to mature, we’ve already had a great deal of success. Importantly, we are not passive recipients of programming models developed by others. Our team works not only with vendor-provided compilers and tools, but also develops improved open-source LLVM-based technologies that feed both open-source and vendor-provided capabilities. In addition, we actively participate in the standardization of OpenMP, SYCL, and C++. To conclude, I’ll share our thoughts on how these models can best develop in the future to support exascale-class systems." Watch the video: https://wp.me/p3RLHQ-lPT Learn more: https://www.iwocl.org/iwocl-2020/conference-program/ and https://www.anl.gov/topic/aurora Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Transforming Private 5G Networks

In this deck, Greg Wahl from Advantech presents: Transforming Private 5G Networks. Advantech Networks & Communications Group is driving innovation in next-generation network solutions with their High Performance Servers. We provide business critical hardware to the world's leading telecom and networking equipment manufacturers with both standard and customized products. Our High Performance Servers are highly configurable platforms designed to balance the best in x86 server-class processing performance with maximum I/O and offload density. The systems are cost effective, highly available and optimized to meet next generation networking and media processing needs. “Advantech’s Networks and Communication Group has been both an innovator and trusted enabling partner in the telecommunications and network security markets for over a decade, designing and manufacturing products for OEMs that accelerate their network platform evolution and time to market.” Said Advantech Vice President of Networks & Communications Group, Ween Niu. “In the new IP Infrastructure era, we will be expanding our expertise in Software Defined Networking (SDN) and Network Function Virtualization (NFV), two of the essential conduits to 5G infrastructure agility making networks easier to install, secure, automate and manage in a cloud-based infrastructure.” In addition to innovation in air interface technologies and architecture extensions, 5G will also need a new generation of network computing platforms to run the emerging software defined infrastructure, one that provides greater topology flexibility, essential to deliver on the promises of high availability, high coverage, low latency and high bandwidth connections. This will open up new parallel industry opportunities through dedicated 5G network slices reserved for specific industries dedicated to video traffic, augmented reality, IoT, connected cars etc. 5G unlocks many new doors and one of the keys to its enablement lies in the elasticity and flexibility of the underlying infrastructure. Advantech’s corporate vision is to enable an intelligent planet. The company is a global leader in the fields of IoT intelligent systems and embedded platforms. To embrace the trends of IoT, big data, and artificial intelligence, Advantech promotes IoT hardware and software solutions with the Edge Intelligence WISE-PaaS core to assist business partners and clients in connecting their industrial chains. Advantech is also working with business partners to co-create business ecosystems that accelerate the goal of industrial intelligence." Watch the video: https://wp.me/p3RLHQ-lPQ * Company website: https://www.advantech.com/ * Solution page: https://www2.advantech.com/nc/newsletter/NCG/SKY/benefits.html Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

The Incorporation of Machine Learning into Scientific Simulations at Lawrence...

In this deck from the Stanford HPC Conference, Katie Lewis from Lawrence Livermore National Laboratory presents: The Incorporation of Machine Learning into Scientific Simulations at Lawrence Livermore National Laboratory. "Scientific simulations have driven computing at Lawrence Livermore National Laboratory (LLNL) for decades. During that time, we have seen significant changes in hardware, tools, and algorithms. Today, data science, including machine learning, is one of the fastest growing areas of computing, and LLNL is investing in hardware, applications, and algorithms in this space. While the use of simulations to focus and understand experiments is well accepted in our community, machine learning brings new challenges that need to be addressed. I will explore applications for machine learning in scientific simulations that are showing promising results and further investigation that is needed to better understand its usefulness." Watch the video: https://youtu.be/NVwmvCWpZ6Y Learn more: https://computing.llnl.gov/research-area/machine-learning and http://www.hpcadvisorycouncil.com/events/2020/stanford-workshop/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

How to Achieve High-Performance, Scalable and Distributed DNN Training on Mod...

In this deck from the Stanford HPC Conference, DK Panda from Ohio State University presents: How to Achieve High-Performance, Scalable and Distributed DNN Training on Modern HPC Systems? "This talk will start with an overview of challenges being faced by the AI community to achieve high-performance, scalable and distributed DNN training on Modern HPC systems with both scale-up and scale-out strategies. After that, the talk will focus on a range of solutions being carried out in my group to address these challenges. The solutions will include: 1) MPI-driven Deep Learning, 2) Co-designing Deep Learning Stacks with High-Performance MPI, 3) Out-of- core DNN training, and 4) Hybrid (Data and Model) parallelism. Case studies to accelerate DNN training with popular frameworks like TensorFlow, PyTorch, MXNet and Caffe on modern HPC systems will be presented." Watch the video: https://youtu.be/LeUNoKZVuwQ Learn more: http://web.cse.ohio-state.edu/~panda.2/ and http://www.hpcadvisorycouncil.com/events/2020/stanford-workshop/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Evolving Cyberinfrastructure, Democratizing Data, and Scaling AI to Catalyze ...

In this deck from the Stanford HPC Conference, Nick Nystrom and Paola Buitrago provide an update from the Pittsburgh Supercomputing Center. Nick Nystrom is Chief Scientist at the Pittsburgh Supercomputing Center (PSC). Nick is architect and PI for Bridges, PSC's flagship system that successfully pioneered the convergence of HPC, AI, and Big Data. He is also PI for the NIH Human Biomolecular Atlas Program’s HIVE Infrastructure Component and co-PI for projects that bring emerging AI technologies to research (Open Compass), apply machine learning to biomedical data for breast and lung cancer (Big Data for Better Health), and identify causal relationships in biomedical big data (the Center for Causal Discovery, an NIH Big Data to Knowledge Center of Excellence). His current research interests include hardware and software architecture, applications of machine learning to multimodal data (particularly for the life sciences) and to enhance simulation, and graph analytics. Watch the video: https://youtu.be/LWEU1L1o7yY Learn more: https://www.psc.edu/ and http://www.hpcadvisorycouncil.com/events/2020/stanford-workshop/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

HPC Impact: EDA Telemetry Neural Networks

The document discusses using systems intelligence and artificial intelligence/neural networks to enhance semiconductor electronic design automation (EDA) workflows by collecting telemetry data from EDA jobs and infrastructure and analyzing it using complex event processing, machine learning models, and messaging substrates to provide insights that could optimize EDA pipelines and infrastructure. The approach aims to allow both internal and external augmentation of EDA processes and environments through unsupervised and incremental learning.

Biohybrid Robotic Jellyfish for Future Applications in Ocean Monitoring

In this deck from the Stanford HPC Conference, Nicole Xu from Stanford University describes how she transformed a common jellyfish into a bionic creature that is part animal and part machine. "Animal locomotion and bioinspiration have the potential to expand the performance capabilities of robots, but current implementations are limited. Mechanical soft robots leverage engineered materials and are highly controllable, but these biomimetic robots consume more power than corresponding animal counterparts. Biological soft robots from a bottom-up approach offer advantages such as speed and controllability but are limited to survival in cell media. Instead, biohybrid robots that comprise live animals and self- contained microelectronic systems leverage the animals’ own metabolism to reduce power constraints and body as an natural scaffold with damage tolerance. We demonstrate that by integrating onboard microelectronics into live jellyfish, we can enhance propulsion up to threefold, using only 10 mW of external power input to the microelectronics and at only a twofold increase in cost of transport to the animal. This robotic system uses 10 to 1000 times less external power per mass than existing swimming robots in literature and can be used in future applications for ocean monitoring to track environmental changes." Watch the video: https://youtu.be/HrmJFyvInj8 Learn more: https://sanfrancisco.cbslocal.com/2020/02/05/stanford-research-project-common-jellyfish-bionic-sea-creatures/ and http://www.hpcadvisorycouncil.com/events/2020/stanford-workshop/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Machine Learning for Weather Forecasts

In this deck from the Stanford HPC Conference, Peter Dueben from the European Centre for Medium-Range Weather Forecasts (ECMWF) presents: Machine Learning for Weather Forecasts. "I will present recent studies that use deep learning to learn the equations of motion of the atmosphere, to emulate model components of weather forecast models and to enhance usability of weather forecasts. I will than talk about the main challenges for the application of deep learning in cutting-edge weather forecasts and suggest approaches to improve usability in the future." Peter is contributing to the development and optimization of weather and climate models for modern supercomputers. He is focusing on a better understanding of model error and model uncertainty, on the use of reduced numerical precision that is optimised for a given level of model error, on global cloud- resolving simulations with ECMWF's forecast model, and the use of machine learning, and in particular deep learning, to improve the workflow and predictions. Peter has graduated in Physics and wrote his PhD thesis at the Max Planck Institute for Meteorology in Germany. He worked as Postdoc with Tim Palmer at the University of Oxford and has taken up a position as University Research Fellow of the Royal Society at the European Centre for Medium-Range Weather Forecasts (ECMWF) in 2017. Watch the video: https://youtu.be/ks3fkRj8Iqc Learn more: https://www.ecmwf.int/ and http://www.hpcadvisorycouncil.com/events/2020/stanford-workshop/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

HPC AI Advisory Council Update

In this deck, Gilad Shainer from the HPC AI Advisory Council describes how this organization fosters innovation in the high performance computing community. "The HPC-AI Advisory Council’s mission is to bridge the gap between high-performance computing (HPC) and Artificial Intelligence (AI) use and its potential, bring the beneficial capabilities of HPC and AI to new users for better research, education, innovation and product manufacturing, bring users the expertise needed to operate HPC and AI systems, provide application designers with the tools needed to enable parallel computing, and to strengthen the qualification and integration of HPC and AI system products." Watch the video: https://wp.me/p3RLHQ-lNz Learn more: http://hpcadvisorycouncil.com Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Fugaku Supercomputer joins fight against COVID-19

Today RIKEN in Japan announced that the Fugaku supercomputer will be made available for research projects aimed to combat COVID-19. "Fugaku is currently being installed and is scheduled to be available to the public in 2021. However, faced with the devastating disaster unfolding before our eyes, RIKEN and MEXT decided to make a portion of the computational resources of Fugaku available for COVID-19-related projects ahead of schedule while continuing the installation process. Fugaku is being developed not only for the progress in science, but also to help build the society dubbed as the “Society 5.0” by the Japanese government, where all people will live safe and comfortable lives. The current initiative to fight against the novel coronavirus is driven by the philosophy behind the development of Fugaku." Initial Projects Exploring new drug candidates for COVID-19 by "Fugaku" Yasushi Okuno, RIKEN / Kyoto University Prediction of conformational dynamics of proteins on the surface of SARS-Cov-2 using Fugaku Yuji Sugita, RIKEN Simulation analysis of pandemic phenomena Nobuyasu Ito, RIKEN Fragment molecular orbital calculations for COVID-19 proteins Yuji Mochizuki, Rikkyo University

Energy Efficient Computing using Dynamic Tuning

In this deck from the Performance Optimisation and Productivity group, Lubomir Riha from IT4Innovations presents: Energy Efficient Computing using Dynamic Tuning. "We now live in a world of power-constrained architectures and systems and power consumption represents a significant cost factor in the overall HPC system economy. For these reasons, in recent years researchers, supercomputing centers and major vendors have developed new tools and methodologies to measure and optimize the energy consumption of large-scale high performance system installations. Due to the link between energy consumption, power consumption and execution time of an application executed by the final user, it is important for these tools and the methodology used to consider all these aspects, empowering the final user and the system administrator with the capability of finding the best configuration given different high level objectives. This webinar focused on tools designed to improve the energy-efficiency of HPC applications using a methodology of dynamic tuning of HPC applications, developed under the H2020 READEX project. The READEX methodology has been designed for exploiting the dynamic behaviour of software. At design time, different runtime situations (RTS) are detected and optimized system configurations are determined. RTSs with the same configuration are grouped into scenarios, forming the tuning model. At runtime, the tuning model is used to switch system configurations dynamically. The MERIC tool, that implements the READEX methodology, is presented. It supports manual or binary instrumentation of the analysed applications to simplify the analysis. This instrumentation is used to identify and annotate the significant regions in the HPC application. Automatic binary instrumentation annotates regions with significant runtime. Manual instrumentation, which can be combined with automatic, allows code developer to annotate regions of particular interest." Watch the video: https://wp.me/p3RLHQ-lJP Learn more: https://pop-coe.eu/blog/14th-pop-webinar-energy-efficient-computing-using-dynamic-tuning and https://code.it4i.cz/vys0053/meric Sign up for our insideHPC Newsletter: http://insidehpc.com/newslett

HPC at Scale Enabled by DDN A3i and NVIDIA SuperPOD

The document discusses how DDN A3I storage solutions and Nvidia's SuperPOD platform can enable HPC at scale. It provides details on DDN's A3I appliances that are optimized for AI and deep learning workloads and validated for Nvidia's DGX-2 SuperPOD reference architecture. The solutions are said to deliver the fastest performance, effortless scaling, reliability and flexibility for data-intensive workloads.

State of ARM-based HPC

In this deck, Paul Isaacs from Linaro presents: State of ARM-based HPC. This talk provides an overview of applications and infrastructure services successfully ported to Aarch64 and benefiting from scale. "With its debut on the TOP500, the 125,000-core Astra supercomputer at New Mexico’s Sandia Labs uses Cavium ThunderX2 chips to mark Arm’s entry into the petascale world. In Japan, the Fujitsu A64FX Arm-based CPU in the pending Fugaku supercomputer has been optimized to achieve high-level, real-world application performance, anticipating up to one hundred times the application execution performance of the K computer. K was the first computer to top 10 petaflops in 2011." Watch the video: https://wp.me/p3RLHQ-lIT Learn more: https://www.linaro.org/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Versal Premium ACAP for Network and Cloud Acceleration

Today Xilinx announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry’s highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration. Versal is the industry’s first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC’s 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to- market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads. Learn more: https://insidehpc.com/2020/03/xilinx-announces-versal-premium-acap-for-network-and-cloud-acceleration/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Zettar: Moving Massive Amounts of Data across Any Distance Efficiently

In this video from the Rice Oil & Gas Conference, Chin Fang from Zettar presents: Moving Massive Amounts of Data across Any Distance Efficiently. The objective of this talk is to present two on-going projects aiming at improving and ensuring highly efficient bulk transferring or streaming of massive amounts of data over digital connections across any distance. It examines the current state of the art, a few very common misconceptions, the differences among the three major type of data movement solutions, a current initiative attempting to improve the data movement efficiency from the ground up, and another multi-stage project that shows how to conduct long distance large scale data movement at speed and scale internationally. Both projects have real world motivations, e.g. the ambitious data transfer requirements of Linac Coherent Light Source II (LCLS-II) [1], a premier preparation project of the U.S. DOE Exascale Computing Initiative (ECI) [2]. Their immediate goals are described and explained, together with the solution used for each. Findings and early results are reported. Possible future works are outlined. Watch the video: https://wp.me/p3RLHQ-lBX Learn more: https://www.zettar.com/ and https://rice2020oghpc.rice.edu/program-2/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Scaling TCO in a Post Moore's Era

In this deck from the Rice Oil & Gas Conference, Bradley McCredie from AMD presents: Scaling TCO in a Post Moore's Law Era. "While foundries bravely drive forward to overcome the technical and economic challenges posed by scaling to 5nm and beyond, Moore’s law alone can provide only a fraction of the performance / watt and performance / dollar gains needed to satisfy the demands of today’s high performance computing and artificial intelligence applications. To close the gap, multiple strategies are required. First, new levels of innovation and design efficiency will supplement technology gains to continue to deliver meaningful improvements in SoC performance. Second, heterogenous compute architectures will create x-factor increases of performance efficiency for the most critical applications. Finally, open software frameworks, APIs, and toolsets will enable broad ecosystems of application level innovation." Watch the video: Learn more: http://amd.com and https://rice2020oghpc.rice.edu/program-2/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

CUDA-Python and RAPIDS for blazing fast scientific computing

In this deck from the ECSS Symposium, Abe Stern from NVIDIA presents: CUDA-Python and RAPIDS for blazing fast scientific computing. "We will introduce Numba and RAPIDS for GPU programming in Python. Numba allows us to write just-in-time compiled CUDA code in Python, giving us easy access to the power of GPUs from a powerful high-level language. RAPIDS is a suite of tools with a Python interface for machine learning and dataframe operations. Together, Numba and RAPIDS represent a potent set of tools for rapid prototyping, development, and analysis for scientific computing. We will cover the basics of each library and go over simple examples to get users started. Finally, we will briefly highlight several other relevant libraries for GPU programming." Watch the video: https://wp.me/p3RLHQ-lvu Learn more: https://developer.nvidia.com/rapids and https://www.xsede.org/for-users/ecss/ecss-symposium Sign up for our insideHPC Newsletter: http://insidehp.com/newsletter

Introducing HPC with a Raspberry Pi Cluster

In this deck from FOSDEM 2020, Colin Sauze from Aberystwyth University describes the development of a RaspberryPi cluster for teaching an introduction to HPC. "The motivation for this was to overcome four key problems faced by new HPC users: * The availability of a real HPC system and the effect running training courses can have on the real system, conversely the availability of spare resources on the real system can cause problems for the training course. * A fear of using a large and expensive HPC system for the first time and worries that doing something wrong might damage the system. * That HPC systems are very abstract systems sitting in data centres that users never see, it is difficult for them to understand exactly what it is they are using. * That new users fail to understand resource limitations, in part because of the vast resources in modern HPC systems a lot of mistakes can be made before running out of resources. A more resource constrained system makes it easier to understand this. The talk will also discuss some of the technical challenges in deploying an HPC environment to a Raspberry Pi and attempts to keep that environment as close to a "real" HPC as possible. The issue to trying to automate the installation process will also be covered." Learn more: https://github.com/colinsauze/pi_cluster and https://fosdem.org/2020/schedule/events/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

Overview of HPC Interconnects

In this deck from ATPESC 2019, Ken Raffenetti from Argonne presents an overview of HPC interconnects. "The Argonne Training Program on Extreme-Scale Computing (ATPESC) provides intensive, two-week training on the key skills, approaches, and tools to design, implement, and execute computational science and engineering applications on current high-end computing systems and the leadership-class computing systems of the future." Watch the video: https://wp.me/p3RLHQ-luc Learn more: https://extremecomputingtraining.anl.gov/ Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter

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