This document provides design specifications and considerations for a fixed frequency switch mode power supply using the FA5311BP controller. It discusses the flyback converter topology, current waveforms, and key equations. The specifications section outlines the targeted output voltage, current, initial conditions, ripple voltage, and efficiency. Subsequent sections explore design parameters like input voltage, transformer characteristics, switching devices, output capacitors, and more. The document aims to guide the design of a power supply meeting the defined specifications.

1. Design Kit
Fixed Frequency Switch Mode Power Supply Using
FA5311BP
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 1

2. Contents (1/2)
Slide #
1. Background
1.1 Flyback Converter................................................................................................ 4-6
1.2 Current Waveforms.............................................................................................. 7
1.3 Equations............................................................................................................. 8
2. Specification............................................................................................................... 9
2.1 Output Voltage..................................................................................................... 10
2.2 Output Current..................................................................................................... 11
2.3 Steady State Initial Conditions............................................................................. 12
2.4 Output Ripple Voltage.......................................................................................... 13
2.5 Efficiency.............................................................................................................. 14
3. Design Consideration................................................................................................. 15
3.1 DC Link Voltage VDC,IN......................................................................................... 16
3.2 Reflected Voltage VRO.......................................................................................... 17
3.3 Transformer Primary Side Inductance LP............................................................. 18
3.4 Transformer Turn Ratio........................................................................................ 19-20
3.5 Transformer Leakage Inductance Lleak................................................................. 21-23
3.6 RCD Clamping Network....................................................................................... 24-25
4. MOSFET Switching Device M1................................................................................... 26
4.1 M1 Voltage and Current Stresses......................................................................... 27
4.2 Losses in M1........................................................................................................ 28
4.3 MOSFET Model................................................................................................... 29
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 2

3. Contents (2/2)
Slide #
5. Output Rectifier Diode D21........................................................................................... 30
5.1 D21 Voltage and Current Stresses........................................................................ 31
5.2 Losses in D21....................................................................................................... 32
6. Output Capacitor C21 and C22...................................................................................... 33-35
7. Photocoupler PC1........................................................................................................ 35-36
Simulation Index.............................................................................................................. 38-39
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 3

4. 1.1 Flyback Converter
Vin Iin VLS IF,D21 VOUT
LP LS D21
+
VLP
-
M1 LC filter stage
+
VDS
-
• This figure shows the basic configuration of the converter ( Flyback + LCR load ).
• The switch M1 ON and OFF events are separated to see how the devices work.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 4

5. 1.1 Flyback Converter
During the M1 ON time
Vin
D21
LS
VLS = Vin Reverse
Bias
LP
M1 LC filter stage
ON
• This figure shows the current path during the ON time, D21 is reverse biased, and the
output capacitor (C21) supplies the LC filter stage on its own.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 5

6. 1.1 Flyback Converter
During the M1 OFF time
VLS = N ⋅ Vin VOUT
D21
LP LS
VOUT
M1 VDS = Vin +
N
OFF
• During the OFF time, D21 is forward biased , LS starts conducting and charges
C21 ,the secondary winding of the flyback transformer starts transferring energy to the
power supply output.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 6

7. 1.2 Current Waveforms
CCM DCM
Vin × ΤΟΝ
Iin ΔΙin = Iin
Lp
Vin × ΤΟΝ
ΔΙin =
Lp
Vin × ΤΟN Vin × ΤΟN
IF,D21 ΔΙF , D 21 = IF,D21 ΔΙF , D 21 =
N × Lp N × Lp
ΤΟN ΤΟN
Τ
Τ time time
Discontinuous
current
• The current waveforms of Iin and IF,D21 in CCM and DCM mode.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 7

8. 1.3 Equations
• The relationship between the VOUT and Vin for the CCM and DCM mode are defined as equations
below.
NS  D  (1)
VOUT , CCM = ⋅  ⋅ Vin
NP  1 − D 
RL
VOUT , DCM = D × Vin × (2)
2 × LP × fsw
• The primary side inductance value LP for the DCM mode is calculated as equation below.
LP , DCM <
(1 − D )2 R ⋅  NP  2

(3)
2 fS  N S

• LP is the inductance of primary winding.
• D = TON/T
• NP is the turns number of primary winding.
• NS is the turns number of secondary winding.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 8

9. 2. Specifications
K K1
K_Linear
COUPLING = {K}
L1 = Lp
L2 = Ls
L3 = LsubD21
Rs_Lp SF6L20U L21
OUT
0.15 8RHB
C2 2 1 C21 C22
R2 0.022u 890uF 890uF
33k
D1 + ESR21 ESR22 2.2k + 12
D4 C3 Lp Ls 33m 33m R23 RL
D2SBA60 C1 R1 150p {Lp} {Nsp*Nsp*Lp} 1 1 C23
SMH200VN270-22A 22k RJJ-35V221MG5-T20
1 2
1
2
3
4
IC = 0 D ESL21 ESL22 IC = 0
MUR160 6.3nH 6.3nH
M1
2SK3869
G ERA91-02
R3 D2 2 2
Vac 4.7k PARAMETERS:
FREQ = 50Hz S 2 Np = 125 R21
PC1_A
VAMPL = {110*1.4142} 18k
R7 Ns = 24 R26
2.2 Nsub = 14 2.2k
R4 Lp = 650uH PC1_K
220 R22
R8 C4 Nsp = {Ns/Np} 1.9k
0.22 DZ1 1 R24
47u Nsubp = {Nsub/Np}
680
D3 Lsub K = 0.996055
ERA91-02 {Nsubp*Nsubp*Lp}
0 C8 R9 MTZJ24B K R25 C24
0.22u 100 330k 0.22u
IC = 0 IC2 REF
C7 NJM431
1500p
A
R27
2.2k
R5 IC1
8 7 6 5
220 FA5311BP
VIN = 110Vrms 0
1 2 3 4
C5 PC1_A
VOUT = 24V
220 0.047u
R6
IOUT = 2A , DCM
R10 C6 R11 PC1_K
2.2k
PC1 fSW = 30kHz
5.6k 6800p TLP281
Output voltage ripple < 0.06VP-P
%Efficiency = 85.6
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 9

10. 2.1 Output Voltage
Analysis
Overshoot voltage Time Domain (Transient)
Run to time: 500ms
Start saving data after: 0
Maximum step size: 10us
.Options
RELTOL: 0.01
VNTOL: 1.0m
ABSTOL: 100.0n
CHGTOL: 1p
GMIN: 1.0E-12
ITL1: 500
ITL2: 200
ITL4: 20
• The output voltage is regulated at 24V(RL=12Ω) ,voltage overshoot at startup is less than 1.2V.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 10

11. 2.2 Output Current
Analysis
Time Domain (Transient)
Run to time: 500ms
Overshoot current Start saving data after: 0
Maximum step size: 10us
.Options
RELTOL: 0.01
VNTOL: 1.0m
ABSTOL: 100.0n
CHGTOL: 1p
GMIN: 1.0E-12
ITL1: 500
ITL2: 200
ITL4: 20
• The output current is 2A (RL=12Ω) ,current overshoot at startup is less than 100mA.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 11

12. 2.3 Steady State Initial Conditions
K K1
K_Linear
COUPLING = {K}
L1 = Lp
L2 = Ls
L3 = LsubD21
Vin_dc
Rs_Lp SF6L20U L21
Vin_dc OUT
0.15 8RHB
C2 2 1 C21 C22
IC(C1) = R2
33k
0.022u 890uF 890uF
D1 + 30V D4 C3 Lp Ls
ESR21
33m
ESR22
33m
2.2k
R23
+ 12
RL
D2SBA60 C1 R1 150p {Lp} {Nsp*Nsp*Lp} 1 1 C23
SMH200VN270-22A 22k RJJ-35V221MG5-T20
1 2 IC(C23)
1
2
3
4
IC = 141.4 D ESL21 ESL22 IC = 23.9
MUR160 6.3nH 6.3nH
M1 = 23.9V
2SK3869
G ERA91-02
R3 D2 2 2
Vac 4.7k PARAMETERS:
FREQ = 50Hz S 2 Np = 125 R21
PC1_A
VAMPL = {110*1.4142} 18k
R7 Ns = 24 R26
PHASE = 30 MTZJ24B 2.2 Nsub = 14 2.2k
R4
Initial 220
Lp = 650uH PC1_K
R22
R8 Nsp = {Ns/Np} 1.9k
phase 0.22 DZ1 1
Nsubp = {Nsub/Np} R24
680
= 30 D3 C4 Lsub K = 0.996055
C8 ERA91-02 47u {Nsubp*Nsubp*Lp}
0 0.22u R9 IC = 16.524 K R25 C24
IC = 2.42 100 330k 0.22u
IC(C8) = C7
IC(C4) = IC2 REF
2.42V
1500p
IC = 2.9
IC(C7) 16.524V NJM431
A
= 2.9V R27
2.2k
R5 IC1
8 7 6 5
220 FA5311BP
IC(C5)
= 3.37V
0
1 2 3 4
220
C5
0.047u
PC1_A Initial condition are set ,so the
R6
IC = 3.37
simulation starts near the steady
R10 R11
C6 2.2k
PC1
PC1_K
state.
5.6k 6800p TLP281
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 12

13. 2.4 Output Ripple Voltage
Output ripple voltage
Analysis
Time Domain (Transient)
Run to time: 60ms
Start saving data after: 40ms
Maximum step size: 100ns
.Options
RELTOL: 0.01
VNTOL: 1.0m
ABSTOL: 100.0n
CHGTOL: 0.1p
GMIN: 1.0E-12
ITL1: 500
ITL2: 200
ITL4: 20
• The output ripple voltage is less than 60 mVP-P.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 13

14. 2.5 Efficiency
 Tracing the %Efficiency of the power supply ,add trace: 100* AVG(W(RL))/ AVG(V(Vin_dc)*I(Vin_dc))
Ploss(M1)= 4.64[W]
Analysis
Time Domain (Transient)
Ploss(D21)= 1.92[W] Run to time: 60ms
Start saving data after: 40ms
Maximum step size: 100ns
Pin= 55.7[W] .Options
RELTOL: 0.01
Pout= 47.68[W] VNTOL: 1.0m
ABSTOL: 100.0n
CHGTOL: 0.1p
GMIN: 1.0E-12
%Efficiency = 85.6
ITL1: 500
ITL2: 200
ITL4: 20
 Tracing the %Efficiency of the power supply ,add trace: 100*
AVG(W(RL))/ AVG(V(Vin_dc)*I(Vin_dc))
• The simulation result shows that the efficiency of the power supply is 85.6%.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 14

15. 3. Design Considerations
K K1
K_Linear
VIN ,DC COUPLING = {K}
L1 = Lp
L2 = Ls VOUT
L3 = LsubD21
Vin_dc
Rs_Lp SF6L20U L21
Vin_dc OUT
- R2
C2
0.022u
0.15
2 1 C21
890uF
C22
890uF
8RHB
VRO
33k
D1 + ESR21 ESR22 2.2k + 12
D4 C3 Lp Ls 33m 33m R23 RL
D2SBA60 C1
SMH200VN270-22A + R1
22k
150p {Lp}
1 2
{Nsp*Nsp*Lp} 1 1 C23
RJJ-35V221MG5-T20
1
2
3
4
IC = 141.4 D ESL21 ESL22 IC = 23.9
+ M1
MUR160 6.3nH 6.3nH
2SK3869
VDS R3
G ERA91-02
D2 2 2
Vac
FREQ = 50Hz - S
4.7k
2
PARAMETERS:
Np = 125 PC1_A R21
18k
VAMPL = {110*1.4142} Ns = 24
R7 R26
PHASE = 30 MTZJ24B 2.2 Nsub = 14 2.2k
R4 Lp = 650uH PC1_K
220 R22
R8 Nsp = {Ns/Np} 1.8k
0.22 DZ1 1 R24
Nsubp = {Nsub/Np}
680
D3 C4 Lsub K = 0.996055
C8 ERA91-02 47u {Nsubp*Nsubp*Lp}
0 0.22u R9 IC = 16.524 R25 C24
IC = 2.42 100 330k 0.22u
C7 IC2
1500p TL431
IC = 2.9 Lp =650uH R27
R5
8 7 6 5
IC1 NP:NS:NSUB = 125:24:14 2.2k
220 FA5311BP
0
1 2 3 4
C5 PC1_A
220 0.047u
IC = 3.37
R6
R10 R11 PC1_K
C6 2.2k
PC1
5.6k 6800p TLP281
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 15

16. 3.1 DC Link Voltage VIN,DC
Maximum VIN ,DC = 154V
Analysis
Time Domain (Transient)
Run to time: 500ms
Minimum VIN ,DC = 139V Start saving data after: 0
Maximum step size: 10us
.Options
RELTOL: 0.01
VLINE, = 110Vac VNTOL: 1.0m
ABSTOL: 100.0n
CHGTOL: 1p
GMIN: 1.0E-12
ITL1: 500
ITL2: 200
ITL4: 20
• The simulation result shows the peak values of the ripple of DC link voltage VIN,DC.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 16

17. 3.2 Reflected Voltage VRO
VDS(M1) = VDC,IN + VRO = 283V Zoomed
Analysis
VRO = 153.71V Time Domain (Transient)
VDC,IN Run to time: 60ms
Start saving data after: 40ms
Maximum step size: 100ns
.Options
RELTOL: 0.01
VNTOL: 1.0m
ABSTOL: 100.0n
CHGTOL: 0.1p
VDS(M1) GMIN: 1.0E-12
VDC,IN ITL1: 500
ITL2: 200
ITL4: 20
• This figure shows the waveform of the drain voltage of flyback converter compared to the VDC,IN.
• When M1 is turned off ,VDS = VDC,IN + VRO
• VRO is the voltage reflected to the primary, the value is approximately VOUT / N ,which N=NS/NP
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 17

18. 3.3 Transformer Primary Side Inductance LP
Analysis
Time Domain (Transient)
Run to time: 60ms
Start saving data after: 40ms
ΤΟN
Maximum step size: 100ns
Τ V(PWM_OUT)
.Options
RELTOL: 0.01
ID(M1) = VDC,IN TON /Lp= 2.34A VNTOL: 1.0m
IF(D21) = 11.667A ABSTOL: 100.0n
CHGTOL: 0.1p
Discontinuous GMIN: 1.0E-12
current ITL1: 500
ITL2: 200
ITL4: 20
• This figure shows the waveforms of ID(M1) and IF(D21 ) in the DCM mode. The peak currents are obtained.
• The primary-side inductance (LP) of the transformer determines the converter operation mode.
• Once the duty ratio is determined by the equation (1), LP is obtained as the equation (3)
• Which the maximum load is 2A (VO=24V, RL=12Ω). At VIN,dc=141V and fs=30kHz ,this equation calls for Lp,DCM <
1.52mH.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 18

19. 3.4 Transformer Turn Ratio
The turn ratio between the primary side and the secondary side is obtained as:
NS VOUT + VF ( D 21)
= (4)
NP VRO
The turn ratio between the primary side and the auxiliary side is obtained as:
NSUB VCC + VF ( Dsub )
= (5)
NS VOUT + VF ( D 21)
Which the maximum load current is 2A (VO=24V, RL=12Ω).
• At VF(D21)≅0.6V and VRO=129V ,this equation calls for NP:NS = 125:24.
• At VF(Dsub)≅0.6V and VCC=14V (more than VCC,OFF of FA5311BP) ,this equation calls for
NS:NSUB = 24:14.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 19

20. 3.4 Transformer Turn Ratio
VP = 275V
VP
Analysis
Time Domain (Transient)
Run to time: 60ms
Start saving data after: 40ms
VS = 52.8V Maximum step size: 100ns
VS .Options
RELTOL: 0.01
VNTOL: 1.0m
ABSTOL: 100.0n
CHGTOL: 0.1p
VSUB = 30.8V
GMIN: 1.0E-12
VSUB ITL1: 500
ITL2: 200
ITL4: 20
• This figure shows the waveforms of the voltages at each side of the transformer.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 20

21. 3.5 Transformer leakage inductance
• To model the transformer (or coupled inductors), we can use the SPICE primitive k ,which
describes the coupling ratio between a primary and a secondary.
• The k value is obtained as:
LP , LSS
k = 1− (6)
LP , LSO
• k is the SPICE primitive which describes the coupling ratio between a primary and a
secondary.
• LP,LSS is the Inductance value of primary winding when the secondary winding is shorted.
• LP,LSS is the Inductance value of primary winding when the secondary winding is opened.
• The leakage inductance of the transformer Lleak is describe as equation:
Lleak = LP ⋅ (1 − k 2 ) (7)
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 21

22. 3.5 Transformer leakage inductance
K K1
K_Linear
COUPLING = {K}
L1 = Lp SPICE primitive k
L2 = Ls
L3 = LsubD21
Rs_Lp SF6L20U L21
OUT
0.15 8RHB
C2 2 1 C21 C22
R2 0.022u 890uF 890uF
33k
D1 + ESR21 ESR22 2.2k + 12
D4 C3 Lp Ls 33m 33m R23 RL
D2SBA60 C1 R1 150p {Lp} {Nsp*Nsp*Lp} 1 1 C23
SMH200VN270-22A 22k RJJ-35V221MG5-T20
1 2
1
2
3
4
IC = 154 D ESL21 ESL22 IC = 23.9
MUR160 6.3nH 6.3nH
M1
2SK3869
G ERA91-02
R3 D2 2 2
4.7k PARAMETERS:
Vac S 2 Np = 125 R21
PC1_A
FREQ = 50Hz 18k
VAMPL = {110*1.4142} R7 Ns = 24 R26
PHASE = 30 2.2 Nsub = 14 2.2k
R4 Lp = 650uH PC1_K
220 R22
R8 C4 Nsp = {Ns/Np} 1.8k
0.22 DZ1 47u 1 R24
Nsubp = {Nsub/Np}
IC = 22 680
D3 Lsub K = 0.996055
ERA91-02 {Nsubp*Nsubp*Lp}
0 C8 R9 MTZJ24B K R25 C24
0.22u 100 330k 0.22u
IC = 2.42 IC2 REF
1500p NJM431
C7
A
IC = 2.9 R27
2.2k
R5 IC1
8 7 6 5
220 FA5311BP
0
1 2 3 4
C5
Which LP is 650uH , Lleak is
PC1_A
220 0.047u
IC = 3.37
R10
R6
C6 R11
2.2k
PC1_K 5.1184uH for k=0.996055 and
5.6k 6800p
PC1
TLP281 25.74uH for k=0.98.
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 22

23. 3.5 Transformer leakage inductance
M1: VDSS=450V VDS,peak = 418V (for Lleak=25.74uH)
VDS,peak = 331V (for Lleak=5.1184uH)
Analysis
Time Domain (Transient)
M1: VDS(t) Run to time: 1000us
Start saving data after: 0
Maximum step size: 80ns
Sweep variable
 Global parameter: k
 Value list: 0.996055, 0.98
.Options
RELTOL: 0.01
VNTOL: 1.0m
ABSTOL: 100.0n
CHGTOL: 0.1p
GMIN: 1.0E-12
ITL1: 500
ITL2: 200
ITL4: 20
• Simulation result shows that the smaller Lleak gets lower VDS peak voltage ,that means better
design margin from the MOSFET VDSS
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 23

24. 3.6 RCD Clamping network
PARAMETERS: K K1
RCD Clamping Cclp = 0.022u K_Linear
COUPLING = {K}
Network CCLP L1 = Lp
L2 = Ls
L3 = LsubD21
Rs_Lp SF6L20U L21
OUT
0.15 8RHB
C2 2 1 C21 C22
R2 {Cclp} 890uF 890uF
33k
D1 + ESR21 ESR22 2.2k + 12
D4 C3 Lp Ls 33m 33m R23 RL
D2SBA60 C1 R1 150p {Lp} {Nsp*Nsp*Lp} 1 1 C23
SMH200VN270-22A 22k RJJ-35V221MG5-T20
1 2
1
2
3
4
IC = 154 D ESL21 ESL22 IC = 23.9
MUR160 6.3nH 6.3nH
M1
2SK3869
G ERA91-02
R3 D2 2 2
4.7k PARAMETERS:
Vac S 2 Np = 125 R21
PC1_A
FREQ = 50Hz 18k
VAMPL = {110*1.4142} R7 Ns = 24 R26
PHASE = 30 2.2 Nsub = 14 2.2k
R4 Lp = 650uH PC1_K
220 R22
R8 C4 Nsp = {Ns/Np} 1.8k
0.22 DZ1 47u 1 R24
Nsubp = {Nsub/Np}
IC = 22 680
D3 Lsub K = 0.996055
ERA91-02 {Nsubp*Nsubp*Lp}
0 C8 R9 MTZJ24B K R25 C24
0.22u 100 330k 0.22u
IC = 2.42 IC2 REF
1500p NJM431
C7
A
IC = 2.9 R27
2.2k
R5 IC1
8 7 6 5
220 FA5311BP
0
1 2 3 4
C5 PC1_A
220 0.047u
IC = 3.37
R6
R10 C6 R11 PC1_K
2.2k
PC1
5.6k 6800p TLP281
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 24

25. 3.6 RCD Clamping network
M1: VDSS=450V
Analysis
VDS,peak = 374V (for CCLP = 1000pF) Time Domain (Transient)
Run to time: 500us
VDS,peak = 332V (for CCLP = 0.022uF) Start saving data after: 0
Maximum step size: 40ns
Sweep variable
 Global parameter: Cclp
 Value list: 0.022u, 1000p
M1: VDS(t)
.Options
RELTOL: 0.01
VNTOL: 1.0m
ABSTOL: 100.0n
CHGTOL: 0.1p
GMIN: 1.0E-12
ITL1: 500
ITL2: 200
ITL4: 20
• Simulation result shows VDS peak voltages for the CCLP(C2) = 0.022uF and 1000pF.
• A larger CCLP value gets lower VDS peak voltage ,that means better design margin from the
MOSFET VDSS
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 25

26. 4. MOSFET Switching Device M1
K K1
K_Linear
COUPLING = {K}
L1 = Lp
L2 = Ls
L3 = LsubD21
Vin_dc
Rs_Lp SF6L20U L21
Vin_dc OUT
0.15 8RHB
C2 2 1 C21 C22
R2 0.022u 890uF 890uF
33k
D1 + ESR21 ESR22 2.2k + 12
D4 C3 Lp Ls 33m 33m R23 RL
D2SBA60 C1 R1 150p {Lp} {Nsp*Nsp*Lp} 1 1 C23
SMH200VN270-22A 22k RJJ-35V221MG5-T20
1 2
1
2
3
4
IC = 141.4 D ESL21 ESL22 IC = 23.9
+ M1
MUR160 6.3nH 6.3nH
2SK3869
VDS R3
G ERA91-02
D2 2 2
Vac
FREQ = 50Hz - ID S
4.7k
2
PARAMETERS:
Np = 125 PC1_A R21
18k
VAMPL = {110*1.4142} Ns = 24
R7 R26
PHASE = 30 MTZJ24B 2.2 Nsub = 14 2.2k
R4 Lp = 650uH PC1_K
220 R22
R8 Nsp = {Ns/Np} 1.9k
0.22 DZ1 1 R24
Nsubp = {Nsub/Np}
680
D3 C4 Lsub K = 0.996055
C8 ERA91-02 47u {Nsubp*Nsubp*Lp}
0 0.22u R9 IC = 16.524 K R25 C24
IC = 2.42 100 330k 0.22u
C7 IC2 REF
1500p NJM431
IC = 2.9
A
R27
2.2k
R5 IC1
8 7 6 5
220 FA5311BP
0
1 2 3 4
C5 PC1_A
220 0.047u
IC = 3.37
R6
R10 R11 PC1_K
C6 2.2k
PC1
5.6k 6800p TLP281
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 26

27. 4.1 M1 Voltage and Current Stresses
Vin_dc(t) Analysis
Time Domain (Transient)
VPEAK = 333V Run to time: 500ms
Start saving data after: 0
Maximum step size: 10us
VDS(M1)(t)
.Options
RELTOL: 0.01
IPEAK = 2.6A
VNTOL: 1.0m
ABSTOL: 100.0n
ID(M1)(t) CHGTOL: 0.1p
GMIN: 1.0E-12
ITL1: 500
ITL2: 200
ITL4: 20
VOUT_24Vdc(t)
• Simulation result shows the VDS(M1) peak voltage and the ID(M1) peak current.
• The voltage and current should not exceed the maximum rating of the device M1 (2SK3869:
VDSS=450V , ID,max=10A).
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28. 4.2 Losses in M1
PLOSS_(M1)(t)
Switching
loss (turn-off) Analysis
Time Domain (Transient)
Switching Run to time: 60ms
loss (turn-on) Conduction loss Start saving data after: 40ms
(VDS x ID) Maximum step size: 100ns
Loss(AVG) = 4.64[W]
.Options
RELTOL: 0.01
VNTOL: 1.0m
ABSTOL: 100.0n
VDS(t)
CHGTOL: 0.1p
GMIN: 1.0E-12
ID(t)
ITL1: 500
ITL2: 200
ITL4: 20
• Simulation results shows waveforms of ID and VDS of MOSFET M1. Switching power loss and
average power loss are also shown.
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29. 4.3 MOSFET Model
• This figure shows the verification of the MOSFET model with measured fall time
characteristics ,that is the key to accurate PLOSS_(M1) simulation.
VGS(t) VDS(t)
90%VDS
tf
10%
Measured Simulated %Error
Fall time (tf) 40(ns) 38.976(ns) -2.56
All Rights Reserved Copyright (C) Bee Technologies Corporation 2010 29