This document provides an outline for a talk on electronic and thermal properties of semiconductor nanostructures from atomistic modeling and simulation. It motivates the importance of integrated atomistic simulation to study next-generation devices facing CMOS scaling challenges. It describes using an atomistic tight-binding approach and charge-potential self-consistent solution to model silicon nanowire field effect transistors, validated against experimental devices. The talk aims to discuss applications to silicon and gallium arsenide nanostructures and disseminating findings through nanohub.org.