Phasor data concentrator or i pdc
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This document describes the design and implementation of a Phasor Data Concentrator (PDC) compliant with the IEEE C37.118 synchrophasor standard for use in a Wide Area Measurement System. It presents the features of the implemented PDC (iPDC) including support for TCP/UDP communication, authentication and integrity checking of received data frames, local data storage, and a GUI. It also discusses the iPDC design including handling of different frame types, time alignment of data, and database storage. Experimental results demonstrate the iPDC's performance in various test cases.
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Upgrade and transform their legacy payment networks from traditional RS232 EDC terminals to RS485 or TCP/IP – without having to re-deploy or change their existing infrastructure or network
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1. The document describes two area and power efficient on-chip communication architectures proposed for image encryption and decryption using a single soft processor (MicroBlaze) on an FPGA.
2. The architectures are implemented using Xilinx Platform Studio on a Spartan6 FPGA. One is based on a Processor Local Bus and the other on an AMBA AXI interconnect.
3. The designs consume low power (0.67W) and occupy only 19% of FPGA resources. Experimental results show encryption and decryption of images takes 45 seconds.shashank_hpca1995_00386533
This document summarizes a paper that proposes and evaluates the performance of a multithreaded architecture capable of exploiting both coarse-grained parallelism and fine-grained instruction-level parallelism. The architecture distributes processing across multiple processing elements connected by an interconnection network. Each processing element supports multiple concurrently executing threads by grouping instructions from different threads. The architecture introduces a distributed data structure cache to reduce network latency when accessing remote data. Simulation results indicate the architecture achieves high processor throughput and the data structure cache significantly reduces network latency.
Design of Tele command SOC-IP by AES Cryptographic Method Using VHDL
The goal of this project is to implement the (AES) encryption system using Verilog. To do this, several separate sections of the algorithm will be coded to work together towards the end goal of performing the correct encryption routines. A telecommand is a command sent to control a remote system or systems i.e not directly connected (e.g. via wires) to the place from which the telecommand is sent. The telecommand word is derived from tele = remote (Greek), and command = to entrust/order (Latin). Systems that need remote measurement and reporting of information of interest to the system designer or operator, require the counterpart of telecommand, telemetry. For a telecommand (TC) to be effective, it must be compiled into a pre-arranged format (which may follow a standard structure), modulated onto a carrier wave which is then transmitted with adequate power to the remote system. The remote system will then demodulates the digital signal from the carrier, decode the telecommand, and execute it.
Csc presentation
This document provides an overview of the CERN School of Computing (CSC) held in August 2010. It discusses the organization of the CSC which covers introductory physics computing, common tools and techniques like ROOT, and data analysis. It also covers various base computing technologies like computer architecture, creating secure software, virtualization, and networking quality of service. Finally, it discusses data technologies and storage systems. The overall goal of the CSC is to provide students and researchers an overview of computing technologies relevant to particle physics experiments and concepts in particle physics.
fermilab-conf-12-398-cd
This document describes research into using a Kerberized Lustre filesystem over a wide area network (WAN) for high energy physics data analysis. Key points:
- The ExTENCI project implemented Kerberos authentication in Lustre to securely share data from CMS and LQCD experiments over the WAN. This allows remote access to analysis data while protecting the Lustre filesystem.
- Distributed object storage target (OST) pools were created at multiple universities and labs for faster local I/O. Virtual Lustre clients using various hypervisors can securely mount the filesystem.
- Benchmarking shows the Kerberized Lustre has little overhead for checksum security but a significant performance penalty for stronger
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This paper proposes improvements to the Chord peer-to-peer network protocol to increase reliability of data transfer. The Chord protocol uses a ring topology to organize nodes and determine routing, but direct routes sometimes fail. The paper suggests having nodes store failed packets locally and route them through multiple neighboring nodes to reach the destination. It also considers available bandwidth when selecting next-hop nodes. Simulations show the proposed methods increase packet delivery ratio compared to the base Chord protocol, especially as node movement increases, improving the reliability of data transfer in the peer-to-peer network.
Performance evaluation of ecc in single and multi( eliptic curve)
The document discusses performance evaluation of ECC (Elliptic Curve Cryptography) implementation on FPGA-based embedded systems using single and dual processor architectures. It explores implementing ECC using a single MicroBlaze soft processor core and a dual MicroBlaze core design with shared memory for inter-processor communication. Experimental results show the dual core design improves throughput by 3.3x over the single core design, encrypting data 3.3 times faster, but utilizes more resources and power due to the additional processor core.
A Comparative Analysis of Additional Overhead Imposed by Internet Protocol Se...
IPSec, an Internet layer three (3)-security protocol suite is often characterising with introducing an additional space and processing overhead when implemented on a network for secured communication using either internet protocol version 4 or 6; IPv4 or IPv6. The use of Internet protocol security (IPSec) on IPv4 is an alternative that offers solutions and addresses the security vulnerabilities in network layer of the open system interconnect (OSI) and transmission control protocol/internet protocol (TCP/IP) protocol stack. In IPv6, IPSec is one among many other features added to the earlier Internet protocol to enhance efficiency and security. This paper, set as its objective to reports on the impact of processing and space overhead introduced by IPSec on both IPv4 and IPv6 in relation to packet end-to-end delay based on different IPSec transformations with different authentication and encryption algorithms deployed in different scenarios simulated using NS2. The experiment result reveals that the cost of IPSec added overhead is relatively small when smaller packet sizes are involved for both protocols in comparison with large packet sizes that were IPSec protected with the same configuration as the smaller packet, unless in the cases whereby the packet was very large which has to be fragmented. This paper can therefore, serve as a guide for network administrators to trade up between processing cost and larger address space specifically for transmission involving larger IP packets
iPDC Report Kedar
The document is a project report submitted by Kedar Khandeparkar for the partial fulfillment of the requirements for the degree of Master of Technology. It discusses the design and implementation of communication, storage, and archival of an IEEE C37.118 standard based Wide Area Measurement System (WAMS). WAMS uses Phasor Measurement Units (PMUs) to collect synchronized phasor measurements across the power grid to provide improved monitoring capabilities compared to traditional SCADA systems. The report covers the components of WAMS, communication protocols, existing WAMS implementations, and use of databases for storage and archival of PMU/PDC data.
Design and Structuring of a Multiprocessor System based on Transputers
This document describes the design of a fault-tolerant multiprocessor system based on transputers. The system uses a modular design with each module containing 4 transputer nodes with bidirectional communication links. This allows the system to continue operating even if some processors or links fail. The design provides transparency against permanent module failures through multiple modular redundancy. Fault tolerance is achieved through mechanisms like acceptance testing, fault masking, and network reconfiguration. The reliability of communication between nodes is increased by using redundant acknowledgement packets. The overall system reliability takes into account factors like fault detection probability, repair probability and fault rate.
International Refereed Journal of Engineering and Science (IRJES)
International Refereed Journal of Engineering and Science (IRJES) is a leading international journal for publication of new ideas, the state of the art research results and fundamental advances in all aspects of Engineering and Science. IRJES is a open access, peer reviewed international journal with a primary objective to provide the academic community and industry for the submission of half of original research and applications
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Attention boosted deep networks for video classification
Attention boosted deep networks for video classification
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STUDY OF VARIOUS FACTORS AFFECTING PERFORMANCE OF MULTI-CORE PROCESSORS
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COMPARATIVE ANALYSIS OF DIFFERENT ENCRYPTION TECHNIQUES IN MOBILE AD HOC NETW...
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An area and power efficient on chip communication architectures for image enc...
An area and power efficient on chip communication architectures for image enc...
Design of Tele command SOC-IP by AES Cryptographic Method Using VHDL
Design of Tele command SOC-IP by AES Cryptographic Method Using VHDL
Performance evaluation of ecc in single and multi( eliptic curve)
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A Comparative Analysis of Additional Overhead Imposed by Internet Protocol Se...
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Design and Structuring of a Multiprocessor System based on Transputers
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International Refereed Journal of Engineering and Science (IRJES)
International Refereed Journal of Engineering and Science (IRJES)
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GHL Systems’ family of award-winning netAccess enterprise payment network devices are essentially simple, plug-and-play routing devices that provide protocol conversion and allow multiple payment devices or EDC terminals to be interconnected, and then simultaneously routing transactions quickly to multiple destination hosts – without ever having to replace or redeploy EDC terminals.
The L & X-Series payment routers are merchant-level, LAN-optimized network transaction concentrators and routers that enable EDC terminals to be networked and to perform extremely cost-effective and efficient transaction routing from these LAN terminals to the acquiring parties.
Upgrade and transform their legacy payment networks from traditional RS232 EDC terminals to RS485 or TCP/IP – without having to re-deploy or change their existing infrastructure or network
Exploit more efficient or faster wireless communications (Wi-Fi, GPRS, EDGE or HSDPA) channels
Use other communications channels as secondary pr backup links (ADSL, PSTN-ODD)
Transform variable communication costs to fixed costs
Route transactions to multiple hosts accurately and securely
Net Access W & N Presentation, Switching NAC, Network transaction concentrato...
NetAccess enterprise payment network equipment ensures dependable, steadfast, speedy yet affordable end-to-end connectivity for today’s financial institutions and merchants of all sizes.
Netator,switching nac,wan and node level uses load balancing,Access W-1000 is a high scalable transaction network platform allowing for multiple communication channels, and can further be deployed in multiple configuration combinations, catering to large-scale requirements. Coupled with its encryption capabilities and its intelligent feature, NetAccess W-1000 ensures your payment network will always stay secure - and connected.
1. Supports PSTN and wireless/GSM-based EDC terminals
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6. Native support for Ethernet TCP/IP
7. Customizable for special or customized protocols
NetAccess N-1000 Node Transaction Concentrator
Large- Scale Transaction Routing for Small Budgets. Connectivity Assured.
Designed for a branch or node environment, the netAccess N-1000 provides cost-effective and the fastest connectivity possible to any central payment transaction network.
Versatility is among the key features of the N-1000 in its support of all analog terminal modem connections, as well as new digital line connections and other ISDN standards. Additionally, netAccess N-1000 supports IPSEC over TCP/IP connections to the main node, which provides secure encrypted channels over a shared and un-trusted TCP/IP network. Additional security innovations includes its Active Clip Filtering (ACF), which allows only predefined and registered merchant phone numbers to access the transaction network.
NetAccess N-1000 WAN Transaction Concentrator
Large- Scale Transaction Routing for Small Budgets. Performance Multiplied.
Ghl Systems’ NetAccess W-1000 is a WAN transaction router that provides the fastest possible transaction access and routing for terminals to connect to payment hosts.
NetAccess W-1000 is a high scalable transaction network platform allowing for multiple communication channels, and can further be deployed in multiple configuration combination, catering to large-scale requirements. Coupled with its encryption capabilities and its intelligent feature, NetAccess W-1000 ensures your payment network will always stay secure - and connected.
Specification and Use of a Flux Concentrator
http://fluxtrol.com
Overview:
Basics of Magnetic Flux Control
Effect of Flux Controllers on Different Coil Styles
Materials for Magnetic Flux Control
Influence of Magnetic Permeability
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Crankshaft Hardening Inductors
Recognizing and Eliminating Flux Concentrator Failures
http://fluxtrol.com
Overview:
• What are the failure modes of a flux concentrator?
• How do we improve the design to prevent the failure in the future?
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concentrators.
Phasor data concentrator
This document discusses Wide Area Measurement Systems (WAMS) which are used to monitor power grids across large areas in real-time. It describes the key components of WAMS including Phasor Measurement Units (PMUs) which measure voltage and current phasors, and Phasor Data Concentrators (PDCs) which collect and process data from multiple PMUs. Standards for PMU data communication and different implementations of WAMS are also outlined.
solar concentrator
Solar concentrators use lenses to focus sunlight onto a smaller surface to increase intensity. The first concentrator plant opened in Italy in 1968. Future studies predict concentrated solar power could provide 25% of global energy needs by 2050 with $174 billion annual investment. Concentrators advantageously reduce heat loss area and thermal mass while increasing intensity on a smaller, cheaper receiver area, though precision optics increase costs and maintenance needs.
iPDC-v1.3.0 - A Complete Technical Report including iPDC, PMU Simulator, and ...
iPDC is a free Phasor Data Concentrator based on IEEEC37.118 synchrophasor standard. It also has Database Server for iPDC and PMU Simulator modules.
The objective of iPDC project is to create a IEEE C37.118 Synchrophasor standardized Phasor Data Concentrator and PMU Simulator, on which research students and others can develop and test their algorithms and applications. The purpose of iPDC released as a Free Software to its availability for users without any restriction regarding its usage and modification. And to get the contribution from users and developers all around the world.
iPDC do the time alignment and combining of the received data into frames as per IEEEC37.118 and can send to other iPDCs, and applications. iPDC can also archive received data in the MySQL database on local/remote machine. PMU Simulator is also IEEEC37.118 std compliant. Software is built to be working on Linux platform.
ICPDAS - Modbus Concentrator 700 series
The document discusses Modbus data concentrators and the MDC-700 Series. It explains that most meters only support low-speed serial interfaces like RS-232 and RS-485, and collecting data discontinuously makes communication less efficient. A Modbus data concentrator solves these problems by concentrating data from multiple RS-485 devices and making their registers appear continuous over Ethernet using Modbus/TCP. The MDC-700 Series is highlighted as having great capability, easy configuration via web interface and CSV files, and good expansion flexibility with multiple port options. It provides advantages over gateways and similar products from competitors.
What is Portable Oxygen Concentrator and How It Is Beneficial For Health
In todays lifestyle oxygen concentrator is quite helpful for healthy living. In this slide know every things about Portable Oxygen Concentrator eg. how does it works, history of oxygen concentrator, developement and why we should use it.
Knelson Concentrator
This document discusses a knelson concentrator, which uses centrifugal force for separating, classifying, dewatering, and treating mixtures. It introduces a new prototype separator that improves on existing solutions. The separator consists of a rotor with disks and pumps to transport separated solids, water, and air. It can treat mixtures containing solids, liquids, and gases. The document defines parameters for calculating the separator's capacity and separation efficiency based on feed properties. It is expected to save on flotation reagents by reducing solids in process water.
Modification and Testing of Parabolic Concentrator Solar Water Distiller Pres...
The document presents a project to modify and test a parabolic concentrator solar water distiller. A team of 5 students led by Siddharth Bhatnagar worked to automatically operate the distiller, increase its usability and efficiency, and reduce its weight. Modifications included strengthening the main frame, replacing mirrors with reflective aluminum sheets, and adding a microprocessor-controlled system with a solar panel, battery, motor and tracking connection. Testing showed usability increased 47%, efficiency increased 32%, and overall efficiency increased 23% compared to the previous design.
PARABOLIC TROUGH SOLAR CONCENTRATOR
Design and Fabrication of Parabolic Trough Solar concentrator For utility hot water production, by locally available materials
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As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high
performance, low power and high degree of programmability is the limitation in many general processor based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance making it
more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100 Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated the required functions in FPGA
Introduction to Programmable Networks by Clarence Anslem, Intel
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This document describes the design of an Ethernet packet processor for system-on-chip applications. The processor performs core packet processing functions like segmentation, reassembly, classification, and queue management to improve switching and routing performance. It has been implemented on an FPGA for 10/100/1000 Ethernet links. The design includes five VHDL modules with the core functionality in an aggregate module. It can identify packet fields, extract addresses and lengths, and check the CRC for errors. This packet processor is intended to offload tasks from the processor and accelerate functions like SFD detection and CRC calculation to improve the performance of next-generation IP network products like high-speed switches and routers.
Resume
Deepak Anand Ravindran is seeking a full-time position in digital ASIC RTL design or verification. He has a Master's degree in Electrical Engineering from USC and a Bachelor's degree from NIT Trichy. He has work experience in memory circuit design at Dolphin Technology, chip validation and failure analysis at Broadcom, and digital and power embedded systems design at CDOT Alcatel-Lucent Research Center. His technical skills include Verilog, C, Perl, and digital design tools from Synopsys and Cadence. He has completed academic projects in memory controller design, ATPG, processor performance simulation, and network processor design.
implementation of area efficient high speed eddr architecture
Abstract-This project presents an EDDR design, based on the residue-and-quotient (RQ) code, to embed into motion estimation (ME) for video coding testing applications. An error in processing elements (PEs), i.e. key components of a ME, can be detected and recovered effectively by using the EDDR design. The proposed EDDR design for ME testing can detect errors and recover data with an acceptable area overhead and timing penalty. The functional verification and synthesis can be done by Xilinx ISE. That is when compare to the existing design the implemented design area and timing will be reduced.
Index Terms—Area overhead, data recovery, error detection, reliability, residue-and-quotient (RQ) code, Xilinx ISE
An ethernet based_approach_for_tm_data_analysis_v2
Testing and performance evaluation of flight vehicles largely depends on the data gathered through telemetry. Tele-metered data describes the internal story of device under test. As the tele-metered data is transmitted to ground receiving stations through radio frequency and Inter Range Instrumentation Group (IRIG) standard data format are well known, anybody who is tuned to transmitted frequency, can receive data and minimal information about the format can reveal the total information of device under test. To deal with this situation, current trend is to encrypt the mission critical information on board before transmitting. In this paper, the authors have discussed the advantage of Local Area Network (LAN) based Telemetry base band system which provides scalability, modularity, and flexibility to the user for the analysis of encrypted data.
Appl 1340
The document summarizes a paper presented at the 2009 IEEE International Advance Computing Conference on implementing a codec driver for network embedded devices. It discusses:
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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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Deep Convolutional Network evaluation on the Intel Xeon Phi
With a sharp decline in camera cost and size along with superior computing power available at increasingly low prices, computer vision applications are becoming ever present in our daily lives. Research shows that Convolutional Neural Networks (ConvNet) can outperform all other methods for
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algorithms to achieve real-time performance on general purpose embedded platforms.
Parallelization and vectorization are very e ective ways to ease this problem and make it possible to implement such ConvNets on energy efficient embedded platforms. This thesis presents the evaluation of a novel ConvNet for road speed sign detection, on a breakthrough 57-core Intel Xeon Phi
processor with 512-bit vector support. This mapping demonstrates that the parallelism inherent in the ConvNet algorithm can be e ffectively exploited by the 512-bit vector ISA and by utilizing the many core paradigm.
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C style functions that map directly onto many Intel assembly instructions).
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This document is a master's thesis that evaluates a convolutional neural network for road speed sign detection on an Intel Xeon Phi processor. The thesis first introduces trends in computer vision like the dominance of neural networks. It then describes the research problem of high computational requirements of neural networks. The major contributions are mapping the neural network to effectively utilize the vector capabilities of the Xeon Phi through parallelization and optimization techniques. Evaluation shows speedups of over 12x can be achieved compared to single core performance.
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Introduction – Multiple tasks and multiple processes – Multirate systems- Preemptive realtime operating systems- Priority based scheduling- Interprocess communication mechanisms – Evaluating operating system performance- power optimization strategies for processes –Example Real time operating systems-POSIX-Windows CE. – Distributed embedded systems – MPSoCs and shared memory multiprocessors. – Design Example – Audio player, Engine control unit – Video accelerator.
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This document provides an overview of various on-chip bus protocols used in system-on-chips (SoCs) for communication between devices, including Inter-Integrated Circuit (I2C), Improved Inter-Integrated Circuit (I3C), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver/Transmitter (UART), and Peripheral Component Interconnect Express (PCIe). It discusses the implementation and applications of these bus protocols, as well as enhancements like I3C that improve upon I2C. The document also reviews related work analyzing the implementation and comparison of bus protocols like I2C and SPI.
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Seven years ago at LCA, Van Jacobsen introduced the concept of net channels but since then the concept of user mode networking has not hit the mainstream. There are several different user mode networking environments: Intel DPDK, BSD netmap, and Solarflare OpenOnload. Each of these provides higher performance than standard Linux kernel networking; but also creates new problems. This talk will explore the issues created by user space networking including performance, internal architecture, security and licensing.
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iPDC is a free Phasor Data Concentrator that collects data from PMUs, and PDC/iPDC that are IEEEC37.118 Synchrophasors std compliant. iPDC do the time alignment and combining of the received data into frames as per IEEEC37.118 and can send to other iPDCs, and applications. iPDC can also archive received data in the MySQL database on local/remote machine. PMU Simulator is also IEEEC37.118 std compliant. Software is built to be working on Linux platform.
iPDC is a free Phasor Data Concentrator based on IEEEC37.118 synchrophasor standard. It also has Database Server for iPDC and PMU Simulator modules.
The objective of iPDC project is to create a IEEE C37.118 Synchrophasor standardized Phasor Data Concentrator and PMU Simulator, on which research students and others can develop and test their algorithms and applications. The purpose of iPDC released as a Free Software to its availability for users without any restriction regarding its usage and modification. And to get the contribution from users and developers all around the world.
iPDC Report Nitesh
The use of synchrophasors for monitoring and improving the stability of power transmission networks is gaining in significance all over the world. The aim is to monitor the system state, to intensify awareness for system stability and to make optimal use of existing lines. This way, system stability can be improved overall and even the transmission performance can be increased. The data from so many PMU’s and PDC’s needs to be collected and directed to proper channels for its efficient use. Thus we need to develop an efficient, flexible and hybrid data concentrator that can serve this purpose. Besides accepting the data from PMU’s, PDC should be able to accept the data also from other PDC. We have designed such a PDC (iPDC) that accepts data from PMU & PDC that are IEEEC37.118 standard compliant.
WAMS architecture with iPDC and PMU at different levels. This architecture enables iPDC to receive data either from a PMU or other iPDC. Both PMU and iPDC from whom the data is being received should be IEEE C37.118 synchrophasor standard compliant. It is hybrid architecture.
iPDC Design
The client server architecture is common in networks when two peers are communicating with each other. Of the two peers (PMU and iPDC) that are communicating with each other in WAMS one acts as a client and the other as a server. Since PMU saves the requests coming
from iPDC by sending data or configuration frames it acts as a server. It listens for command frames from iPDC. PMU-iPDC communication can be either over TCP or UDP communication protocols. On receiving command frames, PMU replies to the iPDC with data or configuration frames according to the type of request.
iPDC functionality is bifurcated as server and client. iPDC as a Client - When iPDC receives data or configuration frames its acts as a client. When acting as a client, it creates a new thread for each PMU or a PDC from whom it is going to receive data/configuration frames. This thread would establish connection between the two communication entities. It handles both TCP and UDP connections. The first frame that the server (PMU/PDC) would receive is the command for sending the configuration frame. When the server replies with the configuration frame, iPDC (client) would generate another request to start sending the data frames. On receiving
such a command frame, the server starts sending the data frames. If there is some change in the status bits of data frame which the client (iPDC) notices, it would take an action. For example if it notices a bit 10 has been set, it would internally send a command to server to send the latest configuration frame.
iPDC as a Server- When iPDC receives command frames from another PDC it would acts as a server. There would be two reserved ports one for UDP and other for TCP on which the PDC would receive command frame requests. Thus PDC now plays the role of PMU waiting
for command frames.
Storage, retreival and process of continuous streaming data in a widearea fre...
Storage, retreival and process of continuous streaming data in a Wide Area Frequency Measurement System and further analysis to generate the flags and alerts.
Power System Network is continuously subjected to disturbances in the form of sudden load and generation changes. These disturbances give rise to oscillations in the rotor angle which are also seen in the frequency. To study these oscillations wide area frequency measurement setup is implemented in this project. The setup are strategically placed in five different places in India and are time synchronized via Network Time Protocol (NTP). The frequency is measured every 20 ms and is time stamped and send through
internet to a server in IITB.
The server program which is continuously receiving the packets, checking the correctness of packet information, doing the insertion in database according their time and displaying it on the web.
In ‘Wide area frequency measurement system’ frequencies measured at different places in India are sent to a IITB Server. Frequencies are measured by sensors at every 20 ms. Local frequency measured is stamped with the time and place and sent to IITB Server.
The IITB server is continuously listening for the packets on UDP port 6000. When a packet is received, it extracts the data and writes it in a file. A separate file is created for each sensor and when any file reaches its maximum a new file is created for each sensor with incremented serial number. Plotting of this data is done offline.
iPDC User Manual
The use of synchrophasors for monitoring and improving the stability of power transmission networks is gaining in significance all over the world. The aim is to monitor the system state, to intensify awareness for system stability and to make optimal use of existing lines. This way, system stability can be improved overall and even the transmission performance can be increased. The data from so many PMU’s and PDC’s needs to be collected and directed to proper channels for its efficient use. Thus we need to develop an efficient, flexible and hybrid data concentrator that can serve this purpose. Besides accepting the data from PMU’s, PDC should be able to accept the data also from other PDC. We have designed such a PDC (iPDC) that accepts data from PMU & PDC that are IEEEC37.118 standard compliant.
WAMS architecture with iPDC and PMU at different levels. This architecture enables iPDC to receive data either from a PMU or other iPDC. Both PMU and iPDC from whom the data is being received should be IEEE C37.118 synchrophasor standard compliant. It is hybrid architecture.
iPDC Design
The client server architecture is common in networks when two peers are communicating with each other. Of the two peers (PMU and iPDC) that are communicating with each other in WAMS one acts as a client and the other as a server. Since PMU saves the requests coming
from iPDC by sending data or configuration frames it acts as a server. It listens for command frames from iPDC. PMU-iPDC communication can be either over TCP or UDP communication protocols. On receiving command frames, PMU replies to the iPDC with data or configuration frames according to the type of request.
iPDC functionality is bifurcated as server and client. iPDC as a Client - When iPDC receives data or configuration frames its acts as a client. When acting as a client, it creates a new thread for each PMU or a PDC from whom it is going to receive data/configuration frames. This thread would establish connection between the two communication entities. It handles both TCP and UDP connections. The first frame that the server (PMU/PDC) would receive is the command for sending the configuration frame. When the server replies with the configuration frame, iPDC (client) would generate another request to start sending the data frames. On receiving
such a command frame, the server starts sending the data frames. If there is some change in the status bits of data frame which the client (iPDC) notices, it would take an action. For example if it notices a bit 10 has been set, it would internally send a command to server to send the latest configuration frame.
iPDC as a Server- When iPDC receives command frames from another PDC it would acts as a server. There would be two reserved ports one for UDP and other for TCP on which the PDC would receive command frame requests. Thus PDC now plays the role of PMU waiting
for command frames.
iPDC Programmer Manual
This document provides the source code documentation for an iPDC Phasor Data Concentrator. It describes the general working of the iPDC, including adding and removing data sources and destinations, turning data transmission on and off, and requesting configuration frames. It then documents the source code files and functions for the iPDC and associated DBServer and PMU simulator.
Design & implementation of phasor data concentrator compliant to ieee c37.118...
The use of synchrophasors for monitoring and improving the stability of power transmission networks is gaining in significance all over the world. The aim is to monitor the system state, to intensify awareness for system stability and to make optimal use of existing lines. This way, system stability can be improved overall and even the transmission performance can be increased. The data from so many PMU’s and PDC’s needs to be collected and directed to proper channels for its efficient use. Thus we need to develop an efficient, flexible and hybrid data concentrator that can serve this purpose. Besides accepting the data from PMU’s, PDC should be able to accept the data also from other PDC. We have designed such a PDC (iPDC) that accepts data from PMU & PDC that are IEEEC37.118 standard compliant.
WAMS architecture with iPDC and PMU at different levels. This architecture enables iPDC to receive data either from a PMU or other iPDC. Both PMU and iPDC from whom the data is being received should be IEEE C37.118 synchrophasor standard compliant. It is hybrid architecture.
iPDC Design
The client server architecture is common in networks when two peers are communicating with each other. Of the two peers (PMU and iPDC) that are communicating with each other in WAMS one acts as a client and the other as a server. Since PMU saves the requests coming
from iPDC by sending data or configuration frames it acts as a server. It listens for command frames from iPDC. PMU-iPDC communication can be either over TCP or UDP communication protocols. On receiving command frames, PMU replies to the iPDC with data or configuration frames according to the type of request.
iPDC functionality is bifurcated as server and client. iPDC as a Client - When iPDC receives data or configuration frames its acts as a client. When acting as a client, it creates a new thread for each PMU or a PDC from whom it is going to receive data/configuration frames. This thread would establish connection between the two communication entities. It handles both TCP and UDP connections. The first frame that the server (PMU/PDC) would receive is the command for sending the configuration frame. When the server replies with the configuration frame, iPDC (client) would generate another request to start sending the data frames. On receiving
such a command frame, the server starts sending the data frames. If there is some change in the status bits of data frame which the client (iPDC) notices, it would take an action. For example if it notices a bit 10 has been set, it would internally send a command to server to send the latest configuration frame.
iPDC as a Server- When iPDC receives command frames from another PDC it would acts as a server. There would be two reserved ports one for UDP and other for TCP on which the PDC would receive command frame requests. Thus PDC now plays the role of PMU waiting
for command frames.
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Phasor data concentrator or i pdc
- 1. Design & Implementation of Phasor Data Concentrator compliant to IEEE C37.118 Synchrophasor Standard in Wide Area Measurement System by Kedar Khandeparkar Nitesh Pandit Under the guidance of Prof. V.Z. Attar Prof. A. M. Kulkarni Prof. S.A. Soman Department of Computer Engineering and IT College of Engineering, Pune
- 2. Index Introduction IPDC Features iPDC Design Communication and Processing of frames Data Storage & iPDC Database Experiment & Results
- 3. Wide Area Measurement System(WAMS) WAMS has two components Phasor Measurement Unit(PMU) Phasor Data Concentrator(PDC)
- 4. WAMS
- 5. PMU Standards IEEE1344 IEEEC37.118(2005)
- 6. IEEE C37.118 Message types Command Data Configuration Header
- 8. Data Frame
- 12. Features of iPDC It is a generalized PDC. Is a multithreaded application.
- 14. iPDC Design
- 17. Recreate configuration objects from file cfg.bin
- 23. Configuration Frame Generation for iPDC Number of PMU is sum of all PMU. Data rate is the highest among all PMU/iPDC data rate. Combined configuration frame compliant with IEEEC37.118 std.
- 24. Data Storage
- 25. iPDC Database
- 26. Requirements Software Requirements : Programming Languages C, GTK+ Database MySQL Packages libmysqldev System Requirements Memory 512 MB OS Linux
- 28. Case1 :
- 29. Case 1 contd...
- 30. Case2 :
- 31. Case 2 contd...
- 32. Case3 :
- 33. Case 3 contd...
- 34. Case4 :
- 35. Case 4 contd...
- 36. Results
- 37. iPDC Interface
- 38. Future Enhancements Need to study and implement iPDC on RTOS and check its performance & scalability in Real Time. Different aspects of security in WAMS need to studied and implemented. On field testing of iPDC application need to be done to know its performance & limitations. iPDC can be updated to support more PMU standards.
- 39. References Ken Martin, "IEEE Standard for Synchrophasors for Power Systems", IEEE Std C37.118 2005. Moustafa Chenine,"Analysisof Data Quality Issues in Wide Area Monitoring and Control Systems", IREP Symposium on Bulk Power System Dynamics and Control, Aug 16, 2010. Yingchen Zhang, "WideArea Frequency Monitoring Network (FNET) Architecture and Applications", IEEE Transactions on Smart Grid, Vol. 1, No.2, Sep 2010. Andrew Armenia, Student Member, IEEE, and Joe H. Chow, Fellow, IEEE, "A Flexible Phasor Data Concentrator Design Leveraging Existing Software Technologies”, IEEE Transactions ON SMART GRID, VOL. 1, NO. 1, JUNE 2010. Moustafa Chenine, Student Member, IEEE, " Investigation of Communication Delays and Data Incompleteness in MultiPMU Wide Area Monitoring and Control Systems".
- 40. Source Code & Documentation http://sourceforge.net/projects/iitbpdc/ http://freshmeat.net/projects/ipdc http://ipdc.codeplex.com/
- 41. Thank You