Design of Tele command SOC-IP by AES Cryptographic Method Using VHDL

IDL - International Digital Library Of
Technology & Research
Volume 1, Issue 3, Mar 2017 Available at: www.dbpublications.org
International e-Journal For Technology And Research-2017
IDL - International Digital Library 1 | P a g e Copyright@IDL-2017
Design of Tele command SOC-IP by AES
Cryptographic Method Using VHDL
Ms.RASHMI P1
, Ms.RASHMITHA C M2
, Mr.SHIVUKUMAR3
, Ms.SWATHI M D4
UG
Scholars. B S Sahana Raj5
, Assistant Professor,
Dept. of Electronics & Communication Engineering,
PESCE, Mandya. An Autonomous Institution affiliated to Visvesvaraya Technological
University, Belgaum)
Literature Review Article
ABSTRACT
The goal of this project is to implement the (AES)
encryption system using Verilog. To do this, several separate
sections of the algorithm will be coded to work together
towards the end goal of performing the correct encryption
routines. A telecommand is a command sent to control a
remote system or systems i.e not directly connected (e.g. via
wires) to the place from which the telecommand is sent. The
telecommand word is derived from tele = remote (Greek), and
command = to entrust/order (Latin). Systems that need remote
measurement and reporting of information of interest to the
system designer or operator, require the counterpart of
telecommand, telemetry. For a telecommand (TC) to be
effective, it must be compiled into a pre-arranged format
(which may follow a standard structure), modulated onto a
carrier wave which is then transmitted with adequate power to
the remote system. The remote system will then demodulates
the digital signal from the carrier, decode the telecommand,
and execute it.
I. REVIEW PAPERS
1. “System-on-Chip (SoC) for Telecommand
System Design International Journal of
Advanced Research in Computer and
Communication Engineering Vol. 2, Issue 3,
March 2014”
The emerging developments in semiconductor
technology have made possible to design entire
system onto a single chip, commonly known as
System-On-Chip (SoC). The incresase in Space
System„s capabilities kindled by the On-board data
processing capabilities can be overcome by
optimizing the SoCs to provide cost effective, high
performance, and reliable data. This is achieved by
embedding pre-designed functions into a single
SoC, which utilizes specialized reusable core (IP
cores) architecture into complex chip.This paper is
concerned with the design of telecommand system
for transfer of signals from ground station to space
station by the integration of SRAM(Static Random
Access Memory), ARM (Advanced RISC Machine)
Processor, EDAC unit (Error Detection And
Correction)and CCSDS (Consultative Committee

for Space Data System) decoder system.In this
paper we designed the Telecommand SoC.
2. “HIGH SPEED IP BASED
ARCHITECTURE FOR TELE COMMAND
SYSTEM Proceedings of Third IRF
International Conference, 07th March-2015,
Mysore, India, ISBN: 978-93-82702-74-0”
An IP (intellectual property) core is a block of logic
or data that is used for making a field programmable
gate array ( FPGA ) or application-specific integrated
circuit ( ASIC ) for a product. Design reuse IP cores
are part of the growing electronic design automation
(EDA ) industry which allows the repeated use of
previously designed components. Using many IP
cores a system itself can be designed, System on
Chip (SoC) offers this requirement. In the current
telecommand communication method, excess number
of physical devices is present, which cause a major
communication delay. Combining many of the
predesigned internal blocks in to a single chip can
solve this problem.
3. “Designing Space Applications Using
Synthesisable Cores- European Space Agency
European Space Research and Technology
Centre (ESTEC) Postbus 299, NL-2200 AG
Noordwijk, The Netherlands”
Very high integration levels of microelectronics will
be required to fulfil the ever-increasing demands for
high processing performance, low mass and power.
With an increasing number of available gates on
silicon, the functionality being implemented will
move away from the use of traditional components to
more advanced and complex systems within a single
device. To develop such complex circuits the design
methodology will have to change from being gate-
level oriented to the integration of complex building
blocks. The designers will have to rely on pre-
existing building blocks with already verified
functionality, with documentation and production test
vectors being available, and which have ultimately
been validated on silicon.
4. “DESIGN OF SPACE DATA LINK
SUBLAYEROF TELECOMMAND
DECODER USING CCSDS PROTOCOL-
ISSN (Print): 2278-5140, Volume-2, Issue – 2,
2013”
This paper deals with the design of Space Data Link
layer of a Telecommand Decoder using CCSDS
protocol. Telecommand Decoder is a part of
Telecommand subsystem which receives uplinked
data/ commands and distributes it to all subsystems.
All commands received will be validated and
thereafter depending on the address, commands will
be delivered to their respective destinations. Space
Data Link sublayer was designed to meet the
requirements of space missions for efficient transfer
of space application data or commands to control the
Spacecraft. Space Data Link modules are designed
using CCSDS protocol and VHDL code for the same.
Simulation is performed using modelsim.
II. OBJECTIVE
The main objective of the project is to design and develop
architecture for Design of Tele command soc IP by using
AES cryptographic method using VHDL. To overcome the
shortfall of the present design where the major drawback has
been the increased delay and decrease in frequency for
transmission of data packets. The new architecture is designed

to analyze the scope for a performance enhancement with
respect to the present system.
III.MOTIVATION
Consumer demands for high performance and rich
functionality have driven the semiconductor manufacturing
industry to the integration of multiple complex components
onto a single chip. As the complexity of the remotely located
physical devices increases, the requirement for a greater
telecommanding capability and efficiency arises, but present
IP Core Based Architecture of telecommand System-on-a-
Chip (SoC) has increased delay in transmission of data
packets. The increase in demand for better throughput and
increase features has lead to the motivation of this project.
IV.SOLUTION
In this proposed design, plan to achieve by
embedding pre-designed functions into a single SoC, which
utilizes specialized reusable core (IP cores) architecture into
complex chip. The conventional telecommand system is
designed with Telecommand Processor and they are integrated
onto a chip .In this project, which reduces the utilization of
slices and hence time delay is reduced.
Since IP cores are pre-designed and pre-verified, the
designer can concentrate on the complete system without
having to worry about the correctness or performance of the
individual components.
REFERENCES
[1] "TC SPACE DATA LINK PROTOCOL” Recommended
standard, Blue book issue 1, CCSDS 231.0-B1, SEP 2003.
[2] "TC SPACE DATA LINK PROTOCOL” Recommended
standard, Blue book issue 2, CCSDS 231.0-B2, Sep 2010.
[3] “Detailed Design Review Document of TTCB/B System of
INSAT-4B” ISRO, Aug 2005.
[4] “Baseline Design Review Document of TTCB/B System
of INSAT-4B” ISRO, Mar 2011.
[5] Lin, Shu, and Daniel J. Costello, Jr., “Error Control
Coding: Fundamentals and Applications”, Englewood Cliffs,
NJ, PrenticeHall, 1983.
[6] Dr. PS. Sathyanarayana “Concepts of Information Theory
and Coding”
[7] “Proximity-1 SPACE LINK PROTOCOLCODING AND
SYNCHRONIZATION SUBLAYER” Recommended
standard, Blue book, CCSDS 211.2-B1, April 2003.
[8] Telecommand Part 1.Channel Service. Recommendation
for Space Data System Standards, CCSDS 201.0-B-3.Blue
Book. Issue 3. Washington, D.C.: CCSDS, June2000.
[9] Packet Telemetry. Recommendation for Space Data
System Standards, CCSDS 102.0B-5.Blue Book. Issue 5.
Washington, D.C.: CCSDS, November 2000.
[10] Telecommand Part 2.1.Command Operation Procedures.
Recommendation for Space Data System Standards, CCSDS
202.1-B-2.Blue Book. Issue 2. Washington, D.C.: CCSDS,
June 2001.
[11] Rajesvari., Manoj G, Angelin Ponrani.M )“IP Core Based
Architecture of Telecommand System-on-Chip (SoC) for
Spacecraft applications “International Conference on Signal
Processing, Image Processing and Pattern Recognition”- 2013
[12] SoC: A Real Platform for IP Reuse, IP Infringement, and
IP Protection Debasri Saha and Susmita Sur-Kolay Advanced
Computing and Microelectronics Unit, Indian Statistical
Institute, Kolkata 700108, India, Received 12 October 2010;
Revised 4 January 2011; Accepted 24 January 2011
[13] Reduced Precision Redundancy for Satellite
Telecommand Receiver Module on FPGA Salman Sadruddin
and Arshad Aziz,National University of Science and
Technology (NUST), H-12, Islamabad, Pakistan, Hindawi
Publishing Corporation ,Chinese Journal of
Engineering,Volume 2013, Article ID 453872, 8 pages.
[14] The International Journal Of Engineering And Science
(IJES) || Volume || 3 || Issue || 6 || Pages || 17-24 || 2014 || ISSN

(e): 2319 – 1813 ISSN (p): 2319 – 1805 www.theijes.com The
IJES Page 17,FPGA Implementation of System-on-chip
(SOC) Architecture for Spacecraft Application ,Kiran Kumar
B.G ,Dr. Kaushik Bhattacharyya
[15] International journal of electronics and communication
engineering & technology(IJECET) ,Volume 5, Issue 8,
August (2014), pp. 139-149, designing of telecommand
system using system on chip(soc) for spacecraft control
applications by Anupama sindgi, u.b.Mahadevaswamy
[16] Wireless Telecommand and Telemetry Systems for
Satellite Communication Using ZigBee Network”
Ravichandran, P.N. Kulkarni S. Sharma, S. Vasudevamurthy,
H.S. Vanitha, M. Lakshminarsimhan, P. Digital Syst. Group,
ISRO Satellite Center, and Bangalore, India this paper appears
in: Advances in Recent Technologies in Communication and
Computing, 2009. ARTCom '09. International Conference.
[17] System-on-Chip: Reuse and Integration Pre-designed and
pre-verified hardware and software blocks can be combined
on chips for many different applicationsVthey promise large
productivity gains. By Resve Saleh, Fellow IEEE,
SteveWilton, Senior Member IEEE, Shahriar Mirabbasi,
Member IEEE

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