The document discusses the instruction format, length, and set extensions of Pentium microprocessors. It also describes the cache structure of original Pentium processors. The cache was divided into separate 8KB code and data caches to allow crossing page boundaries without overwriting. The cache used a set-associative organization with a 2-way 128-line cache and 32-byte cache lines. On a cache miss, the CPU would stall while the requested data was retrieved from main memory.

1. COMPUTER ORGANISATION
THE INSTRUCTIONS AND CACHE
OF PENTIUM MICROPROCESSOR
ANUSH HP

2. OVERVIEW
 PENTIUM INSTRUCTION FORMAT
 INSTRUCTION LENGTH
 INSTRUCTION SET EXTENSIONS
 P III INSTRUCTION EXECUTION UNITS
 PENTIUM 4 INSTRUCTION SET
 PENTIUM IV PROCESSOR ARCHITECTURE
 CACHE STRUCTURE
 BLOCK DIAGRAM of CACHE STRUCTURE
 CACHE ORGANIZATION
 CPU & CACHE HANDLING

3. PENTIUM INSTRUCTION FORMAT
 Supports 8, 16, 32-bit operands.
 It defined layout of bit in an
instruction which includes Opcodes.
 Officially 17 addressing modes,
arguably more.
 Keyed off the opcode and prefixes
 Identical “assembly language” from
old 8080 CPU.
 It has more than one instruction
format in an instruction set.

4. INSTRUCTION LENGTH
It is affected and also affects the system in
Memory Size
Memory Organization
Bus structure
Opcodes and Operands
CPU Complexity
CPU speed

5. INSTRUCTION SET EXTENSIONS
 Each new processor brought new instructions
• Specialized sets, too
 80x87 Math Co-Processor
• Introduced floating point instructions and stack
• Integrated into later processors
 MMX (1997)
• SIMD instructions, 8 integer registers @ 64 bits (reused FP)
 3DNow! (AMD in 1997)
• MMX extended to support floating point operations
 SSE (1999; SSE2 in 2000 for integers)
• 8 giant 128-bit registers for SIMD operation

6. P III INSTRUCTION EXECUTION UNITS

7. PENTIUM 4 INSTRUCTION SET
Embeds a RISC architecture and pipelining within a CISC instruction set
• Instructions fetched to CPU
• Translated into internal RISC-style “microinstructions”
• Microinstructions are stored in the level 0 instruction cache
• CPU execution logic executes microinstructions in a pipelined fashion.
Retains compatibility with old Pentium and x86 code while achieving
RISC-like performance.

8. PENTIUM IV PROCESSOR ARCHITECTURE

9. CACHE STRUCTURE
Cache structure gives info in-depth regarding the cache of the original Pentium
processor.
 It include cache organization, operation modes, and methods to ensuring cache
consistency.
Cache is located on-chip and is divided into separate pieces; one for data and
one for code, each at 8KB.
This division is done to maximize both flexibility and performance by allowing
both code and data caches to readily cross page boundaries without having to
overwrite one another.

10. BLOCK DIAGRAM OF CACHE STRUCTURE

11. CACHE ORGANIZATION
In a set-associative structure the cache is divided into equal sections called
cache ways.
 The cache page size is equal to the size of the cache way and each cache way
is treated like a small direct mapped cache.
 In a 2-way scheme, two lines of memory may be stored at any time.
The Pentium processor’s cache line size is 32 bytes and is filled by a burst of
four reads on the processor’s 64-bit data bus.
 Each cache way contains 128 cache lines and the cache page size is 4K, or
128 lines.

12. CPU AND CACHE HANDLING
 Activities that occurs when there is a cache miss
• A stall, like a pipeline stall, but simpler.
• We stall the whole CPU - inefficient but it’s the best approach.
 When user writes a data
• “Write through” runs the write while CPU proceeds
• Other CPU accesses get the cached, updated value
• “Write miss” - obvious approach isn’t efficient
• Use a “write buffer” to catch missed writes

13. QUESTIONS ???

14. THANK YOU