2. Construction
• A slab of p-type material is formed
from a silicon base called substrate.
• It is the foundation on which
device is constructed
• In some cases, substrate is
internally connected to source.
• In some cases, additional terminal
substrate is provided, resulting in 4
terminal device.
• The source and drain terminals are
connected through metallic
contacts to n-doped region linked
by n-channel.
3. Construction:
• The gate is also connected to
metal contact surface but
remains insulated from n-
channel by a very thin SiO2 layer
• So there is no direct electrical
connection between the gate
and channel of MOSFET.
• So, its input impedance is very
high
4. Basic Operation: When VGS=0 V and VDS>0 V
• When VDS is applied across the
drain to source terminals, the
result is an attraction for the
positive potential at the drain by
the free electrons of the n-channel
and a current ID is established.
• When VDS = VP, pinch off occurs and
ID maintains the saturation level
called IDSS .
• As VDS increased beyond VP, level of
ID remains essentially the same .
• Operation similar to JFET
5. Basic Operation: When VGS<0 V and VDS>0 V
• The negative potential at the
gate will tend to pressure
electrons toward the p-type
substrate and attract holes from
p-type substrate.
• Depending upon the magnitude
of negative VGS, a level of
recombination between
electrons and holes will occur
that will reduce the number of
free electrons in the n-channel
available for conduction.
• So the resulting level of drain
current is reduced with
increasing negative bias for VGS.
6. Reduction in free carrier in channel due to
negative potential at gate terminal
• When VGS = -VP will be
sufficiently negative to
establish a saturation level
that is essentially 0 mA and
for all practical purposes
devices has been turned
off.
7. Basic Operation: When VGS>0 V and VDS>0 V
• For positive value of VGS, the
positive gate will draw
additional electrons from p-
type substrate.
• As VGS continues to increase
in positive direction, drain
current will increase in rapid
rate.
• The application of +VGS has
enhanced the level of free
carriers in the channel
compared to that
encountered with VGS =0 V.
8. Characteristics Curve:
• For this reason , the region of +VGS is referred as enhancement region
and region of VGS (-VP to 0 ) is referred as depletion region in
characteristics curve.
• The characteristics equation:
ID = IDSS(1−
VGS
VP
)2
9. D-MOSFET Biasing: Self-bias Configuration
• Find ID, VGS and VDS
• ID = 6.23 mA ,1.76 mA
• Idsat = VDD/(RD+RS) = 2.33 mA
• since ID can not be greater than
Idsat.
• So, ID = 1.76 mA
• VGS = -4.23 V
• VDS= 4.86 V
•
•
10. Voltage divider bias:
• Find ID, VGS and VDS
• VG = 1.5 V
• ID = 3.1 mA, 11.5 mA
• Idsat = 7.0588 mA
• IDQ = 3.1 mA
• VGSQ = -0.825 V
• VDS= 10.1 V
11. Determine VDS for the network:
• VGS = 0 V
• ID = IDSS
• KVL at output side;
• VDD = IDRD + VDS
• VDS = 5 V
