MIS Diode (MOS capacitor) – Ideal
EC
EF
EV
Ei
Ideal MIS Diode n-type, Vappl=0
Assume Flat-band
at equilibrium
qφS
ECE 663
Ideal MIS Diode p-type, Vappl=0
ECE 663
Band bending due to work function difference
msFBV φ=
ECE 663
Accumulation
Pulling in majority carriers at surface
ECE 663
Depletion
ECE 663
Need CB to dip below EF.
Once below by ψB, minority carrier density trumps the intrinsic density.
Once below by 2ψB, it trumps the major carrier density (doping) !
Inversion
ψB
Some important equations in the
inversion regime (Depth direction)
VT = φms + 2ψB + ψox
Wdm = √[2εS(2ψB)/qNA]
Qinv = Cox(VG - VT)
ψox = Qs/Cox
Qs = qNAWdm
VT = φms + 2ψB + (√[4εSψBqNA] - Qf + Qm + Qot)/Cox
Substrate
Channel Drain
Insulator
Gate
Source
x
ECE 663
P-type semiconductor Vappl≠0
Convention for p-type: ψ positive if bands bend down
ECE 663
Substrate
Drain
Insulator
Gate
Source Channel
Substrate
Insulator
Gate
Channel
MOScap MOSFET
Operation of a transistor
VSG > 0
n type operation
Positive gate bias attracts electrons into channel
Channel now becomes more conductive
Substrate
Channel Drain
Insulator
Gate
Source
VSD
VSG
Substrate
Channel Drain
Insulator
Gate
Operation of a transistor
Transistor turns on at high gate voltage
Transistor current saturates at high drain bias
Source
VSD
VSG
Saturation Region
occurs at large VDS
p
n+n+
metal
source
S
gate
G
drain
D
body
B
oxide
+
-
+++
+++
+++
VDS large
As the drain voltage increases, the difference in voltage
between the drain and the gate becomes smaller. At
some point, the difference is too small to maintain the
channel near the drain  pinch-off
Simplified MOSFET I-V
Equations
Cut-off: VGS< VT
ID = IS = 0
Active: VGS>VT and VDS < VGS-VT
ID = kn
’
(W/L)[(VGS-VT)VDS - 1
/2VDS
2
]
Saturation: VGS>VT and VDS > VGS-VT
ID = 1
/2kn’(W/L)(VGS-VT)2

Mos

Editor's Notes