1) SPI (Serial Peripheral Interface) is a synchronous serial communication interface standard used for communicating with serial peripheral devices.
2) SPI uses four signals - Serial Clock (SCLK), Master Output Slave Input (MOSI), Master Input Slave Output (MISO), and Slave Select (SS). It can support multiple slaves through individual SS lines.
3) SPI is full duplex, allowing simultaneous transmission and reception of data. It provides higher throughput than I2C but requires more pins and the master must control all communication.
SOUG - Experiences with Oracle Solaris 11.4JomaSoft
Oracle Solaris 11.4 was launched in August 2018.
What are the new features in the area of Zones, ZFS and Security?
What was delivered in the last 30 monthly updates?
SOUG - Experiences with Oracle Solaris 11.4JomaSoft
Oracle Solaris 11.4 was launched in August 2018.
What are the new features in the area of Zones, ZFS and Security?
What was delivered in the last 30 monthly updates?
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
Rapid Prototyping with AWS IoT and Mongoose OS on ESP32 PlatformAmazon Web Services
Mongoose OS is a modern open-source real-time operating system for variety of MCU architectures. It has the same look and feel on a broad spectrum of supported microcontrollers. It is also designed from the ground up for connected devices. In this session, we will teach you how to connect to AWS IoT from a device in under 3 minutes and then walk through how to use crypto-element for securing TLS communication and deploy fully functional thermostat with CloudFormation template, utilizing AWS IoT, Amazon DynamoDB, Amazon Cognito, and Amazon S3.
From KubeCon to ContainerDays, eBPF is trendy in the Cloud Native world. What is eBPF, and why is it revolutionary, and what can it bring to you specifically?
Through concrete examples applied to observability, networking, and security, this talk will explain the principles of eBPF and its concrete advantages to connect and secure Cloud Native applications.
This talk will explain what is eBPF, why it is revolutionary is several fields, give examples of tools using eBPF and what they gain from it, and open up to the future of that technology.
100 MHz High Speed SPI Master: Design, Implementation and Study on Limitation...rahulmonikasharma
SPI or Serial Peripheral Interface is among the fastest synchronous serial communication protocols used in embedded systems. High throughput and simplicity of SPI communication has made SPI protocol; a de facto standard. Designs based on FPGAs (Field Programmable Gate Arrays) enhance reusability, flexibility and faster prototyping of digital systems, especially serial buses, which are inevitable in almost all designs. This paper discusses the design and implementation of a 100 MHz High Speed SPI Master Core on FPGA. State machine approach is employed for the RTL (Register Transfer Level) design of the core. The paper also discusses the challenges and limitations of implementing such a high speed SPI bus in digital systems. The SPI Master Core was successfully implemented on Altera Cyclone III FPGA for a speed of 100 MHz.
MySQL Group Replication - HandsOn TutorialKenny Gryp
During this tutorial, attendees have their hands on virtual machines and migrate standard Master - Slave architecture to the new MySQL native Group Replication.
After explaining briefly what is group replication and how this is important for MySQL HA architecture. We will cover how to verify the workload and the scheme to how GR can be used and configured.
Then we will go trough the migration steps with minimal impact on the live system.
Basic administration tasks are covered such as add/remove a node from the cluster. We also play with performance_schema to monitor our Group Replication cluster and understand how to control it.
Serial Peripheral Interface Design for Advanced Microcontroller Bus Architect...IJMTST Journal
Design of System-on-Chip(SoC) receives a great deal of attention in recent days. The number of peripherals used in one SoC becomes larger and larger. Processors and peripherals usually communicate with each other using some protocol. With the development of SoC technique, the communication between processor and peripherals become a problem as processors have limited ports hence we design Serial Peripheral Interface to maximize the usage of the existing ports. We are designing a SPI Flash Controller which is compatible with the Advanced Microcontroller Bus Architecture (AMBA) developed by ARM. We are developing a SPI Module which can operate based on the Advanced High Performance Bus (AHB) signals. Any SPI Flash Slave can be interfaced with the SPI Module directly from the ARM Processor. This paper is concerned with design and implementation of a SPI Flash Controller on FPGA which can communicate with SPI Slaves. Tool used for simulation is ModelSim 10.1b and finally implementation include FPGA kit Spartan3 xc3s400-pq208 comprising of 208 pins synthesis carried on Xilinx v9.1.Implantable and medical devices (IMDs) have been advanced with the advancements in engineering and medical science. IMDs are used for applying new therapies to patients, monitoring human body parameters and making diagnosis as per the monitoring result. Increased use of IMDs has enhanced the chances of attacks to them. Therefore, to make use of IMDs for various applications, they need to be secured. A system is developed to achieve the security. The system monitors various human body parameters wirelessly and detects anomaly if unauthorized node participates in communication. The system uses request response protocol in wireless communication. Experiments show that body parameters can be successfully monitored and signal characteristic can be used to detect anomaly.
String Comparison Surprises: Did Postgres lose my data?Jeremy Schneider
Comparisons are fundamental to computing - and comparing strings is not nearly as straightforward as you might think. Come learn about the history, nuance and surprises of “putting words in order” that you never knew existed in computer science, and how that nuance impacts both general programming and SQL programming. Next, walk through a few actual scenarios and demonstrations using PostgreSQL as a user and administrator, which you can re-run yourself later for further study, including one way you could easily corrupt your self-managed PostgreSQL database if you aren't prepared. Finally we’ll dive into an explanation of the surprising behaviors we saw in PostgreSQL, and learn more about user and administrative features PostgreSQL provides related to localized string comparison.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
Contact with Dawood Bhai Just call on +92322-6382012 and we'll help you. We'll solve all your problems within 12 to 24 hours and with 101% guarantee and with astrology systematic. If you want to take any personal or professional advice then also you can call us on +92322-6382012 , ONLINE LOVE PROBLEM & Other all types of Daily Life Problem's.Then CALL or WHATSAPP us on +92322-6382012 and Get all these problems solutions here by Amil Baba DAWOOD BANGALI
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Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
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SPI (Serial Peripheral Interface)
synchronous data transfer
Full-duplex
Single Master / multi slave
Serial interface
Multiple slave devices are supported through selection with individual slave
select (SS) lines
The SPI bus was originally started by Motorola Corp. (now Freescale), but in recent years has become a widely
used standard adapted by many semiconductor chip companies
It can be used to communicate with a serial peripheral device like
external EEPROM or with another microcontroller with an SPI
interface
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HOW SPI WORKS?
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In).
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out).
The master clock generator provides clock to the shift registers in both the master and
slave.
The clock input of the shift registers can be falling- or rising-edge triggered.
Shift registers are 8 bits long. So after 8 clock pulses, the contents of the two shift
registers are interchanged.
When the master wants to send a byte of data, it places the byte in its shift register and
generates 8 clock pulses.
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HOW SPI WORKS?
After 8 clock pulses the byte is transmitted to the other
shift register.
When the master wants to receive a byte of data, the slave
side should place the byte in its shift register, and after
8 clock pulses the data will be received by the master shift
register.
It must be noted that SPI is full duplex, meaning that it
sends and receives data at the same time.
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Simple SPI Write Transaction
Most SPI flash memories have a write status register command that writes one or two bytes of data.
To write to the status register, the SPI host first enables the slave select line for the current device. The master then outputs
the appropriate instruction followed by two data bytes that define the intended status register contents. Since the transaction
does not need to return any data, the slave device keeps the MISO line in a high impedance state and the master masks any
incoming data. Finally, slave select is de-asserted to complete the transaction.
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Simple SPI Read Transaction
A status register read transaction would be similar to the write transaction, but now takes advantage of
data returned from the slave. After sending the read status register instruction, the slave begins
transmitting data on the MISO line at a rate of one byte per eight clock cycles. The host receives the
bitstream and completes the transaction by de-asserting SS#
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus. In a 3-wire interface bus, we have
SCLK and CE, and only a single pin for data
transfer.
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together.
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol.
For that reason, a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device.
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols.
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QUAD SPI [QSPI]
Multi I/O variants such as dual I/O and quad
I/O add additional data lines to the standard
for increased throughput. This
performance increase enables random
access and direct program execution from
flash memory (execute-in-place)
A multi I/O SPI device is capable of
supporting increased bandwidth or
throughput from a single device. A dual
I/O (two-bit data bus) interface enables
transfer rates to double compared to the
standard serial Flash memory devices.
A quad I/O (four-bit data bus) interface
improves throughput four times.
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Example: Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a
Spansion S25FL016K serial NOR
flash device. To read from the
device, a fast read command
(EBh) is first sent by the master on
the first IO line while all others are
tristated. Next, the host sends the
address; since the interface now
has 4 bidirectional data lines, it
can utilize these to send a
complete 24-bit address along
with 8 mode bits in just 8 clock
cycles. The address is then
followed with 2 dummy bytes (4
clock cycles) to allow the device
additional time to set up the initial
address.
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with
SPI:
SPCR – SPI Control Register – This register is basically the
master register i.e. it contains the bits to initialize SPI and
control it.
SPSR – SPI Status Register – This is the status register. This
register is used to read the status of the bus lines.
SPDR – SPI Data Register – The SPI Data Register is the
read/write register where the actual data transfer takes place.
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SPCR – SPI Control Register
Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set.
Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS
is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR
will become set. The user will then have to set MSTR to re-enable SPI Master mode.
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SPSR – SPI Status Register
Bit 7 – SPIF: SPI Interrupt Flag
1. When a serial transfer is complete, the SPIF Flag is set. An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled.
2. If SS is an input and is driven low when the SPI is in Master mode, this
will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector.
Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set, then accessing the SPI Data Register (SPDR)
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Code Sequence
Before you start data transmission, you should set
SPI Mode (Clock Polarity and Clock Phase) by setting
the values of the CPOL and CPHA bits in SPCR.
You can operate in either master or slave modes.
Master operating mode
If you want to work in master mode, you should set
the MSTR bit to one. Also you should set SCK
frequency by setting the values of SPI2X, SPR1, and
SPR2.
Then you should enable SPI by setting the SPIE bit to
one before you start data transmission.
Writing a byte to the SPI Data Register (SPDR) starts
data exchange by starting the SPI clock generator.
After shifting the last (8th) bit, the SPI clock
generator stops and the SPIF flag changes to one.
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock.
Notice that you cannot write to the SPI Data Register
before transmission is completed, otherwise the
collision happens.
To get the received data you should read it from SPDR
before the next byte arrives.
We can use interrupts or poll the SPIF to know when a
byte is exchanged.
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Code Sequence on Master Mode
# define F_CPU 1000000UL // define crystal frequency for delay.h
#include <avr/io.h> // standard AVR header
#include <util/delay.h>
#define SS 4 // Slave Select is Bit No.4
#define MOSI 5 // Master Out Slave In is Bit No.5
#define MISO 6 // Master In Slave Out is Bit No.6
#define SCK 7 // Shift Clock is Bit No.7
void SPI_MasterInit(void){
// Set MOSI, SCK and SS as Output Pins
DDRB |= (1<<MOSI) | (1<<SCK) | (1<<SS) ;
DDRB &= ~(1<<MISO); // Set MISO as an Input Pin
// Enable SPI, Master mode, Shift Clock = CLK /16
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave, the function of
the SPI interface depends on the SS pin. If the SS is
driven high, MISO is tri-stated and the SPI interface
sleeps. Only the contents of SPDR may be updated in
this state.
When SS is driven low, the data will be shifted by
incoming clock pulses on the SCK pin.
SPIF changes to one when the last bit of a byte has
been shifted completely. Notice that the slave can
place new data to be sent into SPDR before reading
the incoming data; this is because in AVR there are
two one-byte buffers to store received data
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Code Sequence on Slave Mode
#define F_CPU 1000000UL // define crystal frequency for delay.h
#include <avr/io.h> // standard AVR header
#include <util/delay.h>
#define SS 4 // Slave Select is Bit No.4
#define MOSI 5 // Master Out Slave In is Bit No.5
#define MISO 6 // Master In Slave Out is Bit No.6
#define SCK 7 // Shift Clock is Bit No.7
void SPI_SlaveInit(void){
DDRB |= (1<<MISO); // Set MISO as an Output Pin
// Set MOSI, SCK and SS as Input Pins
DDRB &= ~(1<<MOSI) & ~(1<<SCK) & ~(1<<SS) ;
// Enable SPI as a Slave Device
SPCR = (1<<SPE);
}
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MAX7221 Interfacing and Prog…
If you want to connect four 7-segment LEDs directly to a
microcontroller you need 4 x 8 = 32 pins. This is not
feasible.
The MAX7221 IC is supports up to eight 7-segment LEDs. We
can connect the MAX7221 to the AVR chip using SPI protocol
and control up to eight 7-segment LEDs.
The MAX7221 contains an internal decoder that can be used to
convert binary numbers to 7-segment codes. That means we do
not need to refresh the 7-segment LEDs.
All you need to do is to send a binary number to the
MAX7221, and the chip decodes the binary data and displays
the number.
The device includes analog and digital brightness control,
an 8x8 static RAM that stores each digit, and a test mode
that forces all LEDs on.
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip.
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs. A resistor or a
potentiometer is the only
external component that you need.
Next, we will discuss the pins of
the MAX7221.
GND: Pin 4 and pin 9 are the ground. These should be
connected to system ground
Vcc: Pin 19 is the VCC and should be connected to the
+5V.this pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA.
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MAX7221 Pins and Connections
ISET: Pin 18 is ISET and sets the maximum
segment current. This pin should be
connected to VCC through a resistor.
A 10KΩ resistor can be connected to
this pin. If you want to manually
control the intensity of the
segments' light, you can replace the
resistor with a 50KΩ potentiometer.
CS :Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR. Serial
data is loaded into the chip while CS is low,
and the last 16 bits of the serial data are
latched on CS's rising edge.
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MAX7221 Pins and Connections
DIN: Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR. On
CLK's rising edge, data on this pin is loaded
into the internal shift register. Notice that
the MAX7221 uses the SPI Mode 0, that is,
read on rising edge and change on falling
edge..
CLK: Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR. On MAX7221 the
clock input is inactive when CS is high.
DOUT: Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus.
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MAX7221 data packet format
In MAX7221, data packets are 16 bits long (two bytes). You
should first make CS low before transmitting; then you
transmit two bytes of data and terminate the transmission
by making CS high.
The first byte (MSBs) of each packet contains the command
control bits, and the second byte is the data to be
displayed.
The upper four bits (D15-D12) of the command byte are
don't care and the lower four bits (D11-D8) are used to
identify the meaning of the data byte to be followed.
The second byte (D7-D0) of the two-byte packet is called
the data byte and is the actual data to be displayed or
control the 7-segment driver.
Table 17-3 shows the binary and hex values of each
command.
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Think in depth
In terms of readability, enumerations make better constants
than macros, because related values are grouped together.
In addition, enum defines a new type, so the readers of your
program would have easier time figuring out what can be
passed to the corresponding parameter.
A macro is a preprocessor thing, and the compiled code has
no idea about the identifiers you create. They have been
already replaced by the preprocessor before the code hits
the compiler. An enum is a compile time entity, and the
compiled code retains full information about the symbol,
which is available in the debugger (and other tools).
Prefer enums (when you can).
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References
https://www.newbiehack.com/MicrocontrollersABeginnersGuideIntroductionandInterfacinganLC
D.aspx
http://www.slideshare.net/MathivananNatarajan/asynchronous-serial-data-communication-and-
standards
https://www.slideshare.net/AnkitSingh13/uart-32550652
the avr microcontroller and embedded. System using assembly and c. Muhammad Ali Mazidi
Embedded Systems lectures “Engr. Rashid Farid Chishti”
https://www.corelis.com/education/SPI_Tutorial.htm
http://ftm.futureelectronics.com/2014/09/nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-
alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems/
http://www.byteparadigm.com/products/spi-storm/spi-storm-advanced-information/
https://stackoverflow.com/questions/17125505/what-makes-a-better-constant-in-c-a-macro-or-an-
enum
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