Microcontroller part 2

Embedded System
ENG.KEROLES SHENOUDA
1

Index (1/2)
 Polling Vs. interrupt
 What is an Interrupt?
 Interrupt Service Routine
 Interrupt vector Table
 Interrupt types
 Steps in executing an interrupt
 Interrupt Controller on ATMEGA32
 Edge trigger Vs. Level trigger in external
interrupts
 Interrupt Controller_LAB1
 Interrupt questiones
2

Index (2/2)
 What is a timer ?
 Timers in ATMEGA32
 Hand Writing Notes
 Timer interrupt
 TCC0 Registers
 Normal Mode
 CTC (Clear Timer on Compare match) mode
 Timer Lab 1 (OVF) interrupt
 Timer Lab 2 compare match interrupt
 Timer2
 The difference between Timer0 and Timer2
 Timer 1
 PWM Mode will be on the next Part
 References
3

Interrupts v/s Polling
Interrupt Polling
An interrupt is like ashopkeeper. If
one needs a service or product, he
goes to him and apprises him of his
needs. In case of interrupts, when the
flags or signals are received, they
notify the controller that they need to
be serviced.
The polling method is like
asalesperson. The salesman goes
from door to door while requesting to
buy a product or service. Similarly,
the controller keeps monitoring the
flags or signals one by one for all
devices and provides service to
whichever component that needs its
service.
5

Polling Vs. Interrupt
 Polling
 Ties down the CPU
while (true)
{
if(PIND.2 == 0)
//do something;
}
 Interrupt
 Efficient CPU use
 Has priority
 Can be masked
main( )
{
Do your common task
}
whenever PIND.2 is 0 then
do something
6

What is an Interrupt?
 An interrupt is a signal (an "interrupt request") generated by some event external to the CPU , which causes
the CPU to stop what it is doing (stop executing the code it is currently running) and jump to a separate piece of
code designed by the programmer to deal with the event which generated the interrupt request.
 This interrupt handling code is often called an ISR (interrupt service routine). When the ISR is finished, it
returns to the code that was running prior to the interrupt
 Some Common Interrupt Sources
 •Input pin state change
•Timer overflow
•Timer compare/match
•Timer capture
•UART RX char ready
•UART TX ready
•UART TX complete
•SPI transfer
•I2C transfer
•ADC conversion complete
•Watchdog
7

Interrupt Service Routine
 For every interrupt, there must be an interrupt service routine (ISR), or interrupt
handler.
 When an interrupt occurs, the microcontroller runs the interrupt service routine.
 For every interrupt, there is a fixed location in memory that holds the address of
its interrupt service routine, ISR.
 The table of memory locations set aside to hold the addresses of ISRs is called as
the Interrupt Vector Table.
8

Interrupt vector Table
 interrupt vector is the memory address of an
interrupt handler.
The interrupt vector for each interrupt
provided by the AVR microcontrollers can be
found in its datasheet.
 Please note here that the interrupt vectors
are apart of the microcontroller's program
memory. As such when utilizing interrupts this
section of memory should be reserved to store
pointers to interrupt handlers and not to store
regular programs
9

interrupt vector Table on ATMEGA 32 10

External HW Interrupt sources for
ATMEGA 32
1.The RESET interrupt - Triggered from pin 9.
2.External Interrupt 0 (INT0) - Triggered from pin 16.
11

Interrupt types
 you can distinguish three types of interrupts:
- Software/ Exceptions Interrupts
- Hardware Interrupts
12

Software Interrupt
 A software interrupt is caused either by an exceptional condition or a special
instruction in the instruction set which causes an interrupt when it is executed by
the processor.
 For example, if the processor's arithmetic logic unit runs a command to divide a
number by zero, to cause a divide-by-zero exception, thus causing the computer to
abandon the calculation or display an error message.
 Software interrupt instructions work similar to subroutine calls.
13

Hardware Interrupt
 A hardware interrupt is an electronic alerting signal sent to the processor from
an external device or internal Module, like a disk controller or an external
peripheral. For example, when we press a key on the keyboard or move the mouse,
they trigger hardware interrupts which cause the processor to read the keystroke or
mouse position.
CPU
Interrupt
Controller
Other
Modules
GPIO IO MUX
…..
…...
…..
…...
Eternal signal
can be configured
to be input
(external interrupt)
Internal interrupts from
Other Modules
Mange the interrupt Masking/priority
And send it to the CPU
14

Steps taken in servicing an interrupt
 1. The microcontroller completes the execution of the current instruction, clears the I
bit and stores the address of the next instruction that should have been executed
(the content of the PC) on the stack.
 2. The interrupt vector of the triggered interrupt is then loaded in the PC and the
microcontroller starts execution from that point up until is reaches a RETI instruction.
 3. Upon the the execution of the RETI instruction the address that was stored on the
stack in step 1 is reloaded in the PC and the I bit is re-enabled.
 4. The microcontroller then start executing instructions from that point. That is the
point that it left off when the interrupt was triggered.
15

Conclusion by hand writing
When the IRQ Happen
16

PA6 (ADC6)
AVCC
XTAL1
(OC1A) PD5
(SCK) PB7
(OC1B) PD4
RESET
VCC
GND
(TXD) PD1
(INT1) PD3
AGND
VCC
PA0 (ADC0)
PC7 (TOSC2)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA7 (ADC7)
PC4 (TDO)
PC3 (TMS)
PC6 (TOSC1)
PC5 (TDI)
PC0 (SCL)
PD7 (OC2)
PC2 (TCK)
PC1 (SDA)
ATmega32
PB0
PB1
(ICP) PD6
(INT2) PB2
(OC0/AIN0) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Steps in executing an interrupt
0000
0002
0002
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0012
0013
0014
0015
0016
Address Code
(INT0) PD2
SP
PC: 000D000E
0002
000F
(RXD) PD0
XTAL2
Stack
.INCLUDE "M32DEF.INC"
.ORG 0 ;location for reset
JMP MAIN
.ORG 0x02 ;location for external INT0
JMP EX0_ISR
MAIN: LDI R20,HIGH(RAMEND)
OUT SPH,R20
LDI R20,LOW(RAMEND)
OUT SPL,R20
SBI DDRC,3 ;PC.3 = output
SBI PORTD,2 ;pull-up activated
LDI R20,1<<INT0 ;Enable INT0
OUT GICR,R20
SEI ;Set I (Enable Interrupts)
LDI R30, 3
LDI R31, 4
ADD R30, R31
HERE:JMP HERE
EX0_ISR:IN R21,PORTC
LDI R22,0x08
EOR R21,R22
OUT PORTC,R21
RETI
000C000B000A000900080007000600050000000400120013001400150000

PA6 (ADC6)
AVCC
XTAL1
(OC1A) PD5
(SCK) PB7
(OC1B) PD4
RESET
VCC
GND
(TXD) PD1
(INT1) PD3
AGND
VCC
PA0 (ADC0)
PC7 (TOSC2)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA7 (ADC7)
PC4 (TDO)
PC3 (TMS)
PC6 (TOSC1)
PC5 (TDI)
PC0 (SCL)
PD7 (OC2)
PC2 (TCK)
PC1 (SDA)
ATmega32
PB0
PB1
(ICP) PD6
(INT2) PB2
(OC0/AIN0) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0000
0002
0002
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0012
0013
0014
0015
0016
Address Code
(INT0) PD2
SP
PC: 000D000E
0002
000F
(RXD) PD0
XTAL2
Stack
JMP MAIN
JMP EX0_ISR
OUT SPH,R20
LDI R20,LOW(RAMEND)
OUT SPL,R20
OUT GICR,R20
LDI R30, 3
LDI R31, 4
ADD R30, R31
HERE:JMP HERE
LDI R22,0x08
EOR R21,R22
OUT PORTC,R21
RETI
000C000B000A000900080007000600050000000400120013001400150004

PA6 (ADC6)
AVCC
XTAL1
(OC1A) PD5
(SCK) PB7
(OC1B) PD4
RESET
VCC
GND
(TXD) PD1
(INT1) PD3
AGND
VCC
PA0 (ADC0)
PC7 (TOSC2)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA7 (ADC7)
PC4 (TDO)
PC3 (TMS)
PC6 (TOSC1)
PC5 (TDI)
PC0 (SCL)
PD7 (OC2)
PC2 (TCK)
PC1 (SDA)
ATmega32
PB0
PB1
(ICP) PD6
(INT2) PB2
(OC0/AIN0) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0000
0002
0002
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0012
0013
0014
0015
0016
Address Code
(INT0) PD2
SP
PC: 000D000E
0002
000F
(RXD) PD0
XTAL2
Stack
JMP MAIN
JMP EX0_ISR
OUT SPH,R20
LDI R20,LOW(RAMEND)
OUT SPL,R20
OUT GICR,R20
LDI R30, 3
LDI R31, 4
ADD R30, R31
HERE:JMP HERE
LDI R22,0x08
EOR R21,R22
OUT PORTC,R21
RETI
000C000B000A00090008000700060005000000040012001300140015000E
Until
Reach
to
000E

PA6 (ADC6)
AVCC
XTAL1
(OC1A) PD5
(SCK) PB7
(OC1B) PD4
RESET
VCC
GND
(TXD) PD1
(INT1) PD3
AGND
VCC
PA0 (ADC0)
PC7 (TOSC2)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA7 (ADC7)
PC4 (TDO)
PC3 (TMS)
PC6 (TOSC1)
PC5 (TDI)
PC0 (SCL)
PD7 (OC2)
PC2 (TCK)
PC1 (SDA)
ATmega32
PB0
PB1
(ICP) PD6
(INT2) PB2
(OC0/AIN0) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0000
0002
0002
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0012
0013
0014
0015
0016
Address Code
(INT0) PD2
SP
PC: 000D000E
0002
000F
(RXD) PD0
XTAL2
Stack
JMP MAIN
JMP EX0_ISR
OUT SPH,R20
LDI R20,LOW(RAMEND)
OUT SPL,R20
OUT GICR,R20
LDI R30, 3
LDI R31, 4
ADD R30, R31
HERE:JMP HERE
LDI R22,0x08
EOR R21,R22
OUT PORTC,R21
RETI
000C000B000A00090008000700060005000000040012001300140015000E
INT0

PA6 (ADC6)
AVCC
XTAL1
(OC1A) PD5
(SCK) PB7
(OC1B) PD4
RESET
VCC
GND
(TXD) PD1
(INT1) PD3
AGND
VCC
PA0 (ADC0)
PC7 (TOSC2)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA7 (ADC7)
PC4 (TDO)
PC3 (TMS)
PC6 (TOSC1)
PC5 (TDI)
PC0 (SCL)
PD7 (OC2)
PC2 (TCK)
PC1 (SDA)
ATmega32
PB0
PB1
(ICP) PD6
(INT2) PB2
(OC0/AIN0) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0000
0002
0002
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0012
0013
0014
0015
0016
Address Code
(INT0) PD2
SP
PC: 000D000E
0002
000F
(RXD) PD0
XTAL2
Stack
JMP MAIN
JMP EX0_ISR
OUT SPH,R20
LDI R20,LOW(RAMEND)
OUT SPL,R20
OUT GICR,R20
LDI R30, 3
LDI R31, 4
ADD R30, R31
HERE:JMP HERE
LDI R22,0x08
EOR R21,R22
OUT PORTC,R21
RETI
000C000B000A000900080007000600050000000400120013001400150012
0F
00

PA6 (ADC6)
AVCC
XTAL1
(OC1A) PD5
(SCK) PB7
(OC1B) PD4
RESET
VCC
GND
(TXD) PD1
(INT1) PD3
AGND
VCC
PA0 (ADC0)
PC7 (TOSC2)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA7 (ADC7)
PC4 (TDO)
PC3 (TMS)
PC6 (TOSC1)
PC5 (TDI)
PC0 (SCL)
PD7 (OC2)
PC2 (TCK)
PC1 (SDA)
ATmega32
PB0
PB1
(ICP) PD6
(INT2) PB2
(OC0/AIN0) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0000
0002
0002
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0012
0013
0014
0015
0016
Address Code
(INT0) PD2
SP
PC: 000D000E
0002
000F
(RXD) PD0
XTAL2
Stack
JMP MAIN
JMP EX0_ISR
OUT SPH,R20
LDI R20,LOW(RAMEND)
OUT SPL,R20
OUT GICR,R20
LDI R30, 3
LDI R31, 4
ADD R30, R31
HERE:JMP HERE
LDI R22,0x08
EOR R21,R22
OUT PORTC,R21
RETI
000C000B000A000900080007000600050000000400120013001400150016
0F
00

PA6 (ADC6)
AVCC
XTAL1
(OC1A) PD5
(SCK) PB7
(OC1B) PD4
RESET
VCC
GND
(TXD) PD1
(INT1) PD3
AGND
VCC
PA0 (ADC0)
PC7 (TOSC2)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA7 (ADC7)
PC4 (TDO)
PC3 (TMS)
PC6 (TOSC1)
PC5 (TDI)
PC0 (SCL)
PD7 (OC2)
PC2 (TCK)
PC1 (SDA)
ATmega32
PB0
PB1
(ICP) PD6
(INT2) PB2
(OC0/AIN0) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0000
0002
0002
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0012
0013
0014
0015
0016
Address Code
(INT0) PD2
SP
PC: 000D000E
0002
000F
(RXD) PD0
XTAL2
Stack
JMP MAIN
JMP EX0_ISR
OUT SPH,R20
LDI R20,LOW(RAMEND)
OUT SPL,R20
OUT GICR,R20
LDI R30, 3
LDI R31, 4
ADD R30, R31
HERE:JMP HERE
LDI R22,0x08
EOR R21,R22
OUT PORTC,R21
RETI
000C000B000A000900080007000600050000000400120013001400150016000F

PA6 (ADC6)
AVCC
XTAL1
(OC1A) PD5
(SCK) PB7
(OC1B) PD4
RESET
VCC
GND
(TXD) PD1
(INT1) PD3
AGND
VCC
PA0 (ADC0)
PC7 (TOSC2)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA7 (ADC7)
PC4 (TDO)
PC3 (TMS)
PC6 (TOSC1)
PC5 (TDI)
PC0 (SCL)
PD7 (OC2)
PC2 (TCK)
PC1 (SDA)
ATmega32
PB0
PB1
(ICP) PD6
(INT2) PB2
(OC0/AIN0) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0000
0002
0002
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0012
0013
0014
0015
0016
Address Code
(INT0) PD2
SP
PC: 000D000E
0002
000F
(RXD) PD0
XTAL2
Stack
JMP MAIN
JMP EX0_ISR
OUT SPH,R20
LDI R20,LOW(RAMEND)
OUT SPL,R20
OUT GICR,R20
LDI R30, 3
LDI R31, 4
ADD R30, R31
HERE:JMP HERE
LDI R22,0x08
EOR R21,R22
OUT PORTC,R21
RETI
000C000B000A0009000800070006000500000004001200130014001500160010

Interrupt Controller
PROGRAM
ROM
PortsOSC
CPU
Timers
Other
Peripherals
Program
Bus Bus
RAM
I/O
PINS
EEPROM
Interrupt
Unit
SREG
GICR
TIMSK
CNVH ZSTSREG I
IVCE--INT2 IVSEL-INT0GICR INT1
TOIE0TOIE1OCIE1BTICIE1 OCIE0OCIE1ATOIE2TIMSK OCIE2
TOV0TOV1OCF1BICF1 OCF0OCF1ATOV2TIFR OCF2
40 PIN DIP
10
11
1
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
XTAL2
GND
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP) PD6
MEGA32
31
30
40
39
38
37
36
35
34
33
32
29
28
27
26
25
24
23
22
21
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
AGND
PC7 (TOSC2)
AVCC
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
35

Edge trigger Vs. Level trigger in external interrupts
SM1 SM0SM2MCUCR SE ISC00ISC01ISC10ISC11
41

Edge trigger Vs. Level trigger (Cont.)
- JTRFMCUCSR JTD PORFEXTRFBORFWDRFISC2
42

Interrupt priority
Highest
priority
Lowest
priority
43

Conclusion by hand writing
Simple task
48

Interrupt Controller_LAB1
Write C Code using the 3 eternal interrupts
External Interrupt 0 (INT0) - PD2. >> irq occur when “any logical change”
External Interrupt 1 (INT1) - PD3. >> irq occur when “rising edge”
External Interrupt 2 (INT2) - PB2. >> irq occur when “Falling edge”
We have also 3 leds (PD5,6,7) (led0,1,2).
Each interrupt just make the led 0N for 1 sec
The main function is always make all the leds off
49

For example
IRQ0 happen PC jump to ISR for IRQ0
LED 0 ON for 1secReturn to main and all LEDs
Being OFF
50

For example
Press on Bush Botton
IRQ0 and still pressing
(rising edge)
The led0 is on
For 1 sec
51

For example
The led0 is OFF
After 1 sec
Still pressing on Push Button
52

For example
Released so IRQ0 happen
Again because
(Falling edge)
And you already configured
IRQ0 to happen if any logical change happen
The led0 is ON
for1 sec
53

Solution
54

What happen if we pressing to interrupt
(int0 and int1) at the same time ?
55

Questions
 What is interrupt?
 What is interrupt latency?
 How you can optimize it?
 What is ISR?
 What is return type of ISR?
 Can we use any function inside ISR?
57

Questions
What is interrupt?
Hardware Software (Exception/Trap) Software (Instruction set)
Interrupt Request(IRQ) sent
from device to processor.
Exception/Trap sent from
processor to processor, caused
by an exceptional condition in
the processor itself.
A special instruction in the
instruction set which causes an
interrupt when it is executed.
In systems programming, an interrupt is a signal to the processor.
It can be emitted either by hardware or software indicating an event that needs
immediate attention.
Interrupts are a commonly used technique in real-time computing and such a
system is said to be interrupt-driven.
58

Questions
What is interrupt latency?
Interrupt latency is the time between the generation of interrupt and the time for
interrupt handler to process it.
How you can optimize it?
It is clear that the interrupt latency in a system can be shortened by locking parts of code into the cache. But
this will probably have negative effects on the performance of the rest of the system.
Another way
We may use polling on interrupt flag.
59

Questions
What is ISR?
ISR is interrupt service routine which is a short routine used to handle interrupt.
What is return type of ISR?
ISR does not return anything, it does not have parameter.
What is return type of ISR?
If a function could be reentrant, then we could use it.
60

What is a timer ?
 A timer in simplest term is a register. Timers generally have a resolution of 8 or 16
or 32 Bits.
 So a 8 bit timer is 8Bits wide so capable of holding value within 0-255. But this
register has a magical property ! Its value increases/decreases automatically at a
predefined rate (supplied by user).
 This is the timer clock. And this operation does not need CPU’s intervention.
62

A generic timer/counter
 Delay generating
 Counting
 Wave-form generating
 Capturing
Counter register
External
source
Oscillator
Counter/Timer
COUT
0
1
Flag

Timers in AVR
 8-bit and 16-bit timers
 two 8-bit timers and one 16-bit timer in ATmega32

Timers in ATMEGA32
Flag
Counter register
External
source
Oscillator
Counter/Timer
TCNTn
TCCRn
TOVn
OCRn
= OCFn
 TCNTn (Timer/Counter register)
 TOVn (Timer Overflow flag)
 TCCRn (Timer Counter control register)
 OCRn (output compare register)
 OCFn (output compare match flag)
Comment:
All of the timer registers are byte-addressable I/O
registers
65

OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR
TCNT0
TCCR0
TOV0
OCR0
= OCF0
Timer 0 (an 8-bit timer) 69

TCCR0
COM01WGM00FOC0 COM00 CS02 CS01 CS00 TCCR0WGM01
CS02 CS01 CS00 Comment
0 0 0 No clock source (Timer/Counter stopped)
0 0 1 clk (No Prescaling)
0 1 0 clk / 8
0 1 1 clk / 64
1 0 0 clk / 256
1 0 1 clk / 1024
1 1 0 External clock source on T0 pin. Clock on falling edge
1 1 1 External clock source on T0 pin. Clock on rising edge
Clock Selector (CS)
WGM00 WGM01 Comment
0 0 Normal
0 1 CTC (Clear Timer on Compare Match)
1 0 PWM, phase correct
1 1 Fast PWM
Timer Mode (WGM)
10-bit T/C Prescaler
Clear
0
CS00
CS01
CS02
T0
clkIO
PSR10
Timer/Counter0 clock
source
clk/1024
clk/256
clk/64
clk/8
0 1 2 3 4 5 6 7
70

0xFF
TCNT0
0
TOVTOV TOV
time
0TOV0:
1
FE
FF
TOV0 = 1
2
1
0
Normal Mode 73

$100
-$0E
$F2
14 = $0E
0 0 10 0
Counter Register
COUT
UP Load
8
$F2
Clear
0
CS00
CS01
CS02
T0
clkIO
PSR10
source
clk/1024
clk/256
clk/64
clk/8
0 1 2 3 4 5 6 7

Example 1: write a program that waits 14
machine cycles in Normal mode.
DDRB = 1<<5;
PORTB &= ~(1<<5); //PB5=0
while (1)
{
TCNT0 = 0xF2;
TCCR0 = 0x01;
while((TIFR&(1<<TOV0))==0);
TCCR0 = 0;
PORTB = PORTB^(1<<5);
}
$100
-$0E
$F2

How to calculate the delay generated
by the timer?
 1) Calculate how much a machine clock = 1/f
 2) Calculate how many machine clocks it waits.
 3) Delay = T * number of machine cycles

Example 1:if frequency 10 MHZ
Solution 1 (inaccurate):
1) Calculating T:
T = 1/f = 1/10M = 0.1µs
2) Calculating num of machine cycles:
$100
-$F2
$0E = 14
3) Calculating delay
14 * 0.1µs = 1.4 0µs

Generating Large Delays
 Using loop
 Prescaler
 Bigger counters
Clear
0
CS00
CS01
CS02
T0
clkIO
PSR10
source
clk/1024
clk/256
clk/64
clk/8
0 1 2 3 4 5 6 7
78

CTC (Clear Timer on Compare match) mode
TCNT0
0
OCF0OCF0 OCF0
time
0TOV0:
0
1
2
xx
TOV0 = no change
OCF0 = 1
OCR0
OCR0
0OCF0:
1
0xFF
79

Example 2: toggle let each 5 µs if you have a
frequency = Because XTAL = 10 by compare match
mode
 Because XTAL = 10 MHz, the counter counts up
every 0.1 µs. This means that we need 5 µs / 0.1
µs = 50 clocks. Therefore, we have OCR0= 49.
DDRB |= 1<<3;
PORTB &= ~(1<<3);
while (1)
{
OCR0 = 49;
TCCR0 = 0x09;
while((TIFR&(1<<OCF0))==0);
TCCR0 = 0; //stop timer0
PORTB.3 = ~PORTB.3;
}
82

Timer Lab 1 (OVF) interrupt
 Write a program uses Timer0 to
generate a square wave on pin
PORTB.5, while at the same time
data is being transferred from
PORTC to PORTD. +5
PORTCPORTD
88
PORTB.5
ATmega32
83

 ISR (TIMER0_OVF_vect) //ISR for Timer0 overflow
84

 using Timer0 and CTC mode generate a square wave on pin
PORTB.5, while at the same time data is being transferred from
PORTC to PORTD.
Timer Lab 2 compare match interrupt
Time (µS)
86

Timer2
 Timer0  Timer2
TCNT2
TCCR2
TOV2
OCR2
= OCF2
TCNT0
TCCR0
TOV0
OCR0
= OCF0
88

The difference between Timer0 and Timer2
 Timer0  Timer2
0 0 0 Timer/Counter stopped
0 1 0 clk / 8
0 1 1 clk / 64
1 0 0 clk / 256
1 0 1 clk / 1024
1 1 0 External clock (falling edge)
1 1 1 External clock (rising edge)
0 0 0 Timer/Counter stopped
0 1 0 clk / 8
0 1 1 clk / 32
1 0 0 clk / 64
1 0 1 clk / 128
1 1 0 clk / 256
1 1 1 clk / 1024
89

Timer 1
TCNT1H TCNT1LTCCR1B
TOV1
OCR1AH OCR1AL
= OCF1A
= OCF1B
OCR1BH OCR1BL
TCCR1A
90

Timer 1
WGM13 CS12 CS11 CS10WGM12ICNC1 ICES1 - TCCR1B
0 0 0 No clock source (Timer/Counter stopped)
0 1 0 clk / 8
0 1 1 clk / 64
1 0 0 clk / 256
1 0 1 clk / 1024
1 1 0 External clock source on T0 pin. Clock on falling edge
1 1 1 External clock source on T0 pin. Clock on rising edge
Clock Selector (CS)
COM1B1 WGM11FOC1BCOM1B0 WGM10FOC1ACOM1A0COM1A1 TCCR1A
Clear
0
CS10
CS11
CS12
T1
clkIO
PSR10
source
clk/1024
clk/256
clk/64
clk/8
0 1 2 3 4 5 6 7
91

Timer 1
WGM13 CS12 CS11 CS10WGM12ICNC1 ICES1 - TCCR1B
COM1B1 WGM11FOC1BCOM1B0 WGM10FOC1ACOM1A0COM1A1 TCCR1A
92

PWM Mode will be on the next Part
! 
93

References
 https://docs.google.com/viewer?a=v&pid=sites&srcid=ZmtlLnV0bS5teXxyaWR6dWFu
LXMtd2Vic2l0ZXxneDo2ODU0NzlkM2JkOTg4MjRk
 http://www.avrprojects.net/index.php/avr-projects/sensors/38-humidity-and-
temperature-sensor-dht11?showall=&start=1
 http://www.cse.wustl.edu/~lu/cse467s/slides/dsp.pdf
 http://www.avr-tutorials.com/
 Microprocessor: ATmega32 (SEE3223-10)
http://ridzuan.fke.utm.my/microprocessor-atmega32-see3223-10
 http://circuitdigest.com/article/what-is-the-difference-between-microprocessor-and-
microcontroller
 AVR Microcontroller and Embedded Systems: Using Assembly and C (Pearson
Custom Electronics Technology) 1st Edition
https://www.amazon.com/AVR-Microcontroller-Embedded-Systems-
Electronics/dp/0138003319
94

Microcontroller part 2

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Viewers also liked

Viewers also liked (20)

Similar to Microcontroller part 2

Similar to Microcontroller part 2 (20)

More from Keroles karam khalil

More from Keroles karam khalil (20)

Recently uploaded

Recently uploaded (20)

Microcontroller part 2