Micro unit 6

Impulse classes(Learn for perfection) PREMIER INSTITUTE OFFERING
TECHNICAL EDUCATION FOR ENGINEERING STUDENTS IIT,AIEEE,PUC & GATE,IES,PSU
[MICROPROCESSOR (UNIT-6)] (Memory Interface-1) Guided By:Anurag Trigun
Address:#902, 6th
‘A’ Main,1st
Block kormanagala near wipro gate,Bangalore-34 Ph-9060923518,9900398700
©copyright: subject matter to IMPULSE CLASSES, Bangalore-34
1. With a neat diagram, explain the working of 8086 in the minimum mode. Also give the timing
diagram of I/O write operation. [VTU2010]
Mode of operation for Intel 8086 namely the minimum mode. When only one 8086 CPU is to be
used in a micro computer system the 8086 is used in the minimum mode of operation. In this
mode the CPU issues the control signals required by memory and I/O devices. The level of the
pin MN/MX (active low) decides the operating mode of 8086. When MN/MX (active low) is high
the CPU operates in a minimum mode. From pin 24 to 31 issue two different sets of signals. One
set of signals is issued when the CPU is operating in the minimum mode.
Pin description for minimum mode
8086 Minimum Mode Block diagram
 For the minimum mode of operation the pin MN/MX (active low) is connected to 5V DC supply
that is MN/MX (active low) is equal to Vcc. The description of the pins from 24 to 31 for the
minimum mode is as follows:
 INTA (active low)(output) Pin No 24. Interrupt Acknowledge. On receiving interrupt signal the
processor issues an interrupt acknowledge signal.
 ALE (output) Pin No 25. Address Latch Enable. It goes high during T1. The microprocessor
sends the signal to latch the address in to the Intel 8282/8283 latch.
 DEN (output) Pin No 26. Data Enable. When Intel 8286/8287 octal bus transceiver is used, this
signal acts as an output enable signal. It is active low.

Address:#902, 6th
‘A’ Main,1st
 DT/R (active low)(output) Pin No 27. Data Transmit/Receive. When Intel 8286/8287 octal bus
transceiver is used, this signal controls the direction of data flow through the transceiver. When it
is high data are sent out. When it is low data are received.
 N/IO (active low)(output) Pin No 28. Memory or I/O access. When it is high the CPU wants to
access memory. When it is low, the CPU wants to access IO device.
 WR (active low)(output) Pin No 29. Write. When it is low the CPU performs memory or I/O
write operation.
 HLDA (output) Pin No 30. Hold Acknowledge. It is used by the processor when it receives hold
signal. When hold request is removed, HLDA goes low.
 HOLD (input) Pin No 31. Hold. When another device in the complex microcomputer system
wants to use the address and the data bus, it sends a hold request through this pin.
8086 systemin the minimum mode configuration :
 The microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to
logic 1 .
 In this mode, all the control signals are given out by the microprocessor chip itself. There
is a single microprocessor in the minimum mode system. The remaining components in
the system are latches, trans receivers, clock generator, memory and I/O devices. Latches
are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for

Address:#902, 6th
‘A’ Main,1st
separating the valid address from the multiplexed address/data signals and are controlled
by the ALE signal generated by 8086.
 Transreceivers are the bidirectional buffers and some times they are called as data amplifiers.
They are required to separate the valid data from the time multiplexed address/data signals. They
are controlled by two signals namely, DEN and DT/R.
 The DEN signal indicatesthe directionof data,i.e.fromorto the processor. The systemcontains
memoryforthe monitorand usersprogramstorage.Usually,EPROMare usedfor monitor
storage,while RAMforusersprogram storage.A systemmaycontainI/O devices.
 The opcode fetchand readcyclesare similar.Hence the timingdiagramcanbe categorizedin
twoparts, the firstis the timingdiagramforreadcycle and the secondis the timingdiagramfor
write cycle.
 The read cycle beginsinT1 withthe assertionof addresslatchenable (ALE) signal andalsoM/
IO signal.Duringthe negative goingedge of thissignal,the validaddressislatchedonthe local
bus.
 The BHE and A0 signalsaddresslow,highorbothbytes.FromT1 to T4 , the M/IO signal
indicatesamemoryor I/Ooperation.
 At T2, the addressisremovedfromthe local busandis sentto the output.The bus isthen
tristated.The read(RD) control signal isalsoactivatedinT2.
 The read (RD) signal causesthe addressdevice toenable itsdatabusdrivers.AfterRDgoeslow,
the validdata isavailable onthe databus.
 The addresseddevice will drivethe READYline high.Whenthe processorreturnsthe readsignal
to highlevel,the addresseddevice will againtristate itsbusdrivers.
 A write cycle alsobeginswiththe assertionof ALEandthe emissionof the address.
 The M/IO signal isagain
assertedtoindicate amemory
or I/O operation.InT2, after
sendingthe addressinT1, the
processorsendsthe datato be
writtento the addressed
location.
 The data remainson the bus
until middle of T4state.The
WR becomesactive atthe
beginningof T2(unlike RDis
somewhatdelayedinT2 to
provide time forfloating).
 The BHE and A0 signalsare
usedto selectthe properbyte orbytesof memoryor I/Oword to be read or write.
 The M/IO, RD and WR signalsindicate the type of datatransferasspecifiedintable below.

Address:#902, 6th
‘A’ Main,1st
2. Write the note on the read bus cycle for the 8086 microprocessor with the timing
diagram.
Timing diagram refers to the pictorial representation of the status of various pins during
the different cycles of a bus cycle.
The basic operation of reading/writing a byte from/to a memory location/a port is called a
machine cycle. The time taken to complete a machine cycle is represented as Tcy. A machine cycle
is made up of many states.
Timing Diagram for Memory Read Machine Cycle
One Bus Cycle
T1 T2 T3 T4
CLK
Address
Out In
DataAD0 -AD15
Out
Address Status
AD16 -AD1 9
S3-S6
MN/MX
M/IO
ALE
BHE/S7
RD
DT/R
DEN
BHE
S7

Address:#902, 6th
‘A’ Main,1st
InstructionCycle
The time takento fetchand execute anentire instructionisreferredtoasan instructioncycle.An
instructioncycle consistsof one ormore machine cycles.
In 8086, the conceptof a machine cycle isnotso relevant.The ExecutionUnit(EU) executesinstruction
incertainclock periods.These clockcyclesdonotconstitute anyformof machine cycles.The Bus
Interface Unit(BIU) fetchesinstructionsandoperandsfromthe memory.Anyexternal accesseitherto
the memoryor I/Odevice requiresfourclockperiods.Thisgroupof fourclock cyclesiscalledthe bus
cycle.There ismemoryor I/Oread buscycle;memoryor I/Owrite buscycle.
• The 4 processorclockcyclesare calledT states.Fourcyclesisthe shortesttime thatthe
processorcan use for carryingout a read or an inputcycle.
• At the beginningof T1,the processoroutputsS2, S1, S0, A16/S3…A19/S6, AD0..AD15 and
BHE#/S7.
• The 8288 buscontrollertransitionsthe ALEsignal fromlow tohigh,therebyallowingthe address
to pass throughthe transparentlatches(74HC373). The address,alongwiththe BHE# signal is
latchedwhenALEgoeslow,providingthe latchedaddressA0..A19.
• DuringT2 the processorremovesthe addressanddata.S3..S6 status isoutputon the upper4
address/statuslinesof the processor.
• The AD0..AD15 signalsare floatedasinputs,waitingfordatato be read.
• Data bus transceivers(74HC245) are enabledtowardsthe microprocessor(the READdirection)
by the DT/R# and DEN signals.
• The MRDC# (ie MEMR#) or IORC# (IOR#) signal is asserted.
• The signalsare maintainedduringT3.At the endof T3 the microprocessorsamplesthe input
data.
• DuringT4 the memoryand I/Ocontrol linesare de-asserted.
3. Write the note on the read bus cycle for the 8086 microprocessor with the timing
diagram.
The bus cycle starts with the transition of ALE high and the generation of valid status bits S2:0.
The bus cycle ends when WR transitions high (inactive), although data remains valid for one
additional clock. The two types of write bus cycles are as follows.

Address:#902, 6th
‘A’ Main,1st
Write Bus Cycle
The various events that take place in the write cycle (memory or I/O) can be summarized as follows.
• The 4 processor clock cycles are called T states. Four cycles is the shortest time that the processor
can use for carrying out a write or an output cycle.
• At the beginning of T1, the processor outputs S2, S1, S0, A16/S3…A19/S6, AD0..AD15 and
BHE#/S7.
• The 8288 bus controller transitions the ALE signal from low to high, thereby allowing the address
to pass through the transparent latches (74HC373). The address,along with the BHE# signal is
latched when ALE goes low, providing the latched address A0..A19.
• During T2 the processor removes the address and data. S3..S6 status is output on the upper 4
address/status lines of the processor.
• Output data is driven out on the AD0..AD15 lines.
• Data bus transceivers (74HC245) are enabled away from the microprocessor (the WRITE
direction) by the DT/R# and DEN signals.
• The MWRC# (ie MEMW#) or IOWC# (IOW#) signal is asserted at the beginning of T3.
• The signals are maintained during T3.

Address:#902, 6th
‘A’ Main,1st
• During T4 the memory and I/O control lines are de-asserted. In simple Intel Architecture systems,
the data is usually written to the memory or output device at the rising edge of the MWRC# or
IOWC# signal.
4. With a neat diagram, explain the working of 8086 in the maximum mode. Also give the timing
diagram of I/O write operation.
The maximum mode of operation the pin MN/MX (active low) is made low. It’s grounded. The
major difference between the minimum mode and the maximum mode configurations is the need
for the additional circuitry to translate the control signals. The circuitry is for converting the status
bits S1 (Active Low), S2 (Active Low) and S3 (Active Low) into the I/O and memory transfer
signals needed to direct data transfers, and for controlling the 8282 latches and 8286 transceivers.
From the status the 8288 is able to originate the address latch enable signal to the 8282s, the enable
and direction signals to the 8286 transceivers and the interrupt acknowledge signal to the interrupt
controller. The description of the pins from 24 to 31 is as follows:
Maximum mode of 8086

Address:#902, 6th
‘A’ Main,1st
QS1, QS0 (output) Pinno24 and25. InstructionQueue Status.These twopinsallow the system
external tothe processortointerrogate the statusof the processorinstructionqueue sothatit
can determine whichinstructionitiscurrentlyexecuting.The meaningof QS1and QS0 are as
follows:
QS1 QS0 Meaning
0 0 No operation
0 1 1st
byte of opcode fromqueue
1 0 Emptythe queue
1 1 Subsequentbyte fromqueue
S0, S1, S2 (active low) (output)PinNo26, 27 and 28. StatusSignals.These signalsare connected
to the bus controllerIntel 8288. The bus controllergeneratesmemoryandI/Oaccesscontrol
signals
8086 systemin maximum mode:
8086 systeminthe maximummode configuration.Inmaximummode configuration,inadditiontothe
latchesandbus transceivers,abuscontrollerisalsoemployedforthisconfiguration.The buscontroller
providescontrol signalsasshowninfigure.The importantsignalsare
MRDC (Active Low) MemoryRead Command
MWTC (Active Low) MemoryWrite Command

Address:#902, 6th
‘A’ Main,1st
IORC (Active Low) I/ORead Command
IOWC (Active Low) I/OWrite Command
AMWC (Active Low) AdvancedMemoryWrite Command.Itisa memory
write commandissuedearlierinthe machine cycle.Itgives memoryanearlyindicationof awrite
instruction.AIOWC(ActiveLow) AdvancedI/OWrite Command
5. Differentiate between8086 and8088 microprocessor.
8086
 It has 16 data linesD0-D15
 The instruction queue is of 6 bytes.
 From the memory the fetching of a
program is performed only once
there are 2 byte empty in queue.
 The BIU of 8086 is not as same as
in the 8088 but the EU is similar.
8088
 It has only8 data linesD0-D7
 it requires a 1 byte data width which
is generated after the de
multiplexing of AD0 to AD7 pins.
 The instruction queue is 4-bytes.
 Program fetching is performed as
soon as there is a byte empty in
queue

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