The document describes the signals of the 8086 microprocessor. It discusses the address/data and address/status lines that are time multiplexed. It explains the functions of signals like AD0-AD15, A16/S3-A19/S6, S4-S7, RD, READY, INTR, NMI, RESET, CLK and others. It provides timing diagrams for memory read and write cycles in minimum and maximum mode. It also discusses the different modes of operation like single processor mode and multi-processor mode.

1. Microprocessors and Microcontrollers – 11EC311
Signal Description of 8086

2. Pin Diagram of 8086
05/10/15 8086 Signal Description - MPMC 2

3. Signal Description
AD15-AD0:
●
●
●
Time Multiplexed Address/Data Line
T1-Address Cycle
T2, T3, TW, T4- Data Cycle
● T are clock states of machine cycle
S4 S3 Indication
A19/S6- A16/S3: 0 0 Alternate Data
●
●
●
Time Multiplexed Address/Status Lines
During T1- Address line
During I/O these lines are low.
0 1
1 0
1 1
Stack
Code or None
Data
●
S5 -- status of IE Flag at beginning of each cycle.
●
S4 , S3 indicate segment register used for memory
●
●
Latches separate addr and status bits
S6 is always low
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4. Signal Description
●
BHE/S7: BUS HIGH ENABLE BHE A0 Indication
– Indicates a transfer over D8-D15 0 0 Whole Word
●
– S7 is not currently used.
RD: Read
0 1 Upper byte
from/to odd addr
– 0 – Performing Read 1 0 Lower byte
from/to even
addr
●
READY: 1 1 None
– Acknowledgement from slow devices that they completed transfer
●
TEST:
–
–
–
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0 – Execution continues
1 – Idle State
Examined by WAIT instruction
8086 Signal Description - MPMC 4

5. Signal Description
● INTR: Interrupt Request
–
–
Level triggered input
Sampled during last clock cycle of each instruction
to determine availability of request.
● NMI: Non-maskable interrupt
– Causes type 2 interrupt ( Cannot be Masked)
● RESET:
– Stops execution and starts from
FFFF0H● CLK: Clock Input
– Square wave of 33% duty Cycle. Range: 5Mhz- 10
MHz●
●
●
VCC: +5V
GND: Ground
MN/MX: 1-- Min Mode 0-- Max Mode
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6. Signal Description – Minimum Mode Pins
● M/IO: Memory/IO Operation
–
–
–
0 – I/O Operation
1 – Memory Operation
Active from T4 to present T4
● INTA: Interrupt Acknowledge
–
–
0 – Processor accepted interrupt.
Low during T2,T2,TW of interrupt acknowledge
cycle.
● ALE: Address Latch Enable
–
–
Indicates availability of valid address on
address/data line
Connected to latch enable input of Latches
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7. Signal Description – Minimum Mode Pins
● DT/R:Data Transmit or receive
–
–
–
1-Transmit
0- Receive
Same timing as M/IO
● DEN: Data Enable
–
–
–
Availability of valid data over address/data lines
Used to enable transreceivers to separate data from
multiplexed address/data signal.
Active from middle of T2 to middle of T4.
● HOLD/HLDA: Hold Acknowledge.
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–
–
–
1 – Another master is requesting bus access
After hold processer gives hold acknowledge signal in
middle of next clock cycle after current instruction cycle.
0 – HDLA is also low
8086 Signal Description - MPMC 7

8. Signal Description – Maximum Mode Pins
●
●
S2,S1,S0:
– Status lines
– Active from T4 to current T1,T2
LOCK:
– 0 – Other system bus
masters will be prevented
from gaining system bus.
– Activated by LOCK prefix
Instruction..
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Indication
Interrupt
Acknowledge
Read I/O Port
Write I/O Port
Halt
Code access
Read memory
Write memory
Passive
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9. Signal Description – Maximum Mode Pins
●
QS1, QS0 – Queue Status QS1 QS0 Indication
– Status of prefetch queue. 0 0 No Operation
●
RQ/GT0, RQ/GT1:
– Request/Grant
– Used by other local bus
0
1
1
1
0
1
First byte of opcode
from the queue
Empty Queue
Subsequent byte
from the queue
–
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masters to force the processor to release the local bus at
end of processor’scurrent bus cycle.
RQ/GT0 have high priority than RQ/GT1.
8086 Signal Description - MPMC 9

10. General Timing Diagram
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11. Possible Operations
●
●
●
●
Memory Read
Memory Write
IO Read
IO Write
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12. Modes of Operation: Minimum Mode
●
●
Single Processor Mode
Latches are D-Flipflops( 74LS373/8282)
–
–
Demux address from addr/data signal
3 octal latches are required
● Transreceivers are bidirectional buffers(74245)
–
–
–
Demux data from addr/data signal
Controlled using DEN and DT/R 2
octal data buffers
● M/IO, RD , DEN indicate type of data transfer.
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13. 8086 Minimum Mode
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14. Minimum Mode Read Cycle Timing Diagram
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15. Minimum Mode Write Cycle Timing Diagram
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16. Modes of Operation: Maximum Mode
●
●
●
●
●
●
Multi Processor Mode
Bus controller chip IC8288 derives outputs from given
signals.
ALE,DEN,DT/R,MRDC,MWTC,AMWC,IORC,IOWC,AIOWC
Memory Read Control, Memory Write Control
Advanced Memory Write Control
IO Read Control, IO Write Control
Advanced IO Write Control
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17. 8086 Maximum Mode
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18. Maximum Mode Memory Read Timing Diagram
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19. Maximum Mode Memory Write Timing Diagram
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20. References
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https://www.sites.google.com/site/sripathroykoganti/my-forms
D.V.Hall “Microprocessor and Interfacing”, 2nd Edition Tata McGraw
Hill Publishing Company,2006.
A.K. Ray & K. M Bhurchandi, “Advanced Microprocessors &
peripherals”, Tata Mc Graw Hill Publishing Company 2002.
Rajkamal, “Microcontrollers - Architecture, Programming, Interfacing
& System Design”, 2 nd edition, Pearson Education.
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21. Thank You
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