microprocessor notes

1. Impulse classes(Learn for perfection)
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[MICROPROCESSOR (UNIT-8)] (INTERRUPT) Guided By:Anurag Trigun
Address:#902, 6th
‘A’ Main,1st
Block kormanagala near wipro gate,Bangalore-34 Ph-9060923518,9900398700
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1. Explain the interrupt vector table in brief.
 An interrupt vector table that stores pointers to the associated interrupt handlers. This table is
located at base address zero.
 Each entry in this table consists of a CS:IP pointer to the associated ISRs .
 Each entry or vector requires four bytes:
» Two bytes for specifying CS
» Two bytes for the offset
 Up to 256 interrupts are supported (0 to 255)
 . These pointers identify the starting location of their service routines in program memory. The
contents of this table may be either held as firmware in EPROMs or loaded into RAM as part of
the system initialization routine.
 Type 0: Divide error – Division overflow or division by zero
 Type 1: Single step or Trap – After the execution of each instruction when trap flag set
 Type 2: NMI Hardware Interrupt – ‘1’ in the NMI pin
 Type 3: One-byte Interrupt – INT3 instruction (used for breakpoints)
 There is a program associated with every There is a program associated with every interrupt.
interrupt.
 When an interrupt is invoked, a CPU runs a When an interrupt is invoked, a CPU runs a program
for a service program for a service an interrupt service an interrupt service routine (ISR). routine
(ISR).

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[MICROPROCESSOR (UNIT-8)] (INTERRUPT) Guided By:Anurag Trigun
Address:#902, 6th
‘A’ Main,1st
Block kormanagala near wipro gate,Bangalore-34 Ph-9060923518,9900398700
©copyright: subject matter to IMPULSE CLASSES, Bangalore-34
 The address of the interrupt service routine is The address of the interrupt service routine is
shown in the interrupt vector table. shown in the interrupt vector table.
 Four bytes of memory are allocated for every Four bytes of memory are allocated for every
interrupt. interrupt. ¾ The memory space of 1024 bytes (256x4=1024) The memory space of
1024 bytes (256x4=1024) are set aside for the interrupt vector table. are set aside for the
interrupt vector table.
2. Differentiate between memory mapped I/O and I/O mapped I/O.
Isolated I/O No. Memory Mapped I/O
Isolated I/O uses separate
memory space.
01 Memory mapped I/O uses
memory from the main memory.
Limited instructions can be
used. Those are IN, OUT, INS,
OUTS.
02 Any instruction which
references to memory can be
used.
The addresses for Isolated I/O
devices are called ports.
03 Memory mapped I/O devices
are treated as memory locations
on the memory map.
IORC & IOWC signals expands
the circuitry.
04 IORC & IOWC signals has no
functions in this case which
reduces the circuitry.
Efficient I/O operations due to
using separate bus
05 Inefficient I/O operations due to
using single bus for data and
addressing
Comparatively larger in size 06 Smaller in size
Uses complex internal logic 07 Common internal logic for memory
and I/O devices
Slower operations 08 Faster operations
3. Explain the operation of 8259, with near block diagram.
The 8259 A has eight interrupt request inputs, TR2 IR0. The 8259 A uses its INT output to
interrupt the 8085A via INTR pin. The 8259A receives interrupt acknowledge pulses from the at
its input. Vector address used by the 8085 A to transfer control to the service subroutine of the
interrupting device, is provided by the 8259 A on the data bus. The 8259A is a programmable
device that must be initialized by command words sent by the.

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[MICROPROCESSOR (UNIT-8)] (INTERRUPT) Guided By:Anurag Trigun
Address:#902, 6th
‘A’ Main,1st
Block kormanagala near wipro gate,Bangalore-34 Ph-9060923518,9900398700
©copyright: subject matter to IMPULSE CLASSES, Bangalore-34
Data bus buffer: This 3- state, bidirectional 8-bit buffer is used to interface the 8259A to the
system data bus. Control words and status information are transferred through the data bus buffer.
Read/Write & control logic: The function of this block is to accept OUTPUT commands from the
CPU. It contains the initialization command word (ICW) register and operation command word
(OCW) register which store the various control formats for device operation. This function block
also allows the status of 8159A to be transferred to the data bus.
Interrupt request register (IRR): IRR stores all the interrupt inputs that are requesting service.
Basically, it keeps track of which interrupt inputs are asking for service. If an interrupt input is
unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will be set.
Interrupt mask register (IMR): The IMR is used to disable (Mask) or enable (Unmask) individual
interrupt inputs. Each bit in this register corresponds to the interrupt input with the same number.
service register (ISR): The in service registers keeps tracks of which interrupt inputs are currently
being serviced. For each input that is currently being serviced the corresponding bit will be set in
the in service register.
Cascade buffer/comparator: This function blocks stores and compare the IDS of all 8259A’s in
the reg. The associated 3-I/O pins (CAS0-CAS2) are outputs when 8259A is used a master.

4. Impulse classes(Learn for perfection)
PREMIER INSTITUTE OFFERING TECHNICAL EDUCATION FOR ENGINEERING STUDENTS IIT,AIEEE,PUC & GATE,IES,PSU
[MICROPROCESSOR (UNIT-8)] (INTERRUPT) Guided By:Anurag Trigun
Address:#902, 6th
‘A’ Main,1st
Block kormanagala near wipro gate,Bangalore-34 Ph-9060923518,9900398700
©copyright: subject matter to IMPULSE CLASSES, Bangalore-34
4. What is DMA ? briefly explain the two different DMA operation.
 A direct memory access (DMA) is an operation in which data is copied (transported) from
one resource to another resource in a computer system without the involvement of the CPU.
 The task of a DMA-controller (DMAC) is to execute the copy operation of data from one
resource location to another.
 The copy of data can be performed from: - I/O-device to memory - memory to I/O-device
- memory to memory - I/O-device to I/O-device.
 A DMAC is an independent (from CPU) resource of a computer system added for the
concurrent execution of DMA-operations. The first two operation modes are ’read from’
and ’write to’ transfers of an I/O-device to the main memory, which are the common
operation of a DMA-controller.
 operating modes exist for DMACs. The simplest one is the single block transfer copying a block of
data from a device to memory.
 single block transfer - chained block transfers - linked block transfers - fly-by transfers All these
operations normally access the block of data in a linear sequence. Nevertheless, there are more
usefull access functions possible, as there are: constant stride, constant stride with offset,
incremental stride.
 The DMAC increments the memory block address and continue with this loop until the block
length is reached. The completion of the DMAoperation is signaled to the processor by sending
an IRQ signal or by setting a memory semaphore variable, which can be tested by the CPU.
>>multiple channels physical addressing,
>>address translation snooping for cache coherency.
 DMA control signals (REQ, ACK) are used to signal the availability of values in the I/Odevice for
transportation.

5. Impulse classes(Learn for perfection)
PREMIER INSTITUTE OFFERING TECHNICAL EDUCATION FOR ENGINEERING STUDENTS IIT,AIEEE,PUC & GATE,IES,PSU
[MICROPROCESSOR (UNIT-8)] (INTERRUPT) Guided By:Anurag Trigun
Address:#902, 6th
‘A’ Main,1st
Block kormanagala near wipro gate,Bangalore-34 Ph-9060923518,9900398700
©copyright: subject matter to IMPULSE CLASSES, Bangalore-34
5. Explain the hardware and software interrupt.
The primary sources of interrupts, however, are the PCs timer chip, keyboard, serial ports,
parallel ports, disk drives, CMOS real-time clock, mouse, sound cards, and other peripheral
devices.
MASKABLE INTERRUPT
 Whenever an external signal activates the INTR pin, the microprocessor will be interrupted only if
interrupts are enabled using set interrupt Flag instruction. If the interrupts are disabled using clear
interrupt Flag instruction, the microprocessor will not get interrupted even if INTR is activated.
That is, INTR can be masked.
 Hardware pins that request interrupt (INTR & NMI) and one hardware pin (INTA) that
acknowledges the interrupt requested through INTA.
NON-MASKABLE INTERRUPT (NMI)
 The processor provides a single non-maskable interrupt pin (NMI) which has higher priority than
the maskable interrupt request pin (INTR). A typical use would be to activate a power failure
routine. The NMI is edgetriggered on a LOW-to-HIGH transition. The activation of this pin causes
a type 2 interrupt. NMI is required to have a duration in the HIGH state of greater than two CLK
cycles, but is not required to be synchronized to the clock.
. Software interrupt Instructions
There are instructions in 8086 which cause an interrupt. They are
 INT instructions: INT instruction calls the interrupts service procedures that begins at address
represented in vector number
INTO: INTO instruction checks the overflow flag (OF), if OF =1, the instruction calls the
procedure whose address is stored in interrupt vector type number 4.
INT3: INT3 instruction is often used as a breakpoint interrupt because it is easy to
insert a 1-byte instruction into a program, breakpoints are often used to debug faulty
software.