Microprocessor 8086 in Brief. :)

1. Intel 8086 Microprocessor
By :
• Nitish Nagar
• Priyanka Khandelwal
• 6CS9(X)
• Batch – 2008-2012

2. Difference Between 8085 and 8086
• The most significant difference between the Intel 8085 and 8086
microprocessors is that the 8085 is an 8-bit system, NMOS
microprocessor and the 8086 is a 16-bit system, HMOS
microprocessor. This difference allows the 8086 system to have a
much larger set of operational instructions and can make
calculations to more significant places.
• 8085 contains 16-bit address bus and 8-bit data bus .8086 contains
20-bit address bus and 16-bit data bus.
• In 8085 the clock speed is 3MHZ where as in 8086 the clock speed
is 5MHZ.
• An 8085 processor has 6,500 transistors in its programming circuit
boards, compared with 29,000 transistors in an 8086 processor. This
means there are roughly 4.5 times more transistors in an 8086
processor, leading to a much faster processing rate.

3. • 8086 has a special concept called as memory segmentation. It
allows parallel processing, while 8085 does not.
• 8085 consists 74 instructions. 8086 consists 117 instructions. In 8086
four 16 bit registers are available and pin no 33- min/(~max) it selects
minimum mode when this pin is high otherwise it selects maximum mode.
• 8086 has 4 segment registers which are not peresent in 8085. also it has
preftech queue which stores instructions ahead of time which is not present
in 8085. The BIU and execution unit in 8086 works parallely which improves
its performance.
• Pipelining concept is not seen in 8085 and
• The 8086 had more registers and many more instructions.
• Both processors require a 5-volt power supply and both have a 40-pin
DIP, or dual inline package, which is how they plug into the circuit board in
the computer or device where they are being used. They also are both
roughly from the same era of computing and are now outdated.

4. Pin Diagram of 8086
AD15-AD0
ADDRESS DATA BUS: These lines constitute
the time multiplexed memory or i/o address
and data bus .
ALE (ADDRESS LATCH ENABLE): A HIGH on
this line causes the lower orders 16-bit address
bus can be used as data bus.
READY : READY is the acknowledgement
from the addressed memory or i/o device that
will be complete the data transfer .
INTR : INTERRUPT REQUEST is a level
triggered input which is sample during the last
clock cycle of each instruction to determine if
the processor should enter into interrupt
acknowledgment operation .
INTA : INTERRUPT ACKNOWLEDGEMENT
from the mp.
RESET : It causes the processor to
immediately terminate its present activity.

5. Pin Diagram of 8086
• 8086 operates in single processor (minimum mode) or multi
processor (maximum mode) configurations to achieve high
performance.
• The 8086 signals can be categorized in 3 groups.
I. Signals having common functions in minimum as well as
maximum mode.
II. Signals which have special functions for minimum mode.
III. Signals which have special functions for maximum mode.
I. Signals common for both minimum & maximum mode.
1. AD15-AD0 :
These are the time multiplexed memory I/O address & data lines.
Address remains on the lines during T1 state, while the data is
available on the data bus during T2,T3,TW,T4.
These lines are active high, and float to a tristate during interrupt
acknowledge and local bus hold acknowledge cycles.
2. A19/S6, A18/S4, A17/S4, A16/S3
These are the time multiplexed address and status lines. During T1,
these are the most significant address lines for memory operations.
During I/O operations these lines are low.

6. • The status of the Interrupt Enable Flag (IF) bit (displayed on S5) is updated
at the beginning of each clock cycle.
• S4, S3 : together indicates which segment register is presently being used for
memory access.
• These lines float at tristate off during the local bus hold acknowledge.
S4 S3 Indications
0 0 Alternate data
0 1 Stack
1 0 Code or none
1 1 Data
3. BHE/S7: Bus High Enable/Status
The bus high enable signal is used to indicate the transfer of data over the higher order
(D15-D8) data bus.
Whole word = Upper Byte + Lower Byte
BHE A0 Indication
0 0 Whole word i.e AD15 – AD0
0 1 Upper byte from or to i.e AD15-AD8
1 0 Lower byte from or to even address i.e AD7-AD0
1 1 None

7. 4. RD: Read
Read signal , when low, indicates the peripherals that the processor is performing
a memory or I/O operation.
RD is active low & shows the state for T2, T3, TW of any read cycle. The signal
remains tristated during the ‘hold acknowledge’.
5. READY:
This is the acknowledgement from the slow devices or memory that they have
completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator.
6. RESET:
This input causes to processor to terminate the current activity
and start execution from FFFF0H i.e reinitialize the system.
7. INTR: Interrupt Request:
This signal is sampled during the last clock cycle of each instruction to determine
the availability of the request. If any interrupt request is pending the processor
enters the interrupt acknowledge cycle.
8. TEST:
This input is examined by a ‘WAIT’ instruction. If TEST=0, execution will
continue, else processor remains in an idle state. Input is synchronized by clock
cycle.
9. NMI: Non-Maskable Interrupt
The NMI is not maskable internally by software. A transition from low to high
initiates the interrupt response at the end of the current instruction.
10. CLK: Clock Input
The clock input provides the basic timing for processor Operation and bus control
activity.
11. Vcc:
+5V power supply for the operation of the internal circuit.
12. GND:
Ground for the internal circuit.

8. Minimum mode operation of 8086
1.M/IO-:
This line becomes active in the previous T4 and remains active
till final T4 of the current cycle.When it is high CPU wants to access memory.
2. INTA: Interrupt Acknowledge
This signal is low, the processor has accepted the interrupt. It is
active low during T2, T3, Tw of each interrupt acknowledge
cycle.
3. ALE: Address Latch Enable
This output signal indicates the availability of the valid address
on the address/data lines & it is connected to latch enable input
of latches. This signal is active high and is never tristated.
4. DT/R: Data transmit/Receive
This output is used to decide the direction of data flow through
the transreceivers (i.e bidirectional buffers)
DT/R = 1 Processor sends out data
DT/R = 0 Processor receives data
DT/R = S1 in maximum mode.

9. Maximum mode operation of 8086
1.S2, S1, S0: Status lines
These lines active during T4 of the previous cycle & remain active during T1 & T2
of the current bus cycle.
2. LOCK: This output pin indicates that other system bus masters will be
prevented from gaining the system bus, while the LOCK=0. The LOCK signal is
activated by the LOCK prefix instruction and remains active until the completion
of the next instruction. This floats to tri-state off during ‘hold acknowledge’.
3. QS1, QS0 : Queue status These lines give information about the status of the
code-queue. These are active during the CLK cycle after which the queue
operation is performed.The 8086 architecture has a 6-byte instruction pre-fetch
queue.
4. RQ/GT0, RQ/GT1: Request/Grant These pins are used by other local bus
masters, in maximum mode, to force the processor to release the local bus at the
end of the processor’s current bus cycle.
Each of the pins is bidirectional with RQ/GT0 having higher priority than
RQ/GT1.

10. Architecture of 8086:
The 8086 is divided into two units –Execution Unit (EU) & Bus Interface Unit
(BIU). Both units operate asynchronously to give the 8086 an overlapping
instruction fetch and execution mechanism which is called as Pipelining. This
results in efficient use of the system bus and system performance.
• The BIU fetches instructions, reads and writes data, and computes the
20-bit address.
• The EU decodes and executes the instructions using the 16-bit ALU.
– Decodes instructions fetched by the BIU
– Generate control signals
– Executes instructions
The BIU and execution unit in 8086 works parallely which improves its
performance.
The general purpoe register, Stack Pointer, Base Pointer, Index Register, ALU, Flag
Register, Instruction Decoder, an timing and control Unit constitute Execution unit.
The segment register, instruction pointer and 6byte instructionqueueare associated
with Base Interface Unit.

11. Architecture :

12. Bus Interface Unit :
The BIU contains the following registers:
• CS - the Code Segment Register
• DS - the Data Segment Register
• SS - the Stack Segment Register
• ES - the Extra Segment Register
• IP - the Instruction Pointer
Segment Registers
8086 has segmented memory. 1MB memory is divided into
16 logical segments (16x64K)
CS – Code Segment register used for addressing a memory
location in the code segment of the memory where the
executable program is stored.
SS – Stack Segment register refers to stack segment of stack
data
DS – Data Segment register point to the data segment of the
memory, where the data is resided.
ES – Extra Segment register also refers to a segment which
essentially is another data segment of the memory. (It also
points to data segment).

13. Execution Unit :
1. Control circuit – which directs internal operations.
2. Instruction Decoder – translates instructions fetched from memory into a
series of actions which the EU carries out.
3. ALU – Add, sub, increment, decrement, complement, shift binary
numbers.
4. General Data Registers
AX = (AH+AL) Accumulator.
BX - used as an offset storage for forming physical address.
CX - default counter in case of string and loop instructions.
DX – implicit operand or destination register in case of a few instruction.
5. Pointers and Index Registers
Pointers contain offset within the particular segments.
IP – Instruction Pointer register holds the 16-bit address or offset of the
next code byte within code segment .
20 bit address = offset of IP + Segment base address in CS.
BP – Base Pointer contains Source Index (SI) register and Destination
Index (DI) register.
SP – Stack Pointer register in the Execution Unit holds the 16-bit offset
from the start of the segment to the memory location where a word was
most recently stored on the stack (i.e top of stack).
SP,SI,DI – these 3 register are used for temporary storage of data.

14. 6. Flag Registers
A flag is a flip-flop that indicates some condition produced by the execution
of an instruction or controls certain operations of the EU.
A 16-bit flag register in the EU contains 9 active flags, 6 flags indicate
some condition produced by an instruction(conidtion flags), 3 flags are
control flags.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X O D I T S Z X Ac X P X Cy
O – Overflow Flag
S – Sign Flag
Z – Zero Flag
Ac – Auxiliary Carry Flag
P – Parity Flag
Cy – Carry Flag
D – Direction
I – Interrupt Flag
T – Trap Flag
X – Not used

15. How to calculate Physical address
• Segment registers hold the base address of where a particular segment
begins in memory. There is the code segment (CS), data segment (DS),
stack segment (SS), and extra segment (ES).
Segment registers are 16-bit registers which are ASSUMED to be holding a
20 bit number, because it is assumed you will add a zero to the end. For
example, if CS register is holding the hexadecimal value "13A6", then this
value is actually representing the address "13A60".
To calculate a physical address, you take the address (called the logical
address) and add it to the segment address.
• For example, if you wanted to calculate the physical address which relates
to logical address "1356" in the stack segment - you would also need to
know what value is in the SS register, lets assume "2345":
Add the zero to the end of the segment address:
23450
Then add the two addresses together:
23450 + 1356 = 247A6

16. • The physical address is calculated by finding out where the
segment starts, then adding to it the offset address.
• One of the segment registers will tell you where the segment
begins.
• Let's assume that the segment register is holding the value
"A45C". In this case, the segment begins at the 20 bit address
"A45C0".
• Add to that the offset address:
A45C0 + 4B32 = A90F2.
• Therefore the address A90F2 is the 20 bit physical address
that maps to the segment, offset address A45C:4B32

17. Interrupts
The processor has the following interrupts :
• INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using
STI/CLI instructions or using more complicated method of updating the FLAGS register
with the help of the POPF instruction. When an interrupt occurs, the processor stores
FLAGS register into stack, disables further interrupts, fetches from the bus one byte
representing interrupt type, and jumps to interrupt processing routine address of which
is stored in location 4 * <interrupt type>. Interrupt processing routine should return with
the IRET instruction.
• NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority then the maskable interrupt.
• Software interrupts can be caused by:
• INT instruction - breakpoint interrupt. This is a type 3 interrupt.
• INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
• INTO instruction - interrupt on overflow
• Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When
the CPU processes this interrupt it clears TF flag before calling the interrupt processing
routine.
• Processor exceptions: divide error (type 0), unused opcode (type 6) and escape
opcode (type 7).
• Software interrupt processing is the same as for the hardware interrupts.

18. Addressing Modes of 8086 :
The way in which an operand is specified is called its addressing mode.
I. Data-related addressing modes
II. Branch addressing modes
I. Data-related addressing modes :
1. Immediate addressing mode
The datum is either 8 bits or 16 bits long and is part of the instruction.
2. Direct addressing modes
The 16 bit effective address (EA) of the datum is part of the instruction
3. Register addressing modes
The datum is in the register that is specified by the instruction.
4. Register Indirect
The effective address of the datum is in the base register BX or an index register that is
specified by the instruction.
5. Register Relative
The effective address is the sum of an 8 or 16 bit displacement and the contents of
base register or an index register.
6. Based Indexed
The effective address is the sum of a base register and an index register.
7. Relative Based Indexed
The effective address is the sum of an 8 or 16-bit displacement and a based indexed
address.

19. Instruction Set
Instruction set of Intel 8086 processor consists of the following
instructions:
1) Data moving instructions.
2) Arithmetic - add, subtract, increment, decrement, convert
byte/word and compare.
3) Logic - AND, OR, exclusive OR, shift/rotate and test.
4) String manipulation - load, store, move, compare and scan for
byte/word.
5) Control transfer - conditional, unconditional, call subroutine
and return from subroutine.
6) Input/Output instructions.
7) Other - setting/clearing flag bits, stack operations, software
interrupts, etc.

20. Assembler Directives
• An assembler is a program used to convert an assembly language
program into the equivalent machine code modules which may
further be converted to executable codes.
• It decides the address of each label and substitutes the values for each
of the constant and variables.
It then forms the machine code for the mnemonics and data in the
assembly language program (ALP).
• The logical errors or other programming errors are not found out by
the assembler.
To know errors hints are required from the programmer.
• The hints are given to the assembler using some predefined
alphabetical strings called Assembler Directives, which help the
assembler to correctly understand the ALPs to prepare the codes.

21. Macros
• A macro is group if instructions we bracket and give a name to at
the start of our program. Each time we “call” the macro in our
program, the assembler will insert the defined group of instructions
in place of the “call”.
• Every time a macro name in the program, replace it with the group
of instructions defined as that macro at the start of the program.
This process is known as expanding the macro or macro expansion.
• Using a macro avoids the overhead time involved in calling,
returning from a procedure.
• A disadvantage of generating in-line code each time a macro is
called is that this will make the program take up more memory than
using a procedure.

22. Nitish Nagar
Priyanka Khandelwal
6CS9(X)
Batch 2008–2012
Thank You