2. After completing the subject you will gain knowledge
and will be eligible for the following post in an
organization
Electronics Engineer
IOT Engineer
Embedded system Engineer
Embedded Trainer
Embedded Developer
Field Sales Executive
Telecom Engineer Etc..
3. To impart knowledge on the following Topics
Architecture of µP8085 & µC 8051
Adresing modes & instruction set of 8085 & 8051.
Need & use of Interrupt structure 8085 & 8051.
Simple applications development with
programming 8085 & 8051
4. Ability to acquire knowledge in Addressing modes
& instruction set of 8085 & 8051.
Ability to explain the architecture of
Microprocessor and Microcontroller.
Ability to write the assembly language programme.
5. Sl. No. Subject Description Level of
Study
1 Digital
Logic
Circuits
Data and number
system, Boolean
algebra,
Combinational and
Sequential circuits
3rd
Semester
7. 7
Microprocessor
• Microprocessor (µP) is the “brain” of a computer
that has been implemented on one
semiconductor chip.
• The word comes from the combination micro and
processor.
• Processor means a device that processes
whatever(binary numbers, 0’s and 1’s)
To process means to manipulate. It describes all
manipulation.
Micro - > extremely small
8. 8
Definition of a Microprocessor.
The microprocessor is a
programmable device that takes in numbers,
performs on them arithmetic or logical
operations according to the program stored in
memory and then produces other numbers as
a result.
9. 9
Microprocessor ?
A microprocessor is multi
programmable clock driven register
based semiconductor device that is
used to fetch , process & execute a
data within fraction of seconds.
10. 10
Applications
• Calculators
• Accounting system
• Games machine
• Instrumentation
• Traffic light Control
• Multi user, multi-function environments
• Military applications
• Communication systems
16. Intel 4004
Introduced in 1971.
It was the first microprocessor
by Intel.
It was a 4-bit µP.
Its clock speed was 740KHz.
It had 2,300 transistors.
It could execute around
60,000 instructions per
second.
16
19. Intel 8008
Introduced in 1972.
It was first 8-bit µP.
Its clock speed was
500 KHz.
Could execute
50,000 instructions
per second.
19
20. Intel 8080
Introduced in 1974.
It was also 8-bit µP.
Its clock speed was
2 MHz.
It had 6,000
transistors.
20
21. Intel 8085
Introduced in 1976.
It was also 8-bit µP.
Its clock speed was 3 MHz.
Its data bus is 8-bit and address
bus is 16-bit.
It had 6,500 transistors.
Could execute 7,69,230
instructions per second.
It could access 64 KB of memory.
It had 246 instructions.
21
23. INTEL 8086
Introduced in 1978.
It was first 16-bit µP.
Its clock speed is 4.77 MHz, 8 MHz
and 10 MHz, depending on the
version.
Its data bus is 16-bit and address
bus is 20-bit.
It had 29,000 transistors.
Could execute 2.5 million
instructions per second.
It could access 1 MB of memory.
It had 22,000 instructions.
It had Multiply and Divide
instructions.
24. INTEL 8088
Introduced in 1979.
It was also 16-bit µP.
It was created as a
cheaper version of
Intel’s 8086.
It was a 16-bit processor
with an 8-bit external
bus.
20
25. INTEL 80186 & 80188
Introduced in 1982.
They were 16-bit µPs.
Clock speed was 6 MHz.
80188 was a cheaper
version of 80186 with an
8-bit external data bus.
26. INTEL 80286
Introduced in 1982.
It was 16-bit µP.
Its clock speed was 8
MHz.
Its data bus is 16-bit
and address bus is 24-
bit.
It could address 16 MB
of memory.
It had 1,34,000
transistors.
22
28. INTEL 80386
Introduced in 1986.
It was first 32-bit µP.
Its data bus is 32-bit and
address bus is 32- bit.
It could address 4 GB of
memory.
It had 2,75,000
transistors.
Its clock speed varied
from 16 MHz to 33 MHz
depending upon the
various versions.
24
29. INTEL 80486
Introduced in 1989.
It was also 32-bit µP.
It had 1.2 million
transistors.
Its clock speed varied
from 16 MHz to 100
MHz depending upon
the various versions.
8 KB of cache memory
was introduced.
29
30. INTEL PENTIUM
Introduced in 1993.
It was also 32-bit µP.
It was originally named
80586.
Its clock speed was 66
MHz.
Its data bus is 32-bit
and address bus is 32-
bit.
30
31. INTEL PENTIUM PRO
Introduced in 1995.
It was also 32-bit µP.
It had 21 million
transistors.
Cache memory:
8 KB for instructions.
8 KB for data.
31
32. INTEL PENTIUM II
Introduced in 1997.
It was also 32-bit µP.
Its clock speed was 233
MHz to 500 MHz.
Could execute 333
million instructions per
second.
32
33. INTEL PENTIUM II XEON
Introduced in 1998.
It was also 32-bit µP.
It was designed for
servers.
Its clock speed was 400
MHz to 450 MHz.
33
34. INTEL PENTIUM III
Introduced in 1999.
It was also 32-bit µP.
Its clock speed varied
from 500 MHz to 1.4
GHz.
It had 9.5 million
transistors.
35. INTEL PENTIUM IV
Introduced in 2000.
It was also 32-bit µP.
Its clock speed was from
1.3 GHz to 3.8 GHz.
It had 42 million
transistors.
41. Basic Terms
• Bit: A digit of the binary number { 0 or 1 }
• Nibble: 4 bit Byte: 8 bit word: 16 bit
• Double word: 32 bit
• Data: binary number/code operated by an
instruction
• Address: Identification number for memory
locations
• Clock: square wave used to synchronize various
devices in µP
• Memory Capacity = 2^n ,
n->no. of address lines
41
42. BUS CONCEPT
• BUS: Group of conducting lines that carries data ,
address & control signals.
CLASSIFICATION OF BUSES:
1. DATA BUS: group of conducting lines that carries
data.
2. ADDRESS BUS: group of conducting lines that
carries address.
3. CONTROL BUS: group of conducting lines that
carries control signals {RD, WR etc}
CPU BUS: group of conducting lines that directly
connected to µP
SYSTEM BUS: group of conducting lines that carries
data , address & control signals in aµP system 42
43. TRISTATE LOGIC
3 logic levels are:
•High State (logic 1)
•Low state (logic 0)
•High Impedance state
High Impedance: output is not being driven to any defined
logic level by the output circuit.
43
44. Basic Microprocessors System
Input
Devices
s
Proce sing
Data into
Information
Output
Devices
Control
Unit
Secondary Storage Devices
Arithmetic-
Logic
Unit
Primary Storage Unit
Central Processing Unit
Keyboard,
Mouse etc
Monitor
Printer
Disks, Tapes, Optical Disks
40
48. 4
Pin 1 and Pin 2 (Input)
These are also
called Crystal Input
Pins.
8085 can generate
clock signals
internally.
To generate clock
signals internally,
8085 requires
external inputs from
X1& X2 pins
49. RESET IN and RESET OUT
4
Pin 36 (Input) and Pin 3
(Output)
RESET IN:
◦ It is used to reset the
microprocessor.
◦ It is active low signal.
◦ When the signal on this pin is low
for at least 3 clocking cycles, it
forces the microprocessor to reset
itself.
50. RESET IN and RESET OUT
4
Pin 36 (Input) and Pin 3
(Output)
Resetting the
microprocessor means:
◦ Clearing the PC and IR.
◦ Disabling all interrupts (except
TRAP).
◦ Disabling the SOD pin.
◦ All the buses (data, address,
control) are tri- stated.
◦ Gives HIGH output to RESET OUT
pin.
51. RESET IN and RESET OUT
4
Pin 36 (Input) and Pin 3
(Output)
RESET OUT:
◦ It is used to reset the peripheral devices and
other ICs on the circuit.
◦ It is an output signal.
◦ It is an active high signal.
◦ The output on this pin goes high whenever
RESET IN is given low signal.
◦ The output remains high as long as RESET IN
is kept low.
52. SID and SOD
Pin 4 (Input) and Pin 5
(Output)
SID (Serial Input Data):
o It takes 1 bit input from serial port
of 8085.
o Stores the bit at the 8th position
(MSB) of the Accumulator.
o RIM (Read Interrupt Mask)
instruction is used to transfer the
bit.
52
53. SID and SOD
Pin 4 (Input) and Pin 5
(Output)
SOD (Serial Output Data):
o It takes 1 bit from Accumulator to
serial port of 8085.
o Takes the bit from the 8th position
(MSB) of the Accumulator.
o SIM (Set Interrupt Mask) instruction is
used to transfer the bit.
53
54. Interrupt Pins
54
Interrupt:
• It means interrupting the normal execution of the
microprocessor.
• When microprocessor receives interrupt signal, it
discontinues whatever it was executing.
• It starts executing new program indicated by the interrupt
signal.
• Interrupt signals are generated by external peripheral
devices.
• After execution of the new program, microprocessor goes
back to the previous program.
55. Sequence of Steps Whenever There
is an Interrupt
55
Microprocessor completes execution of
current instruction of the program.
PC contents are stored in stack.
PC is loaded with address of the new
program.
After executing the new program, the
microprocessor returns back to the previous
program.
It goes to the previous program by reading the
top value of stack.
60. Non-Maskable Interrupts
60
The interrupts which are always in
enabled mode are called non-
maskable interrupts.
These interrupts can never be
disabled by any software
instruction.
TRAP is a non-maskable interrupt.
61. Vectored Interrupts
61
The interrupts which have fixed
memory location for transfer of
control from normal execution.
Each vectored interrupt points to the
particular location in memory.
63. Vectored Interrupts
63
The addresses to which program
control goes:
Absolute address is calculated by
multiplying the RST value with
0008 H.
Name Vectored Address
RST 7.5 003C H (7.5 x 0008 H)
RST 6.5 0034 H (6.5 x 0008 H)
RST 5.5 002C H (5.5 x 0008 H)
TRAP 0024 H (4.5 x 0008 H)
64. Non-Vectored Interrupts
64
The interrupts which don't have
fixed memory location for transfer
of control from normal execution.
The address of the memory location
is sent along with the interrupt.
INTR is a non-vectored interrupt.
65. Edge TriggeredInterrupts
65
The interrupts which are triggered
at leading or trailing edge are
called edge triggered interrupts.
RST 7.5 is an edge triggered
interrupt.
It is triggered during the leading
(positive) edge.
66. Level TriggeredInterrupts
66
The interrupts which are triggered at
high or low level are called level
triggered interrupts.
RST 6.5
RST 5.5
INTR
TRAP is edge and level triggered
interrupt.
67. Priority Based Interrupts
67
Whenever there exists a
simultaneous request at two or more
pins then the pin with higher priority
is selected by the microprocessor.
Priority is considered only when there
are simultaneous requests.
69. TRAP
Pin 6 (Input)
It is an non-maskable interrupt.
It has the highest priority.
It cannot be disabled.
It is both edge and level triggered.
It means TRAP signal must go from
low to high.
And must remain high for a certain
period of time.
TRAP is usually used for power
failure and emergency shutoff.
69
70. RST 7.5
Pin 7 (Input)
It is a maskable interrupt.
It has the second highest
priority.
It is positive edge
triggered only.
The internal flip-flop is
triggered by the rising
edge.
The flip-flop remains high
until it is cleared by RESET
IN.
70
71. RST 6.5
Pin 8 (Input)
It is a maskable
interrupt.
It has the third highest
priority.
It is level triggered only.
The pin has to be held
high for a specific period
of time.
RST 6.5 can be
enabled by EI
instruction.
It can be disabled by DI
instruction. 71
72. RST 5.5
Pin 9
(Input)
It is a maskable
interrupt.
It has the fourth
highest priority.
It is also level
triggered.
The pin has to be held
high for a specific
period of time.
This interrupt is very
similar to RST 6.5.
72
73. INTR
Pin 10 (Input)
It is a maskable
interrupt.
It has the lowest
priority.
It is also level triggered.
It is a general purpose
interrupt.
By general purpose we
mean that it can be used
to vector
microprocessor to any
specific subroutine 73
74. INTA
Pin 11 (Output)
It stands for interrupt
acknowledge.
It is an out going signal.
It is an active low signal.
Low output on this pin
indicates that
microprocessor has
acknowledged the INTR
request.
74
75. Address and Data
Pins
75
Address Bus:
• The address bus is used to send
address to memory.
• It selects one of the many locations in
memory.
• Its size is 16-bit.
76. Address and Data
Pins
76
Data Bus:
• It is used to transfer data
between microprocessor and
memory.
• Data bus is of 8-bit.
77. AD0 –AD7
Pin 19-12 (Bidirectional)
These pins serve the dual purpose of
transmitting lower order address and data
byte.
During 1st clock cycle, these pins act as
lower half of address.
In remaining clock cycles, these pins act as
data bus.
The separation of lower order address and
data is done by address latch.
77
78. A8 –A15
Pin 21-28 (Unidirectional)
These pins carry the higher
order of address bus.
The address is sent from
microprocessor to memory.
These 8 pins are switched to
high impedance state during
HOLD and RESET mode.
78
80. ALE
Pin 30 (Output)
It is used to enable Address
Latch.
It indicates whether bus
functions as address bus or
data bus.
If ALE = 1 then
◦ Bus functions as address bus.
If ALE = 0 then
◦ Bus functions as data bus.
80
81. S0 and S1
Pin 29 (Output) and Pin 33
(Output)
S0 and S1 are called Status Pins.
They tell the current operation
which is in progress in 8085.
S0 S1 Operation
0 0 Halt
0 1 Write
1 0 Read
1 1 Opcode Fetch
81
82. IO/M
7
Pin 34 (Output)
This pin tells whether
I/O or memory
operation is being
performed.
If IO/M = 1 then
◦ I/O operation is being performed.
If IO/M = 0 then
◦ Memory operation is being performed.
83. IO/M
Pin 34 (Output)
The operation being performed is
indicated by S0 and S1.
If S0 = 0 and S1 = 1 then
◦ It indicates WRITE operation.
If IO/M = 0 then
◦ It indicates Memory operation.
Combining these two we get Memory
Write
Operation.
83
85. RD
Pin 32 (Output)
RD stands for Read.
It is an active low signal.
It is a control signal used for
Read operation either from
memory or from Input device.
A low signal indicates that
data on the data bus must be
placed either from selected
memory location or from input
device.
85
86. WR
Pin 31 (Output)
WR stands for Write.
It is also active low signal.
It is a control signal used for
Write operation either into
memory or into output device.
A low signal indicates that data
on the data bus must be written
into selected memory location
or into output device.
86
87. READY
Pin 35 (Input)
This pin is used to
synchronize slower
peripheral devices with fast
microprocessor.
A low value causes the
microprocessor to enter into
wait state.
The microprocessor
remains in wait state until
the input at this pin goes
high.
87
88. HOLD
Pin 38 (Input)
HOLD pin is used to request the
microprocessor for DMA transfer.
A high signal on this pin is a
request to microprocessor to
relinquish the hold on buses.
This request is sent by DMA
controller.
Intel 8257 and Intel 8237 are two
DMA controllers.
88
89. HLDA
Pin 39 (Output)
HLDA stands for Hold
Acknowledge.
The microprocessor uses this pin
to acknowledge the receipt of
HOLD signal.
When HLDA signal goes high,
address bus, data bus, RD, WR,
IO/M pins are tri- stated.
This means they are cut-off from
external environment.
89
90. HLDA
Pin 39 (Output)
The control of these buses goes to
DMA Controller.
Control remains at DMA Controller
until HOLD is held high.
When HOLD goes low, HLDA also
goes low and the microprocessor
takes control of the buses.
90
91. VSS and VCC
Pin 20 (Input) and Pin 40
(Input)
+5V power supply is
connected to VCC.
Ground signal is
connected to VSS.
91
92. THE 8085 AND ITS BUSSES
The 8085 is an 8-bit general purpose
microprocessor that can address 64K Byte of
memory.
It has 40 pins and uses +5V for power. It can
run at a maximum frequency of 3 MHz.
-The pins on the chip can be grouped into 6
groups:
Address Bus.
Data Bus.
Control and Status Signals.
Power supply and frequency.
Externally Initiated Signals.
Serial I/O ports. 88
93. The Address and Data Busses
The address bus has 8 signal lines A8 – A15 which are
unidirectional.
The other 8 address bits are multiplexed (time shared)
with the 8 data bits.
So, the bits AD0 – AD7 are bi-directional and serve
as A0 – A7 and D0 – D7 at the same time.
During the execution of the instruction, these
lines carry the address bits during the early part,
then during the late parts of the execution, they
carry the 8 data bits.
In order to separate the address from the data, we
can use a latch to save the value before the function
of the bits changes. 89
95. Flag Register
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
95
The flags are affected by the arithmetic and logical
instruction
96. Accumulator
It is an 8 bit register
For any arithmetic and logical instruction one of the
data should be in this register
It is used for storing the result of any arithmetic and
logical manipulations.
It is also called as A register
All the data which are sent to I/O devices are sent via
A register.
96
97. Temporary register
It is used to hold the data during the
operation of arithmetic and logical
operation
97
98. Sign Flag
If the D7 bit of the accumulator is set then
this flag is set i.e 1 meaning that the result
is in negative.
Ex. 7-8 = -1
98
99. 100
Carry flag
During the arithmetic operation if a carry occurs then
this flag is set.
Ex. F1+1F= 1 10
Carry
99
1111 0001
1111 0001
11110 0010
100. Zero flag
During the arithmetic/ logical
operation if the result is zero then
this flag is set.
Ex. FF-FF = 00
100
1 1 1 1 1 1 1 1
1 1 1 1 1 1 11
1 0 0 0 0 0 0 0 0
101. Parity flag
After the of the arithmetic and logical
operation if the result is even then this flag
is set.
Ex. 0A-+0A = 14
101
0000 1010
0000 1010
0001 0100
102. Auxiliary carry flag
During BCD arithmetic operation when a carry is
generated by D3 bit and passed on to D4 bit then
this flag is set.
Ex. 1F+11 = 0001 1111 +0001 0001
= 0010 0000
102
108. Program Counter
It is a 16 bit register
It is used to point out the address
of the next instruction which is to
be executed
108
109. Stack pointer
It is a 16 bit register
It points the starting address of the stack
.
109
110. Register Array
B, C, D, E, H and L are general purpose
register
All are 8 bit register
If the are combined as BC, DE and HL
they can store 16 bit data
110
112. 8085 Communication with Memory
112
Involves the following three steps
1. Identify the memory location (with address)
2. Generate Timing & Control signals
3. Data transfer takes place
120. Memory-mapped I/O
120
8085 uses its 16-bit address bus to identify a
memory location
Memory address space: 0000H to FFFFH
8085 needs to identify I/O devices also
I/O devices can be interfaced using
addresses from memory space
8085 treats such an I/O device as a memory
location
This is called Memory-mapped I/O
121. Peripheral-mapped I/O
121
8085 has a separate 8-bit addressing scheme
for I/O devices
I/O address space: 00H to FFH
This is called Peripheral-mapped I/O or I/O-
mapped I/O
122. 8085 Communication with I/O devices
122
Involves the following three steps
1. Identify the I/O device (with address)
2. Generate Timing & Control signals
3. Data transfer takes place
8085 communicates with a I/O device only if
there is a Program Instruction to do so
124. 2.Generate Timing & Control Signals
Memory-mapped I/O
Reading Input: IO/M = 0, RD = 0
Write to Output: IO/M = 0, WR = 0
Peripheral-mapped I/O
Reading Input: IO/M = 1, RD = 0
Write to Output: IO/M = 1, WR = 0
3. Data transfer takes place
124
125. 8085 Communication with I/O devices
125
Involves the following three steps
Identify the I/O device (with address)
Generate Timing & Control signals
Data transfer takes place
8085 communicates with a I/O device only if
there is a Program Instruction to do so
126. Peripheral I/O Instructions
126
IN Instruction
Inputs data from input device into the
accumulator
It is a 2-byte instruction
Format: IN 8-bit port address
Example: IN 01H
127. OUT Instruction
Outputs the contents of accumulator to an
output device
It is a 2-byte instruction
Format: OUT 8-bit port address
Example: OUT 02H
127
128. ----------Example Program----------
128
WAP to read a number from input port (port
address 01H) and display it on ASCII display
connected to output port (port address 02H)
IN 01H ;reads data value 03H (example)into
;accumulator, A = 03H
MVI B, 30H;loads register B with 30H
ADD B
OUT 02H
;A = 33H, ASCII code for 3
;display 3 on ASCII display
129. Memory-mapped I/O Instructions
129
I/O devices are identified by 16-bit addresses
8085 communicates with an I/O device as if it
were one of the memory locations
Memory related instructions are used
For e.g. LDA, STA
LDA 8000H
Loads A with data read from input device with
16-bit address 8000H
STA 8001H
Stores (Outputs) contents of A to output
device with 16-bit address 8001H
130. ----------Example Program----------
130
WAP to read a number from input port (port
address 8000H) and display it on ASCII
display connected to output port (port
address 8001H)
LDA 8000H;reads data value 03H (example)into
;accumulator, A = 03H
MVI B, 30H;loads register B with 30H
ADD B ;A = 33H, ASCII code for 3
STA 8001H;display 3 on ASCII display
132. 132
Timing Diagram is a graphical representation. It
represents the execution time taken by each
instruction in a graphical format. The execution
time is represented in T-states.
Instruction Cycle:
The time required to execute an instruction .
Machine Cycle:
The time required to access the memory or
input/output devices .
T-State:
•The machine cycle and instruction cycle takes
multiple clock periods.
•A portion of an operation carried out in one
system clock period is called as T-state.
137. 137
OPCODE FETCH
• The Opcode fetch cycle, fetches the instructions from memory
and delivers it to the instruction register of the microprocessor
• Opcode fetch machine cycle consists of 4 T-states.
T1 State:
During the T1 state, the contents of the program counter are
placed on the 16 bit address bus. The higher order 8 bits are
transferred to address bus (A8-A15) and lower order 8 bits are
transferred to multiplexed A/D (AD0-AD7) bus.
ALE (address latch enable) signal goes high. As soon as
ALE goes high, the memory latches the AD0-AD7 bus. At
the middle of the T state the ALE goes low
138. 138
T2 State:
During the beginning of this state, the RD’ signal goes low
to enable memory. It is during this state, the selected memory
location is placed on D0-D7 of the Address/Data multiplexed
bus.
T3 State:
In the previous state the Opcode is placed in D0-D7 of the A/D
bus. In this state of the cycle, the Opcode of the A/D bus is
transferred to the instruction register of the microprocessor.
Now the RD’ goes high after this action and thus disables the
memory from A/D bus.
T4 State:
In this state the Opcode which was fetched from the memory
is decoded.
140. was obtained from the memory is then decoded.
• These machine cycles have 3 T-states.
T1 state:
• The higher order address bus (A8-A15) and lower order address
and data multiplexed (AD0-AD7) bus. ALE goes high so that the
memory latches the (AD0-AD7) so that complete 16-bit address
are available.
The mp identifies the memory read machine cycle from the status
signals IO/M’=0, S1=1, S0=0. This condition indicates the
memory read cycle.
T2 state:
• Selected memory location is placed on the (D0-D7) of the A/D
multiplexed bus. RD’ goes LOW
T3 State:
• The data which was loaded on the previous state is transferred
to the microprocessor. In the middle of the T3 state RD’ goes
high and disables the memory read operation. The data which
136
142. 142
• These machine cycles have 3 T-states.
T1 state:
• The higher order address bus (A8-A15) and lower order address
and data multiplexed (AD0-AD7) bus. ALE goes high so that the
memory latches the (AD0-AD7) so that complete 16-bit address
are available.
The mp identifies the memory read machine cycle from the status
signals IO/M’=0, S1=0, S0=1. This condition indicates the
memory read cycle.
T2 state:
• Selected memory location is placed on the (D0-D7) of the A/D
multiplexed bus. WR’ goes LOW
T3 State:
• In the middle of the T3 state WR’ goes high and disables the
memory write operation. The data which was obtained from
the memory is then decoded.
148. 148
Timing diagram for IN C0H
• Fetching the Opcode DBH from the memory
4125H.
• Read the port address C0H from 4126H.
• Read the content of port C0H and send it to
the accumulator.
• Let the content of port is 5EH.
149. 145
It require 3 m/c cycles
10 T states
opcode fetch(4T)
memory read(3T) I/O
read(3T)
153. Timing diagram for MVI B, 43h
• Fetching the Opcode 06H from the memory
2000H. (OF machine cycle)
• Read (move) the data 43H from memory
2001H. (memory read)
153
160. Types of Interrupts
• Interrupts of 8085 can be classified as
– Maskable (RST 7.5, RST 6.5, RST 5.5, INTR)
– Non-maskable (TRAP)
• An interrupt is a request for attention/service
• 8085 may choose to service/not-service a
maskable interrupt
• 8085 cannot ignore a service request from a
non-maskable interrupt
160
161. Interrupt process
• 8085 is executing its main program
• an interrupt is generated by an external
device
• 8085 pauses execution of main program
• 8085 calls the Interrupt service routine
• 8085 executes the Interrupt service routine
• 8085 returns to execution of main program
(from where it was paused)
161
162. Example: Blinking LED Display with
Interrupt-based Display-Pattern change
Input
Switches
LED
Display
RST 7.5
8085
(Display-Pattern)
Interrupt Switch
162
Peripheral-mapped I/O
Interrupt I/O
163. Interrupt Service Routine (ISR)
• It is a subroutine
• 8085 calls an ISR in response to an
interrupt request by an external device
• ISRs must be located in memory at pre-
determined addresses known as Interrupt
Vectors
163
164. Interrupt Vector Table of 8085
164
Interrupt Interrupt Vector
TRAP 0024H
RST 7.5 003CH
RST 6.5 0034H
RST 5.5 002CH
Please Note: INTR is a non-vectored interrupt
165. Using Vectored Interrupts of 8085
• By default, all the vectored interrupts (except
TRAP) of 8085 are disabled
• 8085 vectored interrupts are enabled with
two instructions: EI and SIM
• EI (Enable Interrupt): 1-byte instruction that
sets the Interrupt Enable flip-flop
– It is internal to the processor & can be set or reset
by using software instructions
165
166. Using Vectored Interrupts
Step-1
•Set Interrupt Enable flip-flop by using EI
instruction to enable the interrupt process
Step-2
•Use SIM (Set Interrupt Mask) instruction to
set mask for RST 7.5, 6.5 and 5.5 interrupts
166
167. SIM Instruction
• It is a 1-byte instruction
• Reads Accumulator contents
• Enables/Disables interrupts accordingly
• Used for three different functions
– Set mask for RST 7.5, 6.5, 5.5 interrupts
– Additional control for RST 7.5
– Implement serial I/O
167
168. Accumulator bit pattern for SIM
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE XXX R7.5 MSE M7.5 M6.5 M5.5
0 = Available, 1 = Masked
Mask Set Enable, 0 = bits 0-2
ignored
1 = mask is set
IF 1, RESET RST 7.5
If 1, bit 7 is output to serial output
data latch
Serial Output Data, ignored if bit 6 = 0
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
164
169. 8085 Interrupt process for
Vectored-Interrupts
1. Enables Interrupt process by writing the EI
instruction in the main program
2. Set interrupt mask using SIM instruction
3. 8085 monitors the status of all interrupt
lines during the execution of each
instruction
169
170. 4. When 8085 detects an interrupt signal from
an external device
• It completes execution of current
instruction
• Disables the Interrupt Enable flip-flop
5. Executes a CALL to Interrupt Vector
location for that interrupt
• Before the CALL is made, 8085 stores
return address in main program on stack
170
8085 Interrupt process for
Vectored-Interrupts (Cont.)
171. 6. 8085 executes the ISR written at the
specified interrupt vector location
• ISR should include the EI instruction to
Enable Interrupt again
• At the end of ISR, RET instruction
transfers the program control back to the
main program
171
Presented by C.GOKUL,AP/EEE Velalar College of Engg & Tech , Erode
8085 Interrupt process for
Vectored-Interrupts (Cont.)
172. Differentiate between the following instructions clearly
(i)Push and POP
(ii)CALL and Jump
(iii)ADD and ADC
(iv)INC and INX
(v)MOVB,B and MOVB,A
(vi)What is the general format of an 8085 instruction set?
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