- Saikishore Reddy Thiyyagura is a computer engineer with over 2.5 years of experience in digital design, ASIC design verification, and hardware design verification. - He has expertise in programming languages like C, C++, Perl, VHDL, Verilog, and SystemVerilog and has experience using simulators like QuestaSim. - His experience includes developing test benches, executing and debugging tests, developing RTL designs, and verifying functionality using UVM methodologies.

1. Saikishore reddy Thiyyagura
thiyyagura.saikishore@gmail.com | (203) 997-5012 | www.linkedin.com/in/saikishorethiyyagura
SUMMARY:
• Computer Engineer with expertise in Hardware DesignVerification.
• Around 2.5 years of experience in Digital Design, ASIC Design Verification, Hardware Design andVerification.
• Experience working with Verification/Validation team to debug test cases, functional verification of components,
designing of IP blocks using verificationmethodologies.
• Expert in Programming languages like C, C++, Perl, VHDL, Verilog, System Verilog.
• Hands on using Simulators like Questa Sim.
• Familiar with System Verilog Assertions (SVA), Functional and Code Coverageconcepts.
• Skilled in Test bench development, Execution and debugging, Developing RTLdesign.
• Developed Monitor, BFM, Scoreboard and Generator, interfaces for different protocols and verified the functionality
using System Verilog and UVM methodologies.
• Good Knowledge on logic implementation, Computer architecture, UVMmethodologies.
• Experience in generating scripts and responsible for automation of the processdevelopment.
• Good knowledge on AMBA (AHB, APB, AXI) protocols, Peripheral protocols PCI Express, Memory Controller, memory
architecture.
SKILLS:
Languages : C, C++, Object oriented Programming concepts
HDL/HVL : VHDL, Verilog, System Verilog
Scripting : Perl
Protocols : AMBA (APB, AXI, AHB)
Methodologies: UVM
Simulators : Modelsim /QuestaSim, cadence Pspice, virtuoso.
OS : UNIX/Linux, Windows
WORK EXPERIENCE:
Graduate Research Assistant at University of Bridgeport, CT, USA June’2016 – Dec’17
• Type -2 logic shut down techniques with custom layout to lower the power consumption.
• Adiabatic logic circuits to lower power consumptions.
• Developed monitoring techniques to measure glucose levels in saliva.
.
SOC verification Engineer at SOCDV Tech Pvt Ltd, Banglore, IN Aug’2014- July’2015
• APB, AHB, I2C protocol were analyzed and verification plan, test cases were developed for theprotocols.
• Verification IP (VIP) Development of AXI protocol was done using System Verilog.
• Verified the functionality of Ethernet Loopback design usingSystem Verilog.
• Monitor, BFM, scoreboard, generator, checker, interface components was developed for differentprotocols.
• Followed the top-down approach and created test plans for the Design under test(DUT) for differentprotocols.
• Developed test bench architecture and components for AMBA protocols.
• Running test cases to achieve 100% Functional Coverage.
Environment: QuestaSim, GVim Editor.
Status: F1 student with opt.

2. PROJECTS:
1. AXI VIP Development using System Verilog
a. Description:
i. VIP component development for AXI3.0 protocol with support for various features like
burst type, burst size, protection, out of order, overlapping, aligned, etc. As part of this
project developed BFM, Generator, Monitor, and Coverage models. Also developed
scenarios targeting validating above features.
b. Tools used: Questasim
c. Duration: 4 months
d. Responsibilities:
i. Developing VIP architecture
ii. Coding VIP components
iii. Validating AXI VIP using AXI slave model.
2. Memory Controller Functional Verification using System Verilog
a. Description:
i. Design supports SDRAM, SSRAM, Flash & Synchronous Chip select devices. It has
support for 8 chip selects. It also supports flexible timing configuration for different
memory types. As part of this design verification, we created test bench using SV to
generate scenarios targeting all types of supported memories for different possible
combinations & different sizes supported. We also developed monitor, reference model &
checker as part self-checking test bench implementation.
b. Tools used: Questasim
c. Duration: 6 months
d. Responsibilities:
i. Listing down features, scenarios
ii. Test plan development
iii. Developing test bench architecture
iv. Coding test bench components including reference model and checkers
v. Verification closure using Functional coverage & code coverage as closing criteria.
3. AHB UVC Development
a. Description:
i. AHB UVC component development for AXI2.0 protocol. As part of this project, we have
developed Driver, Sequencer, Monitor, Coverage models. We have also developed basic
sequences targeting all features of AHB protocol.
b. Tools used: Questasim
c. Duration: 4 months
d. Responsibilities:
i. Listing down features, scenarios
ii. Test plan development
iii. Developing test bench architecture
iv. Coding test bench components including reference model and checkers
v. Verification closure using Functional coverage & code coverage as closing criteria.
Education:
Master of Science in Electrical Engineering, University of Bridgeport GPA: 3.8/4
Bachelors in Electronics and Communication Engineering, JNTU kakinada GPA: 3.7/4