This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired.
This paper presents a high voltage conversion at high sensitivity RF energy harvesting system for IoT applications. The harvesting system comprises bulk-to-source (BTMOS) differential-drive based rectifier to produce a high efficiency RF energy harvesting system. Low-pass upward impedance matching network is applied at the rectifier input to increase the sensitivity and output voltage. Dual-oxide-thickness transistors are used in the rectifier circuit to maintain the power efficiency at each stage of the rectifier. The system is designed using 0.18µm Silterra RF in deep n-well process technology and achieves 4.07V output at -16dBm sensitivity without the need of complex auxiliary control circuit and DC-DC charge-pump circuit. The system is targeted for urban environment.
A Novel Configuration of A Microstrip Power Amplifier based on GaAs-FET for I...IJECEIAES
Power Amplifiers (PA) are very indispensable components in the design of numerous types of communication transmitters employed in microwave technology. The methodology is exemplified through the design of a 2.45GHz microwave power Amplifier (PA) for the industrial, scientific and medical (ISM) applications using microstrip technology. The main design target is to get a maximum power gain while simultaneously achieving a maximum output power through presenting the optimum impedance which is characteristically carried out per adding a matching circuit between the source and the input of the power amplifier and between the load and the output of the power amplifier. A "T" matching technique is used at the input and the output sides of transistor for assure in band desired that this circuit without reflections and to obtain a maximum power gain. The proposed power amplifier for microwave ISM applications is designed, simulated and optimized by employing Advanced Design System (ADS) software by Agilent. The PA shows good performances in terms of return loss, output power, power gain and stability; the circuit has an input return loss of -38dB and an output return loss of -33.5dB. The 1-dB compression point is 8.69dBm and power gain of the PA is 19.4dBm. The Rollet's Stability measure B1 and the stability factor K of the amplifier is greater than 0 and 1 respectively, which shows that the circuit is unconditionally stable. The total chip size of the PA is 73.5× 36 mm 2 .
Negative resistance amplifier circuit using GaAsFET modelled single MESFETTELKOMNIKA JOURNAL
Negative resistance devices have attracted much attention in the wireless communication industry because of their low cost, better performance, high speed, and reduced power requirements. Although negative resistance circuits are non-linear circuits, they are associated with distortion, which may either be amplitude-to-amplitude distortion or amplitude-to-phase distortion. In this paper, a unique way of realizing a negative resistance amplifier is proposed using a single metal-semiconductor field-effect transistor (MESFET). Intermodulation distortion test (IMD) is performed to evaluate the characteristic response of the negative resistance circuit amplifier to different bias voltages using the harmonic balance (HB) of the advanced designed software (ADS 2016). The results obtained are compared to those of a conventional distributed amplifier. The findings of this study showed that the negative resistance amplifier spreads over a wider frequency output with reduced power requirements while the conventional distributed amplifier has a direct current (DC) offset with output voltage of 32.34 dBm.
This paper presents a high voltage conversion at high sensitivity RF energy harvesting system for IoT applications. The harvesting system comprises bulk-to-source (BTMOS) differential-drive based rectifier to produce a high efficiency RF energy harvesting system. Low-pass upward impedance matching network is applied at the rectifier input to increase the sensitivity and output voltage. Dual-oxide-thickness transistors are used in the rectifier circuit to maintain the power efficiency at each stage of the rectifier. The system is designed using 0.18µm Silterra RF in deep n-well process technology and achieves 4.07V output at -16dBm sensitivity without the need of complex auxiliary control circuit and DC-DC charge-pump circuit. The system is targeted for urban environment.
A Novel Configuration of A Microstrip Power Amplifier based on GaAs-FET for I...IJECEIAES
Power Amplifiers (PA) are very indispensable components in the design of numerous types of communication transmitters employed in microwave technology. The methodology is exemplified through the design of a 2.45GHz microwave power Amplifier (PA) for the industrial, scientific and medical (ISM) applications using microstrip technology. The main design target is to get a maximum power gain while simultaneously achieving a maximum output power through presenting the optimum impedance which is characteristically carried out per adding a matching circuit between the source and the input of the power amplifier and between the load and the output of the power amplifier. A "T" matching technique is used at the input and the output sides of transistor for assure in band desired that this circuit without reflections and to obtain a maximum power gain. The proposed power amplifier for microwave ISM applications is designed, simulated and optimized by employing Advanced Design System (ADS) software by Agilent. The PA shows good performances in terms of return loss, output power, power gain and stability; the circuit has an input return loss of -38dB and an output return loss of -33.5dB. The 1-dB compression point is 8.69dBm and power gain of the PA is 19.4dBm. The Rollet's Stability measure B1 and the stability factor K of the amplifier is greater than 0 and 1 respectively, which shows that the circuit is unconditionally stable. The total chip size of the PA is 73.5× 36 mm 2 .
Negative resistance amplifier circuit using GaAsFET modelled single MESFETTELKOMNIKA JOURNAL
Negative resistance devices have attracted much attention in the wireless communication industry because of their low cost, better performance, high speed, and reduced power requirements. Although negative resistance circuits are non-linear circuits, they are associated with distortion, which may either be amplitude-to-amplitude distortion or amplitude-to-phase distortion. In this paper, a unique way of realizing a negative resistance amplifier is proposed using a single metal-semiconductor field-effect transistor (MESFET). Intermodulation distortion test (IMD) is performed to evaluate the characteristic response of the negative resistance circuit amplifier to different bias voltages using the harmonic balance (HB) of the advanced designed software (ADS 2016). The results obtained are compared to those of a conventional distributed amplifier. The findings of this study showed that the negative resistance amplifier spreads over a wider frequency output with reduced power requirements while the conventional distributed amplifier has a direct current (DC) offset with output voltage of 32.34 dBm.
Design of Wide-band Power Amplifier Based on Power Combiner Technique with Lo...IJECEIAES
RF power amplifiers are one of challenging blocks in designing radio frequency transceivers, this is due to non-linearity behavior of power amplifiers that leads to inter-modulation distortion. This paper presents the design of wide-band power amplifier which combined with parallel coupled line band pass filter at the input and output of power amplifier to allow the only required frequency band to pass through the power amplifier. Class-A topology and ATF-511P8 transistor are used in this design. Advanced Design System software used as a simulation tool to simulate the designed wideband power amplifier. The simulation results showed an input return loss (S11) which less than -10dB, and gain (S21) is higher than 10 dB over the entire frequency band and considers as flat as well. The designed amplifier is stable over the bandwidth (K>1). Inter-modulation distortion is -56.919dBc which is less than -50dBc with 10dBm input power. The designed amplifier can be used for the microwave applications which include weather radar, satellite communication, wireless networking, mobile, and TV.
Passive Intermodulation (PIM) distortion is a growing concern for telecommunication network operators. They have to cope with limited bandwidths and at the same time, with highest data demand of their subscribers. Learn more about PIM, its causes and measuring.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
Design and Fabrication of S-Band MIC Power Amplifierijcisjournal
In this paper, we demonstrate an approach to design FET (pHEMT) based amplifier. The FET is from
Berex Inc.The design is carried out using the measured S-parameter data of the FET.ADS is used as design
tool for the design. A single-stage power amplifier demonstrated 13dB output gain from 3GHz-4GHz .The
saturated output power of 1W and the power added efficiency (PAE) up to 43%.The amplifier is fabricated
on a selective device GaAs power pHEMT process in MIC (Microwave Integrated Circuit) Technology.
MICs are realized using one or more different forms of transmission lines, all characterized by their ability
to be printed on a dielectric substrate.Active and passive components such as transistors/FET, thin or thick
film chip capacitors and resistors are attached
This paper presents the design and development of an integrated wireless power transfer and data communication system. The power and data transfer share a common inductive link that consists of two identical Helical coils placed on both sides of a carbon composite barrier. Power and data are transferred simultaneously through a 5-mm thick carbon composite barrier without any physical penetration or contact. Power transfer measurements show that the system can deliver 9.7 AC power to the receiving coil with a power transfer efficiency of 36% through the carbon composite barrier. The system achieves a bidirectional half-duplex data communication with the data rate of unit 1.2kbit/s.
Integrated cmos rectifier for rf-powered wireless sensor network nodesjournalBEEI
This article presents a review of the CMOS rectifier for radio frequency energy harvesting application. The on-chip rectifier converts the ambient low-power radio frequency signal coming to antenna to useable DC voltage that recharges energy to wireless sensor network (WSN) nodes and radiofrequency identification (RFID) tags, therefore the rectifier is the most important part of the radio frequency energy harvesting system. The impedance matching network maximizes power transfer from antenna to rectifier. The design and comparison between the simulation results of one- and multi-stage differential drive cross connected rectifier (DDCCR) at the operating frequencies of 2.44GHz, and 28GHz show the output voltage of the multi-stage rectifier doubles at each added stage and power conversion efficiency (PCE) of rectifier at 2.44GHz was higher than 28GHz. The (DDCCR) rectifier is the most efficient rectifier topology to date and is used widely for passive WSN nodes and RFID tags.
Design consideration in low dropout voltage regulator for batteryless power m...journalBEEI
Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism
reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of
IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions
to decrease power consumption while maintaining the quick transient response to signal variations. LDO
voltage regulators, as power management devices should adjust to modern technological and industrial
trends. To increase the current capability with a minimum standby quiescent current under small-signal
operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the
dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout.
As a result, the efficiency gets increased.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions to decrease power consumption while maintaining the quick transient response to signal variations. LDO voltage regulators, as power management devices should adjust to modern technological and industrial trends. To increase the current capability with a minimum standby quiescent current under small-signal operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout. As a result, the efficiency gets increased.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
2.4GHZ CLASS AB POWER AMPLIFIER FOR HEALTHCARE APPLICATIONijbesjournal
The objective of this research was to design a 2.4 GHz class AB Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. This paper introduces the design of a 2.4GHz class AB power amplifier which consists of two stage amplifiers. This power amplifier can transmit 10dBm output power to a 50Ω load. The power added efficiency is 7.5% at 1dB compression point and the power gain is 10dB, the total power consumption is 0.135W. The performance of the power amplifier meets the specification requirements of the desired.
Class D Power Amplifier for Medical Applicationieijjournal
The objective of this research was to design a 2.4 GHz class AB Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. This paper introduces the design of a 2.4GHz class D power amplifier which consists of two stage amplifiers. This power amplifier can transmit 15dBm output power to a 50Ω load. The power added efficiency was 50% and the total power consumption was 90.4 mW. The performance of the power amplifier meets the specification requirements of the desired.
Design of Wide-band Power Amplifier Based on Power Combiner Technique with Lo...IJECEIAES
RF power amplifiers are one of challenging blocks in designing radio frequency transceivers, this is due to non-linearity behavior of power amplifiers that leads to inter-modulation distortion. This paper presents the design of wide-band power amplifier which combined with parallel coupled line band pass filter at the input and output of power amplifier to allow the only required frequency band to pass through the power amplifier. Class-A topology and ATF-511P8 transistor are used in this design. Advanced Design System software used as a simulation tool to simulate the designed wideband power amplifier. The simulation results showed an input return loss (S11) which less than -10dB, and gain (S21) is higher than 10 dB over the entire frequency band and considers as flat as well. The designed amplifier is stable over the bandwidth (K>1). Inter-modulation distortion is -56.919dBc which is less than -50dBc with 10dBm input power. The designed amplifier can be used for the microwave applications which include weather radar, satellite communication, wireless networking, mobile, and TV.
Passive Intermodulation (PIM) distortion is a growing concern for telecommunication network operators. They have to cope with limited bandwidths and at the same time, with highest data demand of their subscribers. Learn more about PIM, its causes and measuring.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
Design and Fabrication of S-Band MIC Power Amplifierijcisjournal
In this paper, we demonstrate an approach to design FET (pHEMT) based amplifier. The FET is from
Berex Inc.The design is carried out using the measured S-parameter data of the FET.ADS is used as design
tool for the design. A single-stage power amplifier demonstrated 13dB output gain from 3GHz-4GHz .The
saturated output power of 1W and the power added efficiency (PAE) up to 43%.The amplifier is fabricated
on a selective device GaAs power pHEMT process in MIC (Microwave Integrated Circuit) Technology.
MICs are realized using one or more different forms of transmission lines, all characterized by their ability
to be printed on a dielectric substrate.Active and passive components such as transistors/FET, thin or thick
film chip capacitors and resistors are attached
This paper presents the design and development of an integrated wireless power transfer and data communication system. The power and data transfer share a common inductive link that consists of two identical Helical coils placed on both sides of a carbon composite barrier. Power and data are transferred simultaneously through a 5-mm thick carbon composite barrier without any physical penetration or contact. Power transfer measurements show that the system can deliver 9.7 AC power to the receiving coil with a power transfer efficiency of 36% through the carbon composite barrier. The system achieves a bidirectional half-duplex data communication with the data rate of unit 1.2kbit/s.
Integrated cmos rectifier for rf-powered wireless sensor network nodesjournalBEEI
This article presents a review of the CMOS rectifier for radio frequency energy harvesting application. The on-chip rectifier converts the ambient low-power radio frequency signal coming to antenna to useable DC voltage that recharges energy to wireless sensor network (WSN) nodes and radiofrequency identification (RFID) tags, therefore the rectifier is the most important part of the radio frequency energy harvesting system. The impedance matching network maximizes power transfer from antenna to rectifier. The design and comparison between the simulation results of one- and multi-stage differential drive cross connected rectifier (DDCCR) at the operating frequencies of 2.44GHz, and 28GHz show the output voltage of the multi-stage rectifier doubles at each added stage and power conversion efficiency (PCE) of rectifier at 2.44GHz was higher than 28GHz. The (DDCCR) rectifier is the most efficient rectifier topology to date and is used widely for passive WSN nodes and RFID tags.
Design consideration in low dropout voltage regulator for batteryless power m...journalBEEI
Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism
reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of
IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions
to decrease power consumption while maintaining the quick transient response to signal variations. LDO
voltage regulators, as power management devices should adjust to modern technological and industrial
trends. To increase the current capability with a minimum standby quiescent current under small-signal
operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the
dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout.
As a result, the efficiency gets increased.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions to decrease power consumption while maintaining the quick transient response to signal variations. LDO voltage regulators, as power management devices should adjust to modern technological and industrial trends. To increase the current capability with a minimum standby quiescent current under small-signal operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout. As a result, the efficiency gets increased.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
2.4GHZ CLASS AB POWER AMPLIFIER FOR HEALTHCARE APPLICATIONijbesjournal
The objective of this research was to design a 2.4 GHz class AB Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. This paper introduces the design of a 2.4GHz class AB power amplifier which consists of two stage amplifiers. This power amplifier can transmit 10dBm output power to a 50Ω load. The power added efficiency is 7.5% at 1dB compression point and the power gain is 10dB, the total power consumption is 0.135W. The performance of the power amplifier meets the specification requirements of the desired.
Class D Power Amplifier for Medical Applicationieijjournal
The objective of this research was to design a 2.4 GHz class AB Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. This paper introduces the design of a 2.4GHz class D power amplifier which consists of two stage amplifiers. This power amplifier can transmit 15dBm output power to a 50Ω load. The power added efficiency was 50% and the total power consumption was 90.4 mW. The performance of the power amplifier meets the specification requirements of the desired.
CLASS D POWER AMPLIFIER FOR MEDICAL APPLICATIONieijjournal1
The objective of this research was to design a 2.4 GHz class AB Power Amplifier (PA), with 0.18um
Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence
software, for health care applications. The ultimate goal for such application is to minimize the trade-offs
between performance and cost, and between performance and low power consumption design. This paper
introduces the design of a 2.4GHz class D power amplifier which consists of two stage amplifiers. This
power amplifier can transmit 15dBm output power to a 50Ω load. The power added efficiency was 50%
and the total power consumption was 90.4 mW. The performance of the power amplifier meets the
specification requirements of the desired.
CLASS D POWER AMPLIFIER FOR MEDICAL APPLICATIONieijjournal
The objective of this research was to design a 2.4 GHz class AB Power Amplifier (PA), with 0.18um
Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence
software, for health care applications. The ultimate goal for such application is to minimize the trade-offs
between performance and cost, and between performance and low power consumption design. This paper
introduces the design of a 2.4GHz class D power amplifier which consists of two stage amplifiers. This
power amplifier can transmit 15dBm output power to a 50Ω load. The power added efficiency was 50%
and the total power consumption was 90.4 mW. The performance of the power amplifier meets the
specification requirements of the desired.
Design of Low Power, High PSRR Error Amplifier for Low Drop-Out CMOS Voltage...IJEEE
This paper presents design of an improved Error amplifier (EA) for Low Drop-Out Voltage Regulator. The proposed circuit shows good behaviour as compared to the previous Error Amplifier. The Gain, Unity Gain Bandwidth, Phase Margin, CMRR and PSRR of an Error Amplifier is analysed. The proposed circuit is designed on UMC 180nm CMOS technology with supply voltage of 1.8Volts. All the simulation results are calculated through SPECTRE Simulator of cadence.
A Novel Design of a Microstrip Microwave Power Amplifier for DCS Application ...IJECEIAES
This paper presents a 1.80GHz class-A Microwave power amplifier (PA). The proposed power amplifier is designed with single-stage architecture. This power amplifier consists of a bipolar transistor and improved by Collector-Feedback Biasing fed with a single power supply. The aim of this work is to improve the performance of this amplifier by using simple stubs with 50Ω microstrip transmissions lines. The proposed PA is investigated and optimized by utilizing Advanced Design System (ADS) software. The simulation results show that the amplifier achieves a high power gain of 13dB, output power rise up to 21dBm and good impedances matching ;For the input reflection coefficient (S11) is below than - 46.39dB. Regarding the output reflection coefficient (S22) is below than -29.898dB, with an overall size of about 93 x 59mm². By the end; we find that this power amplifier offers an excellent performance for DCS applications.
SOI RF Switch for Wireless Sensor NetworkADEIJ Journal
The objective of this research was to design a 0-5 GHz RF SOI switch, with 0.18um power Jazz SOI technology by using Cadence software, for health care applications. This paper introduces the design of a RF switch implemented in shunt-series topology. An insertion loss of 0.906 dB and an isolation of 30.95 dB were obtained at 5 GHz. The switch also achieved a third order distortion of 53.05 dBm and 1 dB compression point reached 50.06dBm. The RF switch performance meets the desired specification requirements.
A Two Channel Analog Front end Design AFE Design with Continuous Time ∑-∆ Mod...IJECEIAES
In this context, the AFE with 2-channels is described, which has high impedance for low power application of bio-medical electrical activity. The challenge in obtaining accurate recordings of biomedical signals such as EEG/ECG to study the human body in research work. This paper is to propose Multi-Vt in AFE circuit design cascaded with CT modulator. The new architecture is anticipated with two dissimilar input signals filtered from 2-channel to one modulator. In this methodology, the amplifier is low powered multi-VT Analog Front-End which consumes less power by applying dual threshold voltage. Type -I category 2 channel signals of the first mode: 50 and 150 Hz amplified from AFE are given to 2nd CT sigmadelta ADC. Depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in a 0.18 um standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in 0.18 m standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, programmable gains from 52.6 dB to 72 dB, input referred noise of 3.5 µV in the amplifier bandwidth, NEF of 3.
A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low
temperature coefficient (TC) is presented in this paper. Large 1μF off-chip load capacitor is used to
achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower
frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode
amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in
bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC.
The characteristic is achieved by implementing MOSFET transistors operate in weak and strong
inversions. The LDO is designed using 0.18 μm CMOS technology and achieves a constant 1.8 V output
voltage for input voltages from 3.2 V to 5 V and load current up to a 128mA at temperature between -40 °C
to 125 °C. The proposed LDO is targeted for RF application which has stringent requirement on noise
rejection over a broad range of frequency.
A NEW MODIFIED SYSTEM FOR EQUAL POWER DIVISION WITH LCC FOR WIRELESS APPLCATIONSijistjournal
In this paper, a new modified system for equal power division is implemented with the help of rectangular micro strip patch antenna, Gysel power divider and leakage cancellation circuit. Today’s world power division plays an important role in wireless application areas such as base stations, antenna arrays, handheld devices etc., Here micro strip patch antenna is implemented with FR4 as a substrate material due to its benefits such as low loss and low fabrication cost while the ground material is aluminium due to its conductivity. For a good system, the return loss should be highly desirable and insertion loss should be low. Our proposed system is designed with a combination of micro strip patch antenna, leakage cancellation circuit and Gysel power divider produces equal power division with low loss such as insertion loss is measured as -39.291dB, return loss as -16.11dB and leakage cancellation as 6dB which was designed and simulated in Agilent Advanced Design System software (2009).
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
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LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CARE
1. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.4, December 2016
DOI : 10.5121/ieij.2016.4402 7
LOW POWER SI CLASS E POWER AMPLIFIER AND
RF SWITCH FOR HEALTH CARE
Wei Cai1
, Jian Xu,2
and Liang Huang3
1
Department of Electrical Engineering and Computer Science, University of California,
Irvine, CA, USA
2
Division of Electrical and Computer Engineering, School of Electrical Engineering and
Computer Science, Louisiana State University, Baton Rouge, LA, USA
3
Department of Information & Electronic Engineering, ZheJiang Gongshang University,
Hang Zhou, Zhejiang, China
ABSTRACT
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired.
KEYWORDS
Cascode, Negative Capacitance, Class E, Power amplifier, Healthcare, RF switch
1. INTRODUCTION
Wireless Sensor Networks (WSN) can be widely applied to solve a vast array of problems, under
varied conditions[1]. Such WSNs can provide near-real time, non-stop data over a large sampling
area or population, by large distributing many devices to monitor the surrounding environment
[2][3][4][5][6][7][8][9]. WSNs could deliver considerable efficiencies to otherwise with costly
tasks [10][11][12]. For example, patient monitoring carries considerable cost, especially if used to
a large section of the patient. Desirable solutions can be recognized leveraging WSNs and the
present cellular communication. Academic and industry research is currently ongoing
investigating such frameworks [13][14][15][16][17][18].
Due to current hardware components restrictions, healthcare application of WSNs are still in the
early stages[19][20][21][22]. Such devices require Food and Drug Administration (FDA)
approval, which can be challenging and costly due to the requirement that the devices pass a
number of safety tests. Not so many companies and research institutions can successfully building
such a heath care device under full FDA approval [23].
WSNs consist of a number of networked elements, which are individually called sensor
nodes. Sensor nodes usually contain all kinds of hardware elements, such as batteries, sensors,
antennas, memory, ADC, FPGA, etc [24][25][26][30]. A major design challenge for medical
2. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.4, December 2016
8
applications is that - designs a cost effective device which would meet functional requirements
[2][27][28][29]. In order to implement such networks with a massive amount of nodes, each
node must be low cost. Typically, each device must provide long working cycles without battery
recharging. This pushes most sensor node designs to be super ultra-low power. Achieving this
low power performance at low cost are critical to making such sensor networks feasible[31][32].
The main design challenge for such WSN is the high power consumption of portable devices.
One possible answer to this task is the integration of the digital, analog and RF circuitry into one
chip. Thus, switch and power amplifiers have different and unique characteristics, which requires
different processes to tape out each one. But switches and PAs can be integrated on a single
SIP. A system in package (SiP) is a module that contains multiple integrated circuits. A SiP has
the same function as an electronics system. They are often used in the smart phones and
PCs. Dies could be connected via bondwires between packages. Alternatively, solder bumps may
be utilized in a stacked architecture in the package.
Figure 2. Block diagram of a transmitter
The receiver will receive the signal and will also perform DSP processing after the data is sent
out by the transmitter [32]. Figure 2 is the basic transmitter block. It is always desirable that the
transmitter and receiver are low power consumption. In order to meet the standards, the PA and
RF switch are designed as shown in table 1.
Table 1: PA design requirement.
Parameter Target(Unit)
Output Power 15 dBm
Power gain 50 dB
Stability >1
S11 -10 dB
Insertion 0-1.2 dB
Isolation >40 dB
IIP3 55 dB
2. METHODS
CMOS radio-frequency (RF) front-end circuits has developed extremely fast over the past 30
years. Getting the trade-offs between high performance and low cost, and between high
performance and low power consumption design, people always try to achieve these target[34].
3. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.4, December 2016
9
The cascode circuit with negative capacitance is shown in the figure 2. The advantage of this
structure is that it provides less parasitic capacitance, since it allows the parasitic capacitance to
be tuned at the driver stage. A shunt inductor instead of capacitor can also be inserted at the
driver stage to filter out the unwanted parasitic capacitance, at the cost of wafer area [33].
As seen in figure 2, a negative capacitance can be implemented by a capacitor with a common
gate amplifier. For class E power amplifiers, transistor M1 acts as a switch. Transistor M2
delivers high gain, when biased at saturation [35].
Figure 2. Block diagram of a class E power amplifier
To get the optimum bias, cadence simulation such as PSS are completed. Detailed design values
can be seen in Table 2.
Table 2: 2.4GHz PA driver stage component.
Parameter Size (Unit)
Q1 W/L=0.3um/0.6um (f=66,m=24)
Q2 W/L=0.3um/0.6um (f=66,m=24)
Q3 W/L=0.8um/0.6um (f=4,m=2)
L1 36nH (Q=20)
L2 20nH (Q=20)
L3 20nH (Q=20)
C1 240fH
C2 600fH
C3 11pF
R1 10.5ohm
R2 3.8Kohm
FET switches usually have three different topologies, such as series, shunt and combinatorial
topology. Due to modern, complicated requirements, users for in health care usually require the
4. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.4, December 2016
10
combinatorial topology to meet their stringent requirements, as seen in the Figure 3. When a
control voltage is set high, the series FET would be on, which means a signal would pass to the
following transistor, where a shunt FET would connect to the ground. When the control is set
low, the series FET is off, so there will be no signal flow through the transistor, however the
shunt FET will pass the signal.
In terms of RF switch performance, there are several key parameters, such as reflection
coefficient S11, insertion loss S21 and isolation S31[34][35]. S11 is the input reflection
coefficient, which is voltage ratio of the reflected wave on the input port to the original wave.
This parameter represents the power loss from impedance mismatches, also known as voltage
standing wave ratio (VSWR). S21 represents the forward voltage gain. A low insertion loss
between source and active switch is critical to increase the efficiency. S31 is also a very
important switch parameter. When there is 3 ports, two ports are on, and another port is off, and
this parameter is a measure of the transmission coefficient from the source to the off arm. This
parameter represents how much power was leaked into the off arm. Besides the S11, S21, S31, a
switch design’s value must also consider the intercept point (IP3). This parameter is a measure of
the linearity of a device, which also known as intermediation distortion. The third order intercept
point is where the intercept of the fundamental frequency and the third order of the fundamental
frequency. There are many other parameters that can be considered, but the S-parameters and the
IP3 are the critical ones that must often be considered. A good RF switch usually possesses: low
insertion loss, high isolation, high power handling, and very high ESD immunity. A shunt FET
would connect to the ground. When the control is set low, the series FET is off, so there will be
no signal flow through the transistor, however the shunt FET will pass the signal.
FETs are three terminal devices are usually fabricated as SOI or GaAs. The basic function is
shown in Fig. 3[34]. When the gate is more positively biased then the source, a channel would be
formed between the source and drain side, so the resistance is lowered, and a current can be
flowed between source and drain terminals. However, if the gate voltage is equal or smaller than
the source terminal, no channel will form, resistance will be much higher, and no current flows
through channel.
Figure 3. Modified series-shunt FET switch
5. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.4, December 2016
11
3. RESULTS
As seen in figure 4(a), the output power was 17 dBm. As seen in figure 4(b), the S11 is less than -10 dB at
2.4 GHz frequency, also, the total power consumption is 2.061 W.
As seen in figure 5(a), Kf is larger than 1 for all the simulated frequencies, so this design is completely
stable. And the power gain could reach 94 dB.
As seen in figure 6(a), at 5 GHz, an insertion loss is1.36 dB and an isolation is 58.5 dB.
(a) (b)
Figure 4. (a) Output power (b) S11
(a) (b)
Figure 5. (a) Kf (b) Power gain
6. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.4, December 2016
12
(a) (b)
Figure 6. (a) Insertion (green) and isolation (blue) (b) IIP3
4. CONCLUSION
This paper describes the method of designing and simulating power amplifier in SMIC CMOS
180 nm process and RF switch at SOI process 180nm technology. This PA and switch are used
for sensor networks which can be integrated at SIP. Such kind research is still under developing,
to realize this a low cost and low power device, future improvements are needed.
REFERENCES
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Authors
Wei Cai is a graduate student at the University of California, Irvine, CA. She
received her Masters degree from Dept. of Electrical Engineering, University of
Hawaii at Manoa and Bachelor degree from Zhejiang University, China. Her
research interests include device physics simulation, analog/ RF circuit design.
Jian Xu is an assistant professor at the Division of Electrical and Computer
Engineering in the School of Electrical Engineering and Computer Science of
Louisiana State University. He got his Ph. D. in Electrical Engineering at Yale
University. He received a B. S. and a M. S. degree in Physics at Nanjing
University, China. His research interest is in the Bioelectronics, Nanoelectronics
and Nanomedicine, and Biomedical instrumentation for image-guided cancer
surgery.
Liang Huang is an associate Professor, Electronics College of Zhejiang
Gongshang University. He got phd from Zhejiang University china, and finished
his postdoc at Polytechnic of Turin, Italy, and Hanyang University, Seoul, Korea.
His research is mainly focus on Research on: Intelligent Control; Electrical
Robotics.