This document discusses strategies to achieve low power dissipation in integrated circuits. It discusses several techniques: 1) Reducing dynamic power by minimizing transistor sizes, lowering supply voltage, and optimizing manufacturing processes. 2) Reducing static power by lowering subthreshold leakage through multiple threshold voltages and separating logic into high and low power groups. 3) Introducing a new logic style called Energy Economized Pass Transistor Logic (EEPL) that provides reductions in power and delay compared to other pass transistor logic styles like CPL and SRPL through regenerative feedback. 4) EEPL has been shown to perform well in combinational and sequential circuits like multipliers and counters with advantages of lower energy consumption.