This document discusses various techniques for reducing power consumption at different levels of digital design. At the gate level, power can be reduced by optimizing device sizing and fanout. Multiple supply voltages can be used within the same design to lower voltage in non-critical paths. At the architecture level, clock gating is introduced to power gate idle components. Clock gating finite state machines can reduce power based on the current state. Tradeoffs between power and delay can be achieved by adjusting the supply voltage.

1. Low-Power Owe n A .
Rana, Ian
Digital Design

2. Agenda
●
Recap
●
Power reduction on
 Gate level
 Architecture level
 Algorithm level
 System level
2

3. Recap: Problems of Power Dissipation
 Continuously increasing
performance demands
 Increasing power dissipation of
technical devices
 Today: power dissipation is a main
problem
 High Power dissipation leads to:
 Reduced time of operation
 Reduced time of operation  High efforts for cooling
 High efforts for cooling
 Higher weight (batteries)
 Higher weight (batteries)  Increasing operational costs
 Increasing operational costs
 Reduced mobility
 Reduced mobility  Reduced reliability
 Reduced reliability 3

4. Recap: Consumption in CMOS
 Voltage (Volt, V) Water pressure (bar)
 Current (Ampere, A) Water quantity per second (liter/s)
 Energy Amount of Water
1
CL
0
4
Energy consumption is proportional to capacitive load!

5. Recap: Energy and Power
Power is height of curve
Watts
Approach 1
Approach 2
time
Energy is area under curve
Watts
Approach 1
Approach 2
time
6
Energy = Power * time for calculation = Power * Delay

6. Recap: Power Equations in CMOS
P = α f CL VDD2 + VDD Ipeak (P0→1 + P1→0 ) + VDD Ileak
Dynamic power Short-circuit power Leakage power
(≈ 40 - 70% today (≈ 10 % today and (≈ 20 – 50 %
and decreasing decreasing today and
relatively) absolutely) increasing)
7

7. Recap: Levels of Optimization
8
nach Massoud Pedram

8. Recap: Logic Restructuring
 Logic restructuring: changing the topology of a logic
network to reduce transitions
AND: P0→1 = P0 * P1 = (1 - PAPB) * PAPB
3/16
0.5 A Y
0.5 (1-0.25)*0.25 = 3/16
A W 7/64 = 0.109 0.5 B 15/256
B X F
15/256 0.5
0.5 C C
0.5 D F
0.5 0.5 D Z
3/16 = 0.188
 Chain implementation has a lower overall switching activity than
tree implementation for random inputs
 BUT: Ignores glitching effects 9
Source: Timmernann, 2007

9. Recap: Input Ordering
(1-0.5x0.2)*(0.5x0.2)=0.09 (1-0.2x0.1)*(0.2x0.1)=0.0196
0.5 0.2
A B X
X
B C
F 0.1 A F
0.2 C
0.1 0.5
AND: P0→1 = (1 - PAPB) * PAPB
Beneficial: postponing introduction of signals with
a high transition rate (signals with signal
probability close to 0.5)
10
Source: Irwin, 2000

10. Recap: Glitching
A X
B
C Z
ABC 101 000
X
Z
Unit Delay
11
Source: Irwin, 2000

11. Design Layer: Gate Level
●
Basic elements:
 Logicgates
 Sequential elements (flipflops, latches)
●
Behavior of elements is described in libraries
12

12. Dynamic Power and Device Size
 Device Sizing (= changing gate width)
 Affects input capacitance Cin
1.5
 Affects load capacitance Cload fcircuit=1
normalized energy
 Affects dynamic power consumption Pdyn
1
fcircuit=2
 Optimal fanout factor f for Pdyn is smaller
than for performance (especially for fcircuit=5
large loads)
0.5 fcircuit=10
 e.g., for Cload=20, Cin=1
fcircuit=20
 fcircuit = 20
0
 fopt_energy = 3.53 1 2 3 4 5 6 7
fanout f
 fopt_performance = 4.47
13
 ForLow Power: avoid oversizing (f too Source: Nikolic, UCB
big) beyond the optimal

13. VDD versus Delay and Power
6 10
5 8
Relative Delay td
Relative Pdyn
4
td Pdyn 6
3
4
2
1 2
0 0
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
Supply voltage (VDD)
● Delay (td) and dynamic power consumption (Pdyn) are
functions of VDD 14

14. Multiple VDD
●
Main ideas:
 Use of different supply voltages within the same design
 High VDD for critical parts (high performance needed)
 Low VDD for non-critical parts (only low performance demands)
●
At design phase:
 Determine critical path(s) (see upper next slide)
 High VDD for gates on those paths
 Lower VDD on the other gates (in non-critical paths)
 For low VDD: prefer gates that drive large capacitances (yields
the largest energy benefits)
15
● Usually two different VDD (but more are possible)

15. Multiple VDD cont’d
●
Level converters:
 Necessary, when module at lower supply drives gate at higher
supply (step-up)
 If gate supplied with VDDL drives a gate supplied with VDDH
 then PMOS never turns off
 Possible implementation:
VDDH
 Cross-coupled PMOS transistors
 NMOS transistor operate on VDDL Vout
reduced supply Vin
 No need of level converters for
step-down change in voltage
 Reducing of overhead:
 Conversions at register boundaries
16
 Embedding of inside flipflop

16. Data Paths
●
Data propagate through different data paths between registers
(flipflops - FF)
●
Paths mostly differ in propagation delay times
●
Frequency of clock signal (CLK) depends on path with longest
delay  critical path
Paths
Path
17

17. Data Paths: Slack
A
G1 ready with
B evaluation
Y all inputs of G2
all Inputs of G1 arrived
arrived
C
18
delay of G1 Slack for G1 time

18. Multiple VDD in Data Paths
●
Minimum energy consumption when all logic paths are critical
(same delay)
●
Possible Algorithm: clustered voltage-scaling
 Each path starts with VDDH and switches to VDDL (blue gates)
when slack is available
 Level conversion in flipflops at end of paths
Connected with VDDL
Connected with VDDH 19

19. Design Layer: Architecture Level
●
Also known as Register transfer level (RTL)
●
Base elements:
 Register structures
 Arithmetic logic units (ALU)
 Memory elements
●
Only behavior is described
(no inner structure)
20

20. Clock Gating
●
Most popular method for power reduction of clock signals and
functional units
●
Gate off clock to idle functional units
●
Logic for generation of disable signal necessary
 Higher complexity of control logic R
Functional
 Higher power consumption e
unit
 Critical timing critical for avoiding of
g
clock glitches at OR gate output
 Additional gate delay on clock signal
clock
disable
21
Source: Irwin, 2000

21. Clock Gating cont’d
●
Clock-Gating in Low-Power Flip-Flop
D D Q
CLK
22
Source: Agarwal, 2007

22. Clock Gating cont’d
●
Clock gating over consideration of state in Finite-State-
Machines (FSM)
PI
Combinational
Flip-flops
logic PO
Clock
activation Latch
logic
Source: L. Benini and G. De Micheli, 23
CLK Dynamic Power Management, Boston: Springer, 1998.

23. Clock Gating: Example
Without clock gating
30.6mW
With clock gating
DEU
8.5mW VDE
MIF
0 5 10 15 20 25 DSP/
Power [mW]
HIF
896Kb SRAM
 90% of FlipFlops clock-gated
 70% power reduction by clock-gating
MPEG4 decoder 24
Source: M. Ohashi, Matsushita, 2002

24. Recap: VDD versus Delay and Power
6 10
5 8
Relative Delay td
Relative Pdyn
4
td Pdyn 6
3
4
2
1 2
0 0
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
Supply voltage (VDD)
Dynamic Power can be traded by delay 25

25. A Reference Datapath
Register
Register
Combinational
Input Output
logic
Cref
CLK
Supply voltage = Vref
Total capacitance switched per cycle = Cref
Clock frequency = fClk
Power consumption: Pref = CrefVref2fclk 26
Source: Agarwal, 2007

26. Thank You!!! :)