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IRPS2005 P5 A 1
- 1. Breakdown Characteristics of Interconnect Dielectrics Gaddi S. Haase , Ennis T. Ogawa And Joe W. McPherson SiTD, Texas Instruments, Inc. Dallas, TX, USA 5A.1
- 7. Experimental details: The test structure ILD = IMD = Orgno-Silicate Glass (OSG) ESL = SiC x N y Line-to-line spacing in a single test structure (DUT) Cu M1 level IMD ESL ILD
- 15. Example for Defect Detection When for low V bd events, does NOT decrease monotonically with decreasing V bd .
Editor's Notes
- Quick Low-k : leaky, traps Interfaces with ESL or cap span between Cu lines Thickness like gate oxide 2 decades ago
- 3 Fast!
- The E-model was shown phenomenologically by Berman (1981) For Const. Temp: Tbd decreases exponentially with the stress field E Later explained by McPherson with the thermochemical model: gamma= effective dipole over temperature Instead of constant-field time-dependent-dielectric BD test (slow) – we can ramp to breakdown = Constant time tests
- For Previous technologies (such as 130nm) line-to-line spacing variations had little effect on E Now (90nm) and on, the same spacing variation can give X3 higher E-uncertainty! spacing variations effect cannot be ignored Move to V space (not E) Minimum spacing cannot be picked up with SEM Xsection - need electrical means to measure it! *** Minimum s per DUT is not necessarily the true global minimum if has a low occurrence ***.
- Gamma – physical constant , slightly material dependent, but constant W2W, Lot2Lot A way to extract spacing electrically! S proportional to delta(Vbd) Knowing gamma = extract s Example – caps with uniform dielectric thickness (avoiding wafer edge): Delta(Vbd) is constant for all Vbd, since s & gamma are constant . The index I represents….
- Top down view of test structure DUT OSG (k=2.8-2.9), ESL 130nm is spacing between lines at mid height - much narrower at the top (to improve Cu-seed dep/ fill) For ONE single DUT: taking many X-sections & plot the spacing at top : we can easily see how s can go as low as 85-90 nm SEM - low chance of catching the true minimum s.
- We divide all the DUTs ( test structures ) to 2 well-mixed equivalent sister population An example for how the current vs. voltage….
- *** Slow down *** Tested at Different T one example of a few sets at different Temps and 3 different wafers Ramp rates are: same DeltaV Same data plotted as Cum. Plot and as Weibull plot: * Linear X scale for Vbd *Note that Weibull plot may not be linear… **** Note that Delta Vbd decreases – when Vbd decreases **** CLEAR Correlation between Vbd and S Use smoothed lines S distribution can be extracted if we know gamma . Here: since we already know the range of s from Xsections, we can fit gamma
- Another example : extreme temperature *** Emphasize DeltaV – Vbd correlation *** Fitting the same L2L spacing range – a new gamma Note again: i-replaced by F Only……..
- We repeated the 2RR tests at a few temperatures READ
- Sites – well mixed, avoid edges The lines are never perfectly parallel In the less noisy data - lines diverge as Vbd decreases (indicates s effect)
- Compare to 2RR
- Different lot, different technology node, different fab Weibull plot No monotonic decrease – beneath green line: from a particular zone on the wafer edge – Xsection SEM showed defected diff. barrier
- Next we need to explain the low activ. Energy and the gamma-T-independence Low-k contains Si-C, Si-H weaker bond with different polarity Interfaces Low-k dielectric are more leaky - higher chance for current-induced degradation *** Expalain picture: Fermi-level – dielectric VB CB At the high stress V - Electrons where shown to maintain high energy – partly ballistic - hot not thermalize with substrate (DiMaria) Every scattering event dumps much energy locally Substrate temp washes out (electron temp prevails)
- Al low field, other degradation mechanisms (Cu drift) may prevail
- I wish to thank out process/integration engineers and help from our reliability team members Back to CONCLUSIONS