The document discusses input-output devices and interrupt handling in a computer system. It describes: 1) How input from devices like keyboards is received through an input register and output to devices like printers is sent through an output register. 2) How interrupt handling works, with an interrupt flip-flop getting set when input or output flags are raised, causing the computer to save its return address and branch to an interrupt service program. 3) The interrupt cycle in more detail, explaining how the return address is stored and how the computer returns to the main program after servicing the interrupt.

1. INPUT –OUTPUT AND INTERRUPT
M.SANDHIYA M.SC(IT)
DEPARTMENT OF CS&IT
NADAR SARASWATHI COLLEGE OF ARTS&SCIENCE

2. INPUT- OUTPUT AND INTERRUPT
 A computer serve no useful it communication
with the external Environment Instruction and
data stored in memory must come from some
input device Computational result must be
transmitted to the user through some output
device commercial include many type of input
and output devices

3. INPUT –OUTPUT CONFIGURATION
 The terminal sends and receives serial
information each quantity of information has
eight bits of an alphanumeric code the serial
information form the keyboard is shifted in to
the input register INPR the serial information
for the printer is stored in the output register
OUTR the two register communication in
interface and the AC parallel the interface
receives serial keyboard transmits to INPR the
receiver interface receiver from OUTR serially

4. INPUT REGISTER
The Input register INPR consists of eight bits
and hold alphanumeric input the 1-bot input
flag FGI is a control flip-flop the flag bits is set to
1 available in input device is cleared to 0
accepted the computer initially the flag FGI
cleared 0 .key is struck in the keyboard an 8 bits
alphanumeric code shift in to INPR Input flag
FGI set to 1 once flag cleared be shifted into
INPR striking key

5. INPUT REGISTER
INPUT-OUTPUT SERIAL COMMUNTION COMPUTER REGISTER&
TERMIAL INTERFACE FLIP FLOPS
printer
FGO
INPR
Transmitter
interface
OUTR
Receiver
interface
AC
FGI
keyboard

6. OUTPUT REGISETR
 The output register OUTR .the output flag
FGO is set 1 the computer check the flag bit is
1. the AC transferred is parallel to OUTR and
FGO cleared to 0 .the computer load a new
character into OUTR when FGO is 0 the
condition that the output device is in the
process .

7. INPUT-OUTPUT INSTRUCTION
 input and output instruction are need for
transferring information to and from AC
register the flag bit interrupt facility .input
output operation code 1111 and recognized
the control when D7=& I=1the instruction
executed with the clock transition time signal
T3 each control function need boolean
relation D7LT3 the control function is
distinguished by one of the bit .

8. INPUT –OUTPUT INSTRUCTION
 D7IT3=P(common to all input-output instruction)
IR(i)=B[bit in IR(6-11)that specifies the instruction]
P: clear sc
INP PB11: SC 0 input character
OUT PB10: AC(0-7) INPR,FGI 0 output character
SKI PB9: OUTR AC(0-7),FGO 0 skip on input flag
SKO PB8: IF(FGI=1)Then(PC PC+1) skip on output flag
ION PB7: IF(FGI=1)Then(PC PC+1) interrupt enable on
IOF PB6: IEN 1 interrupt enable off

9. PROGRAM INTERRUPT
 The process of communication just described referred as
programming control transfer the
computer checking the flag difference
 information flow rate the computer and input output device
make many type of transfer consider computer instruction
cycle in 1as.assume that input output device transfer the
information at maximum rate of 10 character the interrupt
flip-flop cleared with two instruction .IEN cleared to 0 the flag
can not interrupt the computer the IEN is set 1.when R=0
instruction cycle IEN is control with the next instruction cycle
IEN =1,flip-flop r set to 1,control check value of R equal to 1

10. INTERRUPT CYCLE
 The interrupt cycle is a hardware implementation of
branch and save return address operation the return
address available in PC stored in a specific location
founder later the program return to the instruction
was interrupted the location be a processor register
memory stack specific memory location the memory
location 0 the return address control insert address 1
PC clear IEN and R.

11. INTERRUPT CYCLE
 Interrupt occurs and R is set to 1 the control
executing the instruction address 255 at the
time the return address 256 in PC The
programmer memory address 1120 BUN
instruction at address 1. t0 and finds R=1
 the instruction that return the computer to
original place in the main program is a branch
indirect instruction with an address part 0
the instruction is placed at the end IO service
program

12. DEMONSTRATION INTERRUPT
CYCLE
Memory ss Memory
0 BUS 1120
Main program
1 BUS 0
IO program
256
0 BUS 1120
Main program
IO program
1 BUS 0

13. FLOWCHART
= 0 = 1 interrupt cycle
R
O
E
Store return address
in location 0
M [0] PC
Fetch & decode
instruction
Branch to location
1 pc 1
IEN 0
R 0
Execute
instruction G

14. INTERRUPRT CYCLE
 The register transfer statement for the
interrupt cycle the interrupt cycle in initiated
the last execute phase if the interrupt flip-flop
R IS equal to 1 the flip-flop is set to 1 if IEN=1
FGI0R FGO are equale to 1 transition timing
signals T0,T1,OR T2 active the condition for
flip-flop R to 1
T0T1’T2’(IEN)(FGI+FGO):R 1

15. MODIFIED FETCH PHASE
 The symbol FGI and FGO in the control function
designates a logic OR operation this AND De d
with IEN and T0,’T1’,T2’
Instead of using only timing signals T0,T1 and T3
active
The condition for Flip flop R to 1to expressed
register transfer statement
 AND the timing signal with R
 The interrupt cycle stores return address
memory location
1 and IEN R and SC to 0 they sequence
microoperation