The document describes a project to implement a finite impulse response (FIR) filter on an ADSP-BF537 digital signal processor. It provides background on FIR filters and their properties. The project involved generating filter coefficients in Matlab, programming the FIR algorithm on the DSP board using tools like VisualDSP++, and simulating the lowpass filter output on a spectrum analyzer. Key instruments used included an oscilloscope, spectrum analyzer, function generator, and an evaluation board with the Blackfin DSP processor.
Analysis of different FIR Filter Design Method in terms of Resource Utilizati...ijsrd.com
In this paper fully parallel FIR filters are designed with different design method on FPGA for resource utilization and response analysis. fully parallel band-pass FIR filters with same specification designed and simulated on ISE. The suggested implementations are synthesized with Xilinx ISE 14.2 version. Results show comparison of three different filter design methods in terms of resource utilization.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This project describes a novel architecture based on Recursive Running Sum (RRS) filter implementation for wire and wireless data processing. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one tenth of required bit period. The intermediate data bit is decoded using magnitude comparator. The advantage of this architecture is that baud rate is decided by the window size so there is no need of any external “timer module” which is normally required for standard UARTs. The Recursive Running Sum (RRS) filter architecture with programmable window size of M is designed and modules are implemented with VHDL language. This project implementation includes many applications in wireless data communication Systems like RF, Blue tooth, WIFI, ZigBee wireless sensor applications. Total coding written in VHDL language. Simulation in Modelsim Simulator, Synthesis done by XILINX ISE 9.2i. Synthesis result is verified by the Chipscope. Input signal given from the keyboard and output is seen by the help of HyperTerminal.
Analysis of different FIR Filter Design Method in terms of Resource Utilizati...ijsrd.com
In this paper fully parallel FIR filters are designed with different design method on FPGA for resource utilization and response analysis. fully parallel band-pass FIR filters with same specification designed and simulated on ISE. The suggested implementations are synthesized with Xilinx ISE 14.2 version. Results show comparison of three different filter design methods in terms of resource utilization.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This project describes a novel architecture based on Recursive Running Sum (RRS) filter implementation for wire and wireless data processing. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one tenth of required bit period. The intermediate data bit is decoded using magnitude comparator. The advantage of this architecture is that baud rate is decided by the window size so there is no need of any external “timer module” which is normally required for standard UARTs. The Recursive Running Sum (RRS) filter architecture with programmable window size of M is designed and modules are implemented with VHDL language. This project implementation includes many applications in wireless data communication Systems like RF, Blue tooth, WIFI, ZigBee wireless sensor applications. Total coding written in VHDL language. Simulation in Modelsim Simulator, Synthesis done by XILINX ISE 9.2i. Synthesis result is verified by the Chipscope. Input signal given from the keyboard and output is seen by the help of HyperTerminal.
RISC Implementation Of Digital IIR Filter in DSPiosrjce
This paper is base on the implementation of Reduce Instruction set computer with the application of
Discrete Cosine transform (DCT) , Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier
Transform (FFT), Digital filter are performed by DSP system. Digital filter is one of the important contents of
digital signal process. The performance of the processor design is improved by using the pipeline approach. It
allows the processor to work on different steps of the instruction at the same time, thus more instruction can be
executed in a shorter period of time. The analysis of this processor will provide various features including
arithmetic operations. The speed of operation is mainly affected by the computational complexity due to
multipliers and adder modules of the digital systems. Our work will targets the computer architecture courses
and presents an FPGA (Field Programmable Gate Array) implementation of a MIPS (Microprocessor without
Interlocked Pipeline Stages) via VHDL (Very high speed integrated circuit Hardware Description Language)
design. The latency and computational time is utmost important in microprocessor. Thus we design the
multiplier and adder module with improve latency and computational time.
Highly Reliable Parallel Filter Design Based On Reduced Precision Error Corre...iosrjce
The project is mainly focusing on multiple error detection and correction. Digital filters are widely
used in signal processing and communication n systems. In some cases, the reliability of those systems is critical
and fault tolerant implementations are needed. So that, the idea is generalized to show that parallel FIR filters
can be protected using error correction codes. Triple Modular Redundancy (TMR) is the traditional mitigation
techniques for Field-Programmable Gate Arrays (FPGAs) subject to Single-Event Upsets (SEUs) in high
radiation environment. To overcome the problem, in our project we propose RFFF (Reduced Faultless FIR
Filter) is a technique combined with TMR used to multiple errors are detected and corrected. TMR increases
the parameters like area, power and delay. In RFFF, multiple errors are corrected and the comparison of parameters like area, power and delay of existing and the proposed technique is done
Performance Analysis of Fractional Sample Rate Converter Using Audio Applicat...iosrjce
Fractional rate converters which are generally used for many applications with different frequencies
and are an essential part of communication systems. In this paper fractional rate converter with use of both
FIR and Nyquist FIR have been compared and analyzed. Its implementation can be easily found in the
developing communication systems, but here results are taken for audio applications. The proposed design and
analysis have been developed with the help of MATLAB with order 50 for FIR and 71 for Nyquist, sampling
frequency 48000Hz. The filters are then interpolated by an interpolation factor 2 and decimated by a decimation
factor of 3. The cost implementation of both has been taken into consideration and a result is drawn which
concludes that fractional rate converter for Nyquist FIR filter much more cost effective as compared to the
fractional rate converter for FIR filter
Implementation Cost Analysis of the Interpolator for the Wimax Technologyiosrjce
The design of the multirate filter (programmable) has been proposed which can be used in digital
transceivers that meets 802.16d/e (wimax) standard in the wireless communication system. Wimax is a
technology emerging in the wireless communication system in order to increase the broadband wireless internet
access. As there is wide spread need of the digital representation of the signal for the transmission and storage
which create the challenges in DSP [1]. In this paper, analysis of the implementation cost of interpolator for the
wimax technology, and cost of interpolator is analyzed on the basis of number of adders and multiplier. The
Filters are designed using the FDA (filters design and analysis) tool in MATLAB.
It is sometimes desirable to have circuits capable of selectively filtering one frequency or range of frequencies out of a mix of different frequencies in a circuit. A circuit designed to perform this frequency selection is called a filter circuit, or simply a filter. A common need for filter circuits is in high-performance stereo systems, where certain ranges of audio frequencies need to be amplified or suppressed for best sound quality and power efficiency. You may be familiar with equalizers, which allow the amplitudes of several frequency ranges to be adjusted to suit the listener's taste and acoustic properties of the listening area. You may also be familiar with crossover networks, which block certain ranges of frequencies from reaching speakers. A tweeter (high-frequency speaker) is inefficient at reproducing low-frequency signals such as drum beats, so a crossover circuit is connected between the tweeter and the stereo's output terminals to block low-frequency signals, only passing high-frequency signals to the speaker's connection terminals. This gives better audio system efficiency and thus better performance. Both equalizers and crossover networks are examples of filters, designed to accomplish filtering of certain frequencies.
International Journal of Engineering Inventions (IJEI) provides a multidisciplinary passage for researchers, managers, professionals, practitioners and students around the globe to publish high quality, peer-reviewed articles on all theoretical and empirical aspects of Engineering and Science.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
Matlab Based Decimeter Design Analysis Wimax Appliacationiosrjce
A Digital down Converter (DDC), which is basically used to convert an intermediate frequency (IF)
signal to its baseband form, forms an integral part of wireless receivers. The major functional blocks of a DDC
constitute a mixer, Numerically Controlled Oscillator (NCO) and an FIR filter chain. In this paper, We can
comparison of two window and see the costs of all Window filters
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
RISC Implementation Of Digital IIR Filter in DSPiosrjce
This paper is base on the implementation of Reduce Instruction set computer with the application of
Discrete Cosine transform (DCT) , Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier
Transform (FFT), Digital filter are performed by DSP system. Digital filter is one of the important contents of
digital signal process. The performance of the processor design is improved by using the pipeline approach. It
allows the processor to work on different steps of the instruction at the same time, thus more instruction can be
executed in a shorter period of time. The analysis of this processor will provide various features including
arithmetic operations. The speed of operation is mainly affected by the computational complexity due to
multipliers and adder modules of the digital systems. Our work will targets the computer architecture courses
and presents an FPGA (Field Programmable Gate Array) implementation of a MIPS (Microprocessor without
Interlocked Pipeline Stages) via VHDL (Very high speed integrated circuit Hardware Description Language)
design. The latency and computational time is utmost important in microprocessor. Thus we design the
multiplier and adder module with improve latency and computational time.
Highly Reliable Parallel Filter Design Based On Reduced Precision Error Corre...iosrjce
The project is mainly focusing on multiple error detection and correction. Digital filters are widely
used in signal processing and communication n systems. In some cases, the reliability of those systems is critical
and fault tolerant implementations are needed. So that, the idea is generalized to show that parallel FIR filters
can be protected using error correction codes. Triple Modular Redundancy (TMR) is the traditional mitigation
techniques for Field-Programmable Gate Arrays (FPGAs) subject to Single-Event Upsets (SEUs) in high
radiation environment. To overcome the problem, in our project we propose RFFF (Reduced Faultless FIR
Filter) is a technique combined with TMR used to multiple errors are detected and corrected. TMR increases
the parameters like area, power and delay. In RFFF, multiple errors are corrected and the comparison of parameters like area, power and delay of existing and the proposed technique is done
Performance Analysis of Fractional Sample Rate Converter Using Audio Applicat...iosrjce
Fractional rate converters which are generally used for many applications with different frequencies
and are an essential part of communication systems. In this paper fractional rate converter with use of both
FIR and Nyquist FIR have been compared and analyzed. Its implementation can be easily found in the
developing communication systems, but here results are taken for audio applications. The proposed design and
analysis have been developed with the help of MATLAB with order 50 for FIR and 71 for Nyquist, sampling
frequency 48000Hz. The filters are then interpolated by an interpolation factor 2 and decimated by a decimation
factor of 3. The cost implementation of both has been taken into consideration and a result is drawn which
concludes that fractional rate converter for Nyquist FIR filter much more cost effective as compared to the
fractional rate converter for FIR filter
Implementation Cost Analysis of the Interpolator for the Wimax Technologyiosrjce
The design of the multirate filter (programmable) has been proposed which can be used in digital
transceivers that meets 802.16d/e (wimax) standard in the wireless communication system. Wimax is a
technology emerging in the wireless communication system in order to increase the broadband wireless internet
access. As there is wide spread need of the digital representation of the signal for the transmission and storage
which create the challenges in DSP [1]. In this paper, analysis of the implementation cost of interpolator for the
wimax technology, and cost of interpolator is analyzed on the basis of number of adders and multiplier. The
Filters are designed using the FDA (filters design and analysis) tool in MATLAB.
It is sometimes desirable to have circuits capable of selectively filtering one frequency or range of frequencies out of a mix of different frequencies in a circuit. A circuit designed to perform this frequency selection is called a filter circuit, or simply a filter. A common need for filter circuits is in high-performance stereo systems, where certain ranges of audio frequencies need to be amplified or suppressed for best sound quality and power efficiency. You may be familiar with equalizers, which allow the amplitudes of several frequency ranges to be adjusted to suit the listener's taste and acoustic properties of the listening area. You may also be familiar with crossover networks, which block certain ranges of frequencies from reaching speakers. A tweeter (high-frequency speaker) is inefficient at reproducing low-frequency signals such as drum beats, so a crossover circuit is connected between the tweeter and the stereo's output terminals to block low-frequency signals, only passing high-frequency signals to the speaker's connection terminals. This gives better audio system efficiency and thus better performance. Both equalizers and crossover networks are examples of filters, designed to accomplish filtering of certain frequencies.
International Journal of Engineering Inventions (IJEI) provides a multidisciplinary passage for researchers, managers, professionals, practitioners and students around the globe to publish high quality, peer-reviewed articles on all theoretical and empirical aspects of Engineering and Science.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
Matlab Based Decimeter Design Analysis Wimax Appliacationiosrjce
A Digital down Converter (DDC), which is basically used to convert an intermediate frequency (IF)
signal to its baseband form, forms an integral part of wireless receivers. The major functional blocks of a DDC
constitute a mixer, Numerically Controlled Oscillator (NCO) and an FIR filter chain. In this paper, We can
comparison of two window and see the costs of all Window filters
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Fault Tolerant Parallel Filters Based On Bch CodesIJERA Editor
Digital filters are used in signal processing and communication systems. In some cases, the reliability of those
systems is critical, and fault tolerant filter implementations are needed. Over the years, many techniques that
exploit the filters’ structure and properties to achieve fault tolerance have been proposed. As technology scales,
it enables more complex systems that incorporate many filters. In those complex systems, it is common that
some of the filters operate in parallel, for example, by applying the same filter to different input signals.
Recently, a simple technique that exploits the presence of parallel filters to achieve multiple fault tolerance has
been presented. In this brief, that idea is generalized to show that parallel filters can be protected using Bose–
Chaudhuri–Hocquenghem codes (BCH) in which each filter is the equivalent of a bit in a traditional ECC. This
new scheme allows more efficient protection when the number of parallel filters is large.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to
provide signal processing in wireless communication system. There are many
applications in which sampling rate must be changed. Interpolators and decimators are
utilized to increase or decrease the sampling rate. In this paper an efficient method has
been presented to implement high speed and area efficient interpolator for wireless
communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate
operations with look up table (LUT) accesses. Interpolator has been
implemented using Partitioned distributed arithmetic look up table (DALUT)
technique. This technique has been used to take an optimal advantage of embedded
LUTs of the target FPGA. This method is useful to enhance the system performance in
terms of speed and area. The proposed interpolator has been designed using half band
poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx
Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The
proposed LUT based multiplier less approach has shown a maximum operating
frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by
consuming considerably less resources to provide cost effective solution for wireless
communication systems.
Power efficient and high throughput of fir filter using block least mean squa...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of Multiplier Less 32 Tap FIR Filter using VHDLIJMER
This Paper provide the principles of Distributed Arithmetic, and introduce it into the FIR
filters design, and then presents a 32-Tap FIR low-pass filter using Distributed Arithmetic, which save
considerable MAC blocks to decrease the circuit scale and pipeline structure is also used to increase the
system speed. The implementation of FIR filters on FPGA based on traditional method costs considerable
hardware resources, which goes against the decrease of circuit scale and the increase of system speed.
It is very well known that the FIR filter consists of Delay elements, Multipliers and Adders. Because of
usage of Multipliers in early design gives rise to 2 demerits that are:
(i) Increase in Area and
(ii) Increase in the Delay which ultimately results in low performance (Less speed).
So the Distributed Arithmetic for FIR Filter design and Implementation is provided in this work to solve
this problem. Distributed Arithmetic structure is used to increase the recourse usage and pipeline
structure is used to increase the system speed. Distributed Arithmetic can save considerable hardware
resources through using LUT to take the place of MAC units
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Filtering is an important mitigation technique for suppressing undesired conducted electromagnetic interference, when a system incorporates shielding, undesired coupling caused by radiated EMI is reduced. Conventional filter analysis and design assumes idealized and simplified conditions. These assumptions are not completely valid in many EMI filter because of unavoidable and severe impedance mismatch. Classical passive filter theory is well developed for communication circuits, where one can operate under impedance-matched conditions. Such filter characteristics are evaluated with 50Ω terminations. Filter evaluated with this procedure may behave differently when used in a circuit, where the impedance presented by the circuit to the filters is not exactly 50Ω. Now a day, digital signals are mostly used to avoid such EMI effects. These are caused by the capacitors, inductors, which are also part of the filtering circuits. Filter design using software, like MATLAB is very useful in avoiding hardware, is highly immune to noise and possesses considerable parameter stability, can be operated over a wide range of frequencies. The frequency response can be changed by changing the filter coefficients and can minimize the Insertion loses (IL).
Performance Analysis and Simulation of Decimator for Multirate ApplicationsIJEEE
In this paper, a decimator design has been presented for multirate digital signal processing. The decimator design has been analysed and simulated for performance comparison in terms of filter order and ripple factor. Direct form-I with decimation factor 2 have been used for performance and ripple analysis. The decimators have been designed & simulated using MATLAB. It can be observed from the simulated results that as we increase the filter order, ripple factor decreases, for the same filter structure. On the other hand, increasing filter order will increase its area and implementation cost.
A High Speed Transposed Form FIR Filter Using Floating Point Dadda MultiplierIJRES Journal
There is a huge demand in high speed area efficient parallel FIR filter using floating point dadda algorithm, due to increase performance of processing units. Area and spped are usually confictiong constraints so that improving speed results mostly in large areas. In our research we will try to determine the best solution to this problem by comparing the results of different multipliers. Different sized of two algorithm for high speed hardware multipliers were studied and implemented ie.dadda and booth multipliers. The working of these two multipliers were studied and implementing each of them separately in VHDL. The results of this research will help us to choose the better option between multipliers for floating point multiplier for fabricating different system.
FPGA Implementation of Higher Order FIR Filter IJECEIAES
The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.
Simulation Study of FIR Filter based on MATLABijsrd.com
First, the rapid design of FIR digital filter was completed by using the Signal Processing Toolbox FDA Tool, the case filter design of a composite signal by filtering, to prove that the content filter designed for filtering. MATLAB and Simulink programs of the filter were used to verify the performance of the filter in MATLAB. Experimental results show that the low-pass filter filters the high frequency component of input signals mixed. Comparison of two types of simulation, the latter method was more convenient quickly, and reduces the workload.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...
INDUSTRIAL TRAINING REPORT
1. PROJECT REPORT
“Implementation of FIR Filter on ADSP-BF537
DSP Processor”
(From- 08 June 2016 to 21 July 2016)
At
Defense Electronics Applications Laboratory (DEAL)
Dehra Dun ABHISHEK DABRAL
Roll No. 130970102002
B.Tech, 3rd Year ECE
THDC-Institute Of Hydropower
Engineering And Technology,
New Tehri, Uttarakhand
2. D.R.D.O(DEFENCE RESEARCH &
DEVELOPMENT ORGANISATION)
Defence Research & Development Organisation (DRDO) works under Department of
Defence Research & Development of Ministry of Defence .DRDO dedicatedly working
towards enhancing self-reliance in Defence Systems and undertakes design &
development leading to production of world class weapon systems and equipment in
accordance with the expressed needs and qualitative requirements laid down by three
services . DRDO while striving to meet the cutting edge weapons technology requirements
provides ample spinoff benefits to the society at large thereby contributing to nation
building.
3. INTRODUCTION
• One of the most important application of digital signal processing in communication
equipment is filtering.
• A digital filter is a system that performs mathematical operations on a sampled,
discrete time signal to reduce or enhance certain aspects of that signal.
• Filters are required to select the desired signal and reject unwanted signals and noise.
• Actual filtering is not done by manual calculations, the coefficients of filters are
calculated using softwares which allows the designer to examine frequency response
and other parameters.
4. Finite Impulse-Response
(FIR)Filter
An Fir filter is a filter whose impulse response is of finite duration, because it
settles to zero in finite time.
The impulse response of FIR filter is equal to its coefficients .
The value of each output sequence is a weighted sum of most recent input
values which is also called convolution.
yn =
i=0
N−1
xn−ihi
5. X(n)
Taking the z-transform gives:
Y (z) = 𝑖=1
𝑁−1
ℎ𝑖 X(z)z-1
Block Diagram of Finite Impulse Response (FIR) filter
And the transfer function is,
𝑯 𝒛 =
𝒀(𝒁)
𝑿(𝒛)
6. Properties:
A FIR filter has a number of useful properties which sometimes make it preferable to an infinite impulse
response (IIR) filter. FIR filters:
Require no feedback. This means that any rounding errors are not compounded by summed iterations. The
same relative error occurs in each calculation. This also makes implementation simpler.
Are inherently stable, since the output is a sum of a finite number of finite multiples of the input values, so
can be no greater ∑bi times the largest value appearing in the input.
They can easily be designed to be linear phase by making the coefficient sequence symmetric. This property
is sometimes desired for phase-sensitive applications, for example data communications, crossover filters,
and mastering.
7. Advantages of using this technique:
They can easily be designed to be “linear phase”.
They are simple to implement on most DSP processors, the FIR calculation can be done by looping a single instruction.
They are suited to multi rate applications. By multi-rate, we mean either decimation (increasing the sampling rate) or
interpolation(decreasing the sampling rate), or both. Whether decimation or interpolation, the use of FIR filter allows
some calculations to be omitted, thus providing an important computational efficiency.
They have desirable numeric property. In practise, all DSP filter must be implemented using “finite precision”
arithmetic that is a limited no. of bits, the use of finite precision arithmetic in IIR filter can cause significant problems
due to the use of feedback, so they can using fewer bits, and the designer has fewer practical problems to be solved
related to non-ideal arithmetic.
Complete stability at all frequencies regardless of size of filter.
8. Disadvantages of using FIR filter:
FIR filet also comes with some disadvantages as well:
The frequency response is not as easily defined as it with IIR filters.
The number of states required to meet a frequency specification may far larger than required for IIR
filters.
FIR filter sometimes have a disadvantage that they require more memory and/ or calculations to
achieve a given filter response characteristics.
Also, certain response is not practical to implement with FIR filters.
More computational power in general purpose processor is required compared to IIR filter with
similar sharpness or selectivity.
9. Blackfin Embedded Processor ADSP-BF537
• Upto 600MHz high performance BlackFin processor.
• 132Kb on chip full speed SRAM.
• 10 stage RISC MCU/DSR pipeline.
10. The VisualDSP++ IDE
Analog Devices supports its processors with a complete line of software and hardware development tools,
including integrated development environments( like CrossCore® EmbeddedStudio and/or VisualDSP++®)
evaluation products, emulators, and a wide variety of software add-ins.
11. STEPS INVOLVED IN PROGRAMMING OF FIR FILTER:
Generate filter coefficients in matlab for various decimating filters.
Initialize all the parameters required in main function along with the coefficient buffers.
Initialize all the port values required in initialize file along with defining the appropriate default functions.
Design Fir filters using these coefficients in convolution in Process data function.
Define all the interrupt service routines in the interrupt file used for timers along with default functions.
Include all the necessary header files and declare all the used parameters in the Talkthrough header file.
12. Algorithm for implementing filter
Create an array h[i] storing the coefficients.
Create another array x[n] to store the sampled signals.
REPEAT:
Store the current sample at x[0].
Multiply the corresponding elements of the x[n] and h[i].
Add all the values of x[n]*h[i].
Send the sum to the output buffer.
Shift the values of the array x[n] by one element and store new sample at
x[0].