Digital signal processor part4

Books.Books.
1.1. Digital Signal Processing Principles, Algorithms and ApplicationsDigital Signal Processing Principles, Algorithms and Applications
John G.Proakis & Dimitris G.Manolakis
2.2. Digital Signal ProcessingDigital Signal Processing By.
Sen M. Kuo & Woon-Seng Gan
3.3. Digital Signal Processing A Practical Approach.Digital Signal Processing A Practical Approach. By
Emmanuel C. Ifeachor & Barrie W. Jervis
4.4. Digital Signal Processing By Dr. Krishnanaik Vankdoth LAPDigital Signal Processing By Dr. Krishnanaik Vankdoth LAP
LAMBERT Academic Publishing Dnfscland/Germany – 2014LAMBERT Academic Publishing Dnfscland/Germany – 2014
krishnanaik.ece@gmail.com 2

3
Grading Policy
krishnanaik.ece@gmail.com
Assignments 1 & 2
20 Marks
Quiz Test -Mid-Term 30 Marks
Final Exam 50 Marks
Class will be divided different level as per their GPA
Group A- GPA
Group B- GPA
Group C – GPA

Multirate Digital Signal
Processing
4Dr. V. Krishnanaik Ph.D

Processing
• systems that employ multiple sampling rates in
the processing of digital signals are called
multirate digital signal processing systems.
• Multirate systems are sometimes used for
sampling-rate conversion
• In most applications multirate systems are
used to improve the performance, or for
increased computational efficiency.
5krishnanaik.ece@gmail.com

Processing
• The basic Sampling operations in a
multirate system are:

Sampling Rate Reduction by Integer Factor D

Sampling Rate Reduction by Integer
Factor D
H(n)
Downsampler
D
Digital anti-aliasing
filter
Sampling-rate
compressor

Sampling Rate Reduction by Integer
Factor
D

Sampling Rate Reduction by
Integer Factor D

Integer Factor D

Sampling Rate Increase by
Integer Factor I
• Interpolation by a factor of L, where L is a
positive integer, can be realized as a two-step
process of upsampling followed by an anti-
imaging filtering.
L LPF

Sampling Rate Increase by Integer
Factor I
• An upsampling operation to a discrete-time
signal x(n) produces an upsampled signal
y(m) according to

Factor I
• The frequency domain representation of upsampling can be found by
taking the z-transform of both sides

Factor I

Sampling rate conversion by a rational factor ‘L/D’ can be
achieved by first performing interpolation by the factor ‘L’ and
then decimation the interpolator o/p by a factor ‘D’ .
In this process both the interpolation and decimator are cascaded
as shown in the figure below:
Upsampl
er
I
Downsam
pler
D
Sampling RateSampling Rate conversionconversion by Integer Rationalby Integer Rational
Factor L/DFactor L/D

• Example:
Consider a multirate signal processing problem:
i. State with the aid of block diagrams the process
of changing sampling rate by a non-integer factor.
ii.Develop an expression for the output y[n] and
g[n] as a function of input x[n] for the multirate
structure of fig .

• Answer:
i. .
1.We perform the upsampling process by a
factor L following of an interpolation filter
h1(l).
2.We continue filtering the output from the
interpolation filter via anti-aliasing filter h2(l)
and finally operate downsampling.

Sampling Rate conversion by Integer Rational
Factor L/D
ii.

Polyphase filters
• Polyphase filters A very useful tool in multirate signal
processing is the so-called poly phase representation of
signals and systems facilitates considerable simplifications
of theoretical results as well as efficient implementation of
multirate systems.
• To formally define it, an LTI system is considered with a
transfer function

Applications of
Multirate DSP
• Multirate systems are used in a CD player when the
music signal is converted from digital into analog
(DAC).

Applications of
Multirate DSP

Applications of
Multirate DSP
The effect of oversampling also has some other
desirable features:
 Firstly, it causes the image frequencies to be much
higher and therefore easier to filter out.
 Secondly reducing the noise power spectral
density, by spreading the noise power over a
larger bandwidth.

High quality Analog to Digital conversion for
digital audio

Digital Signal Processor
38Dr. V. Krishnanaik Ph.D

What is a dsp processor?
• It is a type of processor which is generally used to process
real time data.
• DSP applications such as convolution , correlation need
array multiplication.
• In such cases it is required that multiplication should be
completed before arrival of next input sample in the array.
• Most DSP algorithms involve repetitive arithmetic
operations such as multiply and add, multiple memory
access , heavy dataflow through CPU.
• For these functions to be performed advanced DSP
architecture is required.

DSP BLOCKS
• The internal hardware of a digital signal
processor consists of many blocks:
1.CPU
2.Arithmetic Logic Unit (ALU)
3.Accumulators
4.Barrel shifter
5.Multiplier unit
6.Compare Select and Store Unit ( CSSU )
7.Memory cache
8.DMA controller

GENERAL DSP ARCHITECTURE

Dsp MEMORY architecture
• The DSP architecture is of three types:
1.Von Neumann Architecture
2.Harvard Architecture
3.Super Harvard Architecture (SHARC)

VON NEUMANN ARCHITECTURE
• Von Neumann architecture contains a single memory and a
single bus for transferring data into and out of the central
processing unit (CPU).
• Multiplying two numbers requires at least three clock cycles, one
to transfer each of the three numbers over the bus from the
memory to the CPU. We don't count the time to transfer the
result back to memory, because we assume that it remains in the
CPU for additional manipulation (such as the sum of products in
an FIR filter).
• The Von Neumann design is quite satisfactory when you are
content to execute all of the required tasks in serial.

Harvard architecture
• It has separate memories for data and program
instructions, with separate buses for each. Since the
buses operate independently, program instructions
and data can be fetched at the same time, improving
the speed over the single bus design.
• This architecture increases the speed of computation
as compared to Von Neumann architecture.

Super Harvard architecture (sharc)
• SHARC® DSPs, a contraction of the longer
term, Super Harvard ARChitecture.
• SHARC DSPs are optimized by addition of: an instruction
cache, and an I/O controller.
INSTRUCTION CACHE
• DSP algorithms generally spend most of their execution
time in loops, such as instructions . This means that the
same set of program instructions will continually pass from
program memory to the CPU. By including an instruction
cache in the CPU. It is a small memory that contains about
32 of the most recent program instructions. On additional
executions of the loop, the program instructions can be
pulled from the instruction cache. This means that all of the
memory to CPU information transfers can be accomplished
in a single cycle.

Super Harvard architecture (sharc)
I/O CONTROLLER
•The SHARC DSPs provides both serial and parallel communications ports.
These are extremely high speed connections. For example, at a 40 MHz clock
speed, there are two serial ports that operate at 40 Mbits/second each, while six
parallel ports each provide a 40 Mbytes/second data transfer. When all six
parallel ports are used together, the data transfer rate is an incredible 240
Mbytes/second.
•Thus the I/O port helps in faster execution.

Pipelining
• It is a technique which allows two or more operations to
overlap during execution.
• DSP algorithms are repetitive making them suitable for
pipelining .
• It ensures a steady flow of instructions to the CPU and
increases system performance.
• In pipelining each instruction still takes three clock cycles
but at each cycle the processor is executing up to three
different instructions.
• It has an impact upon the system memory . The no.of
memory accesses increases by the no.of stages.
• In Harvard architecture the separation of data and
instruction memory promotes pipelining.
• It also allows better utilisation of arithmetic unit.

PIPELINING

Multiplier-ACCUMULATOR UNIT (MAC)
• DSP operations involve many time consuming multiplications
and additions.
• To make real-time operation faster multiplier-accumulator
(MAC) unit using fixed or floating point arithmetic is mandatory.
• The MAC unit consists of a multiplier that has a pair of input
registers that holds the inputs to the multiplier and a 32 bit
product register which holds the result of a multiplication.
• The output of the product register is connected to a double
precision accumulator where the products are accumulated.
• Floating point MACs allow fast computation with minimal
errors.

MAC UNIT

Multiplier/adder unit
• The multiplier/adder block consists of several elements:
1. A multiplier , an adder ,signed/unsigned input
2. Control logic
3. Zero detector, a rounder, overflow logic
• The multiplier/adder unit performs 17 X 17 bit multiplication
with 40 bit addition in a single instruction cycle.

1. Genaral purpose digital signal processors
1. High speed microprocessor
2. Architechture & Instruction sets optimized for DSP operations
1. Fixed point processors ( TMS320C5x, TMS320C54x,
DSP563x)
2. Floating point processors (TMS320C4x, TMS320C67xx)
3. Analog devices (ADSP21xx)
2. Special purpose digital signal processors
1. H/W designed for specific DSP algorithms such as FFT.
2. H/W designed for specific DSP applications such as PCM &
filtering.
1. Mitel’s multi channel telephony voice echo canceller
(MT93001)
2. FFT processor (PDSP 16515A, TM-44, TM-66)
3. Programmable FIR filter (UDSP 16256, Model3092)

Need of digital signal processor

The tms320c3X
• First Texas Instruments 32-bit floating point
digital signal processors.
• It is :
» Easy-to-use architecture
» High performance
• Applications:
» Automotive applications
» Digital audio
» Industrial automation & control
» Data communication
» Office equipments like copiers, laser printers,
etc.
• It has Independent
multiplier and ALU to offer
upto 60 million floating-
point operations per second
(MFLOPS)
• It has upto 30 MIPS.
• Total memory space is 16
million 32-bit words.

The tms320c4X
• 32-bit floating point digital signal
processors optimized for parallel
processing.
• It is :
» DMS controller with upto 6 com ports
» High performance
» On chip analysis module that supports h/w
breakpoints for parallel processing dev & debugging
• Applications:
» 3-D graphics
» Image processing
» Networking
» Telecommunication base station 56krishnanaik.ece@gmail.com

The tms320c5X
• Accepts source code from the ‘C1x, ‘C2x
and ‘C2xx generations.
• It is :
» Faster cycle times
» On chip memories
» A Parallel Logic Unit (PLU)
» Zero overhead context switching
» Block repeats differentiate the ‘C5x
• It has also an ANSI C compiler designed
for the ‘C5x, which translates the widely
used ANSI C language directly into highly
optimized assembly language for the ‘C5x.57krishnanaik.ece@gmail.com

The tms320c55X
• 16-bit fixed-point packaged DSP
processor.
• It can execute upto 2 instructions in
parallel (instruction width 8 – 48 bits)
» Interfaces directly to SDRAM
» Used where large memory buffers are needed
• Application:
» Digital cameras
» CD-ROM
» Audio players

The tms320c62XX
• Fixed-point DSP processor.
• It is based on VLIW architecture
• For example:
• TMS320C62xx works at 200MHz with 1.8V core
supply
• It executes upto 400 millions MACs per second.

Von Neumann architecture
• Proposed by John Von
Neumann
• Also known as the Von
Neumann
model and Princeton
architecture
• Program instructions stored
in ROM
• Both read/write of data and
reading of instructions can’t
be performed simultaneously

Von Neumann architecture
Single System Bus

Modified/super Harvard
architecture (sharc®
)

Very long instruction word
architecture

Very long instruction word
architecture
• Advantages
– Increased performance
– Better compiler targets
– Potentially easier to
program
– Potentially scalable
– Can add more execution
units, allow more
instructions to be
packed into VLIW
instruction.
• Disadvantages
• New kind of
programmer/compiler
complexity
• Program must keep track
of instruction scheduling
• Increased memory use
• High power consumption
• Misleading MIPS ratings

Dr. Krishnanaik VankdothDr. Krishnanaik Vankdoth
B.EB.E(ECE),(ECE), M.TechM.Tech (ECE),(ECE), Ph.DPh.D (ECE)(ECE)
Professor in ECE Dept
Aksum University, Ethiopia– 1010
Krishnanaik.ece@gmail.com
Krishnanaik_ece@yahoo.com
Phone : +919441629162
krishnanaik.ece@gmail.com 68

Digital signal processor part4

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