![VLSI Email: vlsi@pantechmail.com
[ Xilinx ISE & Spartan FPGA's]
www.pantechsolutions.net|www.pantechproed.com 8 | P a g e
©2016 Pantech ProEd Private Limited
PROJECT
CODE
PROJECT THEME APPLICATION TECHNOLOGY
| CORE
PSVLSI 801
Low Input Resistance CMOS Current Comparator
Based on the FVF for Low-Power Applications
Analog to Digital
Converter
2016
CADENCE
MEMORY|ANALOG|DIGITALCIRCUITS
PSVLSI 802
Cyclic Combinational Gate Diffusion
Input(CCGDI) Technique- A New Approach of Low
Power Digital Combinational Circuit Design ALU Design
PSVLSI 803
Self-gated resonant-clocked flip-flop optimized for
power efficiency and signal integrity
Photovoltaic
System
PSVLSI 804 Reliable Power Gating With NBTI Aging Benefits Photovoltaic
PSVLSI 805
Accurate and efficient Estimation of Dynamic
Virtual Ground Voltage in Power Gated Circuits Photovoltaic
PSVLSI 806
Characterization of a Novel Low Leakage Power and
Area Efficient 7T SRAM Cell
Consumer
Electronics
PSVLSI 807
Variation Tolerant Differential 8T SRAM Cell for
Ultralow Power Applications Router Buffers
PSVLSI 808
Sub threshold Level Shifter with Self Controlled
Current Limiter by Detecting Output Error
Power
Management
PSVLSI 809 Low-power technique for dynamic comparators
Analog to Digital
Converter
PSVLSI 810 A Modified SRAM Based Low Power Memory Design Router
PSVLSI 811
A New Sense Amplifier Topology with Improved
Performance for High Speed SRAM Applications Router
PSVLSI 812
Characterization of a Novel Low Leakage Power and
Area Efficient 7T SRAM Cell Router
PSVLSI 813
Accurate and Efficient Estimation of Dynamic
Virtual Ground Voltage in Power Gated Circuits
Power
Management
PSVLSI 814
Design Methodology for Voltage-Scaled Clock
Distribution Networks
Standalone
systems
PSVLSI 815
A Modified Partial Product Generator for
Redundant Binary Multipliers Digital Multipliers
XILINXISE|MODELSIM
REGISTERTRANSFERLOGIC|
ARCHITECTUREDESIGN
PSVLSI 816
High-Speed and Energy-Efficient Carry Skip Adder
Operating Under a Wide Range of Supply Voltage
Level
Digital Signal
Processing
PSVLSI 817
Low-Cost High-Performance VLSI Architecture for
Montgomery Modular Multiplication Digital Multipliers
PSVLSI 818
Efficient FPGA-Implementation of Two’s
Complement Digit-Serial/Parallel Multipliers Digital Multipliers
PSVLSI 819
A CDF based Lifting scheme for the satellite image
compression Access Control](https://image.slidesharecdn.com/pantech-vlsixilinxisespartanfpga2016-17-161215125545/85/pantech-vlsi-xilinx-ise-amp-spartan-fpga-201617-1-320.jpg)
![VLSI Email: vlsi@pantechmail.com
[ Xilinx ISE & Spartan FPGA's]
www.pantechsolutions.net|www.pantechproed.com 9 | P a g e
©2016 Pantech ProEd Private Limited
PSVLSI 820
Reversible Data Hiding in Encrypted Image with
Distributed Source Encoding Defense
PSVLSI 821
An Efficient Hardware Implementation of Canny
Edge Detection Algorithm Machine Vision
PSVLSI 822
Design & Optimization of FinFET based Schmitt
Trigger using Leakage Reduction Techniques Sensor Networks
2015
LOWPOWERDESIGN
COMBINATIONAL|SEQUENTIAL|DIGITALCIRCUITS|TESTING
PSVLSI 823
Implementation of Sub threshold Adiabatic Logic
for Ultralow-Power Application Sensor Networks
PSVLSI 824
Aging-Aware Reliable Multiplier Design With
Adaptive Hold Logic Signal Processing
PSVLSI 825
Design of Low Leakage Current Average Power
CMOS Current Comparator Using SVL Technique
Analog to Digital
Converter
PSVLSI 826
Low Power Multiplier Architectures Using Vedic
Mathematics in 45nm Technology for High Speed
Computing Digital Multipliers
PSVLSI 827
Implementation of Low Power Flip Flop Design in
Nanometer Regime
Photovoltaic
system
PSVLSI 828
Reduction of Leakage Power & Noise for
DRAM Design Using Sleep Transistor Technique Memory circuits
PSVLSI 829
Implementation of High Performance SRAM Cell
Using Transmission Gate Router
PSVLSI 830
Dynamic Threshold Source Coupled Logic with Push
pull topology for Ultra Low Power Applications Signal Processing
PSVLSI 831
Design of a Low Power 4x4 Multiplier Based on Five
Transistor (5-T) Half Adder, Eight Transistor (8-T)
Full Adder & Two Transistor (2-T) AND Gate
Biomedical
System
PSVLSI 832
Design and Analysis of Approximate Compressors
for Multiplication
DSP
ARCHITECTURE
PSVLSI 833
Design of Area and Power Aware Reduced
Complexity Wallace Tree Multiplier DSP
PSVLSI 834
Design of Full Adder circuit using Double Gate
MOSFET
DSP
ARCHITECTURES
PSVLSI 835
Design of a Compact Reversible Carry Look-Ahead
Adder Using Dynamic Programming Nanotechnology
PSVLSI 836
Energy and Area Efficient Three-Input XOR/XNORs
With Systematic Cell Design Methodology Avionics
PSVLSI 837
Low-Power Clock Distribution Using a Current-
Pulsed Clocked Flip-Flop
Standalone
systems](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
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Pantech vlsi [xilinx ise & spartan fpga] 2016-17
- 1. VLSI Email: vlsi@pantechmail.com [ Xilinx ISE & Spartan FPGA's] www.pantechsolutions.net|www.pantechproed.com 8 | P a g e ©2016 Pantech ProEd Private Limited PROJECT CODE PROJECT THEME APPLICATION TECHNOLOGY | CORE PSVLSI 801 Low Input Resistance CMOS Current Comparator Based on the FVF for Low-Power Applications Analog to Digital Converter 2016 CADENCE MEMORY|ANALOG|DIGITALCIRCUITS PSVLSI 802 Cyclic Combinational Gate Diffusion Input(CCGDI) Technique- A New Approach of Low Power Digital Combinational Circuit Design ALU Design PSVLSI 803 Self-gated resonant-clocked flip-flop optimized for power efficiency and signal integrity Photovoltaic System PSVLSI 804 Reliable Power Gating With NBTI Aging Benefits Photovoltaic PSVLSI 805 Accurate and efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits Photovoltaic PSVLSI 806 Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell Consumer Electronics PSVLSI 807 Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications Router Buffers PSVLSI 808 Sub threshold Level Shifter with Self Controlled Current Limiter by Detecting Output Error Power Management PSVLSI 809 Low-power technique for dynamic comparators Analog to Digital Converter PSVLSI 810 A Modified SRAM Based Low Power Memory Design Router PSVLSI 811 A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications Router PSVLSI 812 Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell Router PSVLSI 813 Accurate and Efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits Power Management PSVLSI 814 Design Methodology for Voltage-Scaled Clock Distribution Networks Standalone systems PSVLSI 815 A Modified Partial Product Generator for Redundant Binary Multipliers Digital Multipliers XILINXISE|MODELSIM REGISTERTRANSFERLOGIC| ARCHITECTUREDESIGN PSVLSI 816 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Level Digital Signal Processing PSVLSI 817 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Digital Multipliers PSVLSI 818 Efficient FPGA-Implementation of Two’s Complement Digit-Serial/Parallel Multipliers Digital Multipliers PSVLSI 819 A CDF based Lifting scheme for the satellite image compression Access Control
- 2. VLSI Email: vlsi@pantechmail.com [ Xilinx ISE & Spartan FPGA's] www.pantechsolutions.net|www.pantechproed.com 9 | P a g e ©2016 Pantech ProEd Private Limited PSVLSI 820 Reversible Data Hiding in Encrypted Image with Distributed Source Encoding Defense PSVLSI 821 An Efficient Hardware Implementation of Canny Edge Detection Algorithm Machine Vision PSVLSI 822 Design & Optimization of FinFET based Schmitt Trigger using Leakage Reduction Techniques Sensor Networks 2015 LOWPOWERDESIGN COMBINATIONAL|SEQUENTIAL|DIGITALCIRCUITS|TESTING PSVLSI 823 Implementation of Sub threshold Adiabatic Logic for Ultralow-Power Application Sensor Networks PSVLSI 824 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic Signal Processing PSVLSI 825 Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique Analog to Digital Converter PSVLSI 826 Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing Digital Multipliers PSVLSI 827 Implementation of Low Power Flip Flop Design in Nanometer Regime Photovoltaic system PSVLSI 828 Reduction of Leakage Power & Noise for DRAM Design Using Sleep Transistor Technique Memory circuits PSVLSI 829 Implementation of High Performance SRAM Cell Using Transmission Gate Router PSVLSI 830 Dynamic Threshold Source Coupled Logic with Push pull topology for Ultra Low Power Applications Signal Processing PSVLSI 831 Design of a Low Power 4x4 Multiplier Based on Five Transistor (5-T) Half Adder, Eight Transistor (8-T) Full Adder & Two Transistor (2-T) AND Gate Biomedical System PSVLSI 832 Design and Analysis of Approximate Compressors for Multiplication DSP ARCHITECTURE PSVLSI 833 Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier DSP PSVLSI 834 Design of Full Adder circuit using Double Gate MOSFET DSP ARCHITECTURES PSVLSI 835 Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming Nanotechnology PSVLSI 836 Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology Avionics PSVLSI 837 Low-Power Clock Distribution Using a Current- Pulsed Clocked Flip-Flop Standalone systems
- 3. VLSI Email: vlsi@pantechmail.com [ Xilinx ISE & Spartan FPGA's] www.pantechsolutions.net|www.pantechproed.com 10 | P a g e ©2016 Pantech ProEd Private Limited PSVLSI 838 A Low-Power Architecture for the Design of a One- Dimensional Median Filter Edge Preserving PSVLSI 839 Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications Tele- communication 2015 XILINXISE|MODELSIM REGISTERTRANSFERLOGIC|ARCHITECTURE DESIGN PSVLSI 840 High speed 16-bit digital Vedic multiplier using FPGA DSP PSVLSI 841 Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform Radar PSVLSI 842 Analysis of ternary multiplier using booth encoding technique Signal Processing PSVLSI 843 A New Gate for Low Cost Design of All-optical Reversible Logic Circuit Quantum Computing PSVLSI 844 On the Analysis of Reversible Booth’s Multiplier Quantum Computing PSVLSI 845 Parity Preserving Adder/Subtractor using a Novel Reversible Gate Quantum Computing PSVLSI 846 Median Filtered Image Quality Enhancement and Anti-Forensics via Variation DE convolution Computer Vision 2015 IMAGEPROCESSING FEATUREEXTRACTION|BIOMETRICRECOGNITION PSVLSI 847 Comparisons of Robert, Prewitt, Sobel operator based edge detection methods for real time uses on FPGA Machine Vision PSVLSI 848 Multifocus Image Fusion Based on NSCT and Focused Area Detection Remote Sensing PSVLSI 849 Semantic image compression based on data hiding Defense PSVLSI 850 Iris Image Compression using Wavelets Transform Coding Satellite imagery PSVLSI 851 Shape analysis of decisive objects from an image Using Mathematical Morphology Computer Vision PSVLSI 852 Reversible Image Data Hiding with Contrast Enhancement Defense PSVLSI 853 Leaf Shape Extraction For Plant Classification Optical Character PSVLSI 854 Image segmentation framework based on multiple feature spaces Computer Vision PSVLSI 855 Reconfigurable Architecture of Adaptive Median Filter – An FPGA Based Approach for Impulse Noise Suppression Computer Vision
- 4. VLSI Email: vlsi@pantechmail.com [ Xilinx ISE & Spartan FPGA's] www.pantechsolutions.net|www.pantechproed.com 11 | P a g e ©2016 Pantech ProEd Private Limited PSVLSI 856 Hardware Implementation of Digital Watermarking System for Real Time Captured Image Transmitting Broadcast Monitoring PSVLSI 857 An Efficient Algorithm For Boundary Detection Computer Vision PSVLSI 858 Rapid Heterogeneous Prototyping from Simulink Defense PSVLSI 859 Aware and Smart Member Card: RFID and License Plate Recognition Systems Integrated Applications at Parking Guidance in Shopping Mall Shopping Malls PSVLSI 860 Microcontroller Based Self Sustaining Automatic Traffic Light Control Using Speed Breaker Traffic