This document discusses hard disk interfaces, specifically the Enhanced Small Device Interface (ESDI) and the AT Attachment (ATA) interface, commonly known as IDE. ESDI was developed in 1983 as an intelligent successor to the ST412/506 interface. It integrated the data separator onto the drive itself rather than a separate controller. An ESDI controller could pass complete commands to the drive for decoding and execution. The ATA/IDE interface was developed in the mid-1980s as a lower-cost alternative that integrated the controller directly onto the drive. It uses a simple 40-pin interface and cable to connect up to two drives to the system. The interface presents the drives to the operating system like conventional

1. r
Chapter 3] . Hard Disk Drives
883
wires between the plug in the middle and the end of the cable (s
drives) do exist. But, "~1:1-~ n bDUl Is designed for a transfer rate of up to 24 Mbits/s between drive and controller; typically
select 3 and drive select 4 are not used, so you may 10-15 Mbits/s are achieved. ESDI hard disks use the RLL method for data encoding. Further-
more, an ESDI controller is Intended for connecting up to seven ESDI drives, and may access
Of all hard disk interfaces used on the PC, the ST412/506 Is the least «intelligent». It is a pure ^ard disks with a maximum of 64 heads In four groups of 16 heads each, as well as a maximum
signal Interface, thus the controller Is unable to pass any command to the drive. The drive Itself of 4096 cylinders. The controller of Its predecessor Interface (ST412/506), on the other hand,
accommodates only the control circuitry for stabilizing the disk rotation and the head position- allowed a maximum of only 16 heads and 1024 cylinders.
ing. All other control functions are carried out by the controller Itself, for example, Interpretation
of the commands from the PC system, the encoding and decoding of the read and write data, An ESDI controller may also pass complete commands which are decoded and executed by the
the generation of address marks, etc. drive. On the other hand, the generation of address marks, synchronization pattern and the
decoding of the NRZ into parallel bit data for the PC system bus are carried out by the control-
ST412/506 controllers and drives were used first in the XT, and later also in the AT. Because the ler. Thus an ESDI controller Is neither a pure controller which takes over all control functions,
XT BIOS was not designed as standard for the support of hard disks, all XT controllers must nor a host adapter which solely establishes a connection to the system bus; instead, it Is some-
have their own BIOS with the hard disk functions of INT 13h. The start address of this BIOS thing like an intermediate product between controller and host adapter. ESDI signals and ESDI
extension Is usually c8000h. The AT, on the other hand, supported hard disks from the first day, commands will not be discussed here because the interface Is already outdated.
and the required routines are already Implemented In the system BIOS at address fOOOOh. But For the connection of ESDI hard disks, in principle the same rules as for an ST412/506 drive
there are other differences between XT and AT controllers with an ST412/506 Interface: apply. First you must configure the drives, that Is, adjust their ESDI address. Because of the
different uses of the cable wires and the binary encoding of the drive address on the control
- The XT controller uses DMA channel 3 for transferring data between sector buffer and main
cable, no cables with twisted wires are available for ESDI to free you from this drive configu-
memory; In the AT, on the other hand, the BIOS carries out a programmed I/O by means
of the port instructions IN and OUT without using any DMA channel ration. With ESDI you always need to assign every drive an ESDI address. However, It Is not
significant here which plug of the control cable you connect with which ESDI drive.
- The XT controller employs IRQ5 for Issuing a hardware interrupt; the AT controller IRQ14.
- The XT controller is accessed via the XT task file, the AT controller via the AT task file; the
register assignment and addresses of these +™m t-^v &~~ _..«vucx via me AI tasK tile;
_ ----
icgwiei assignment and addresses of these two task files are Incompatible; drivers for XT 31.6 Drives with IDE, AT Bus or ATA Interface
hard disk controllers with an ST412/506 interface cannot be used for an AT controller.
The commands for an XT controller always consist of a 6-byte command block to a single Recently, a new hard disk interface standard was established for PCs which is overtaking the
register; several -—^^^x, on the other is programmed by means of single command
bytes to the AT controller, registers. hand, k r»rr»n-^~™-j *-
individual ST412/506 standard more and more: the so-called IDE or AT bus interface. IDE Is the abbrevia-
tion for intelligent drive electronics ~ an Indication that the connected drives are intelligent on
their own. With the conventional controller-hard disk combination, the drive itself has only
Connecting and Confii those electronic elements required to drive the motors and gates of the drive. The more exten-
luring ST412/506 Hard Disk Drives
sive control for executing commands (for reading a sector, for example, a head seek, the reading
The of the encoded signals, the separation of data and clock signal, the transfer into main memory,
etc. must be carried out) Is taken over by the electronic equipment on a separate adapter, that
the control cable, an eventual second h d di kto h ^ ** ^ ** t0 *" ™ d ° f is, the hard disk controller. Thus the drive itself is rather «stupid». A further disadvantage of
a control cable without twisted w^ Aen on T"**" " ** ^ ff >™ a r e u s i n § this solution Is that the still encoded signals must run from the drive via the data cable to the
drive select 1 by m e a n s o f t h e ^ s o ^ d l ^ * G M *** 8ekct ° a n d * * * D : a s controller to be decoded there. The transfer path worsens the signals; a high data transfer rate
cable with twisted wires then y o u Z c o t f ' T ^ * * ^3S " y ° U a r e U s i n § a «>"** between drive and controller falls because of the relatively long signal paths. Further, the ex-
for floppy drive, B e c a u s e ^ Sof^l l eT e ^c t^ ^
t s Ie
*** "** h as JL the case ploding market for hard disk drives gave rise to a nearly infinite variety of drive geometries and
enabled. exchange signals, the intended disk is always storage capacities, so that a separate controller (which possibly comes from a third-party manu-
facturer) Is simply overtaxed to serve all hard disk formats.
3 1 ! 3 The ESDI int@ The falling prices for electronic equipment during the past few years, in parallel with a remark-
able performance enhancement, gave a simple solution: modern and powerful hard disk drives
already integrate the controller, and It Is no longer formed by a separate adapter card. The
ESDI was conceived by Maxtor In 1983 as a powerful and intelligent successor to the ST412/506
signal paths from disk to controller are thus very short, and the controller can be adapted In an
interface. The main problem of the long transfer distances between hard disk and data separ-
optimized way to the hard disk It actually controls. The IDE and SCSI Interfaces follow this
ator was solved, In that ESDI already Integrates the data separator on the drive.
I of integrating drive and controller into a single unit. But SCSI has another philosophy

2. 884 Chapter; f 885
In other aspects; details concerning SCSI are discussed in the next chapter. ESDI, as a midcj,
course, integrates the data separator on the drive but the rest of the controller (for example, f| bus. To the system and you as a programmer, the AT bus drives appear to be the usual con-
sector buffer and drive control) Is still formed on a separate adapter. trollers and drives with an ST412/506 interface which had been operating in your PC up to now.
Thus AT bus drives can be accessed by the routines of INT 13h implemented in the conventional
The IDE Interface (discussed In the following sections) lies, In view of its performance, betweer AT BIOS. Unlike ESDI or SCSI hard disk drives, no BIOS extension is required.
the conventional solution with a separate controller and an ST412/506 interface to the drive oi For connecting the drives, only a single 40-wire flat conductor cable is used, with which you
the one side, and the SCSI and ESDI hard disks as high-end solutions on the other.
connect the host adapter and the drives. The IDE interface can serve a maximum of two drives,
AT the end of 1984, Compaq Initiated the development of the IDE Interface. Compaq ws a-
one of which must be the master, and the other the slave (adjust the jumper or DIP switch
looking for an ST506 controller which could be directly mounted onto the drive and connected
accordingly). The master drive is assigned address 0, the slave address 1. Table 31.10 lists the
to the main system by means of simple circuitry. In common with hard disk manufacturers sucli
as Western Digital, Imprimis and Seagate, the AT bus Interface arose In a very short time. T o assignment of the 40 wires and the signals running on them.
o
many cooks spoil the broth, and so in the beginning Incompatibilities were present everywhere, - pin 20 of the cable Is locked to avoid a mlsinsertion of the plug. Most of the 40 IDE lines are
To take remedial action several system, drive and software manufacturers founded an interest grounded or can be directly connected to the AT system bus. This explains the name AT bus
group called CAM (common access method), which elaborated a standard with the name A A T interface. Between host adapter and IDE drive there are only five signals, CSlFx, C83Fx,
(AT attachment) In March 1989. Besides other properties, the command set for IDE drives was SPSYNC, DASP and PDIAG, which control the IDE drives and are not connected to the AT
also defined. As well as the 8 commands with several subcommands already present on the bus. The two first signals CSlFx and CS3Fx are chip select signals generated by the host adapter
AT controller, 19 new commands were added, which mainly refer to the drive control in view to select the register group with the base address If Oh or the register group with the base
of low power consumption. For example, the sleep command for disabling the controller and
address 3f0h. The meaning of the accompanying registers is described below.
switching off the drive If no access has been carried out for a while Is one of these. Appendix
With the spindle synchronization signal SPSYNC the spindle motor rotation of master and slave
H lists all the necessary and optional commands. Today, all manufacturers orient to this speci-
can be synchronized. This Is advantageous If, for example, drive arrays are formed or a mirror-
fication, so that Incompatibilities are (nearly) a thing of the past. You may use the terms AT bus, '
IDE and ATA synonymously. An extension to the standard with a higher transfer rate, and also ing is carried out. But many IDE drives don't Implement this, and the SPSYNC pin Is not used.
to drives with removable mediums (especially CD-ROM), Is presently in preparation, and will •• The two signals DASP (drive active/slave present) and PDIAG (passed diagnostic) return ac-
be called Enhanced IDE; this seems to be a response to the triumph of SCSI However, more knowledge signals by the slave to the master during the course of Initialization. Also, these
flexibility and higher performance aren't at all bad for IDE either. signals are not implemented in many older IDE models manufactured before trie ATA standard
became effective. That's not very serious; only some diagnostics routines are not always ex-
ecuted correctly. If your diagnostics software reports-some obscure errors, although your drives
'sical CPU-Drive interface
have been running error-free for several months, then the reason may be the lack of one or both
signals.
IDE is a further development of the AT controller with an ST506 Interface so that the AT bus -
hard disks orient to the register set and the performance of such hard disks. Thus, IDE is a An optional but, nevertheless, important signal Is IORDY. With a low level a drive can inform
logical interface between system and hard disk, and accepts high-level commands (for example, the CPU that it requires additional clock cycles for the current I/O cycle, for example, for
read sector or format track). ESDI and ST412/506, on the other hand, are physical interfaces - reading the sector buffer or transferring the command code. The CPU then inserts wait states.
between controller and drive and refer, for example, to the control signals for the drive motors But many IDE drives don't use this signal, and always fix the corresponding line at a high level
to move the head to a certain track. As with IDE the controller and hard disk form an insepa- For performance enhancement the IDE standard defines two more signals, which were not to
rable unit, it is the job of every manufacturer to design the control of the drive and the transfer be found on an ST506 controller In the original AT: DMARQ (DMA request) and DMACK
of the data. The definition of a physical Interface Is therefore obsolete. (DMA acknowledge). In the AT, the data exchange between main memory and the controller's
sector buffer was not carried out via a DMA channel, as was the case on the PC/XT, but by
The physical connection between the AT bus in the PC and the IDE Interface of the drives (or means of the CPU; a so-called programmed I/O (PIO) Is executed. If, for example, a sector is to
better, the controllers on the drives) Is established by a so-called host adapter. The motherboard be read, then the sector data read Into the sector buffer Is repeatedly transferred via the data
plays the role of host here. The host adapter accommodates only a few buffers and decoder register into a CPU register by an IN instruction, and from there into main memory by a MOV
circuits, which are required to connect the IDE drives and the AT system bus. Newer mother-
instruction, until the sector buffer is empty. Thus the AT controller didn't carry out a DMA
boards already Integrate these host adapters, otherwise they need a separate adapter card which
transfer, and therefore didn't provide any DMA control signals. As with modern and powerful
Is Inserted Into a bus slot. Many host adapters further have a floppy controller so that they are
DMA chips, the transfer rate between sector buffer and main memory Is much higher (a factor
often called an AT bus controller. That's not correct as the controller is located Immediately on
°f two can readily be achieved) and the development of multitasking systems like OS/2 request
the board of the drive; the adapter only establishes the connection between the drive and system a
relief from such «silly» data transfer operations, the two optional DMA control signals are

3. 887
Chapter] Hard Disk Drives
IDE signal pjn
Signal meaning implemented in the new IDE standard. Some AT bus hard disks can be instructed by a software
AT signal Signal
direction
command or a jumper to use a DMA channel instead of PIO for exchanging data between sector
RESET 1 reset drives buffer and main memory. But as the programmer, you must then take into account the prepar-
GND 2 ground RESET DRV1) host~»drive
DD7 3 ations for carrying out such a DMA transfer.
data bus bit 7
DD8 4 SD7
data bus bit 8 bidirectional The integration of the controllers on the drives makes it possible to integrate more intelligence
DD6 5 SD8
data bus bit 6 bidirectional
DD9 6 SD6 into the hard disk control To this belongs, for example, intelligent retries if an access has failed.
data bus bit 9 bidirectional
DD5 7 SD9 It is especially important that many IDE drives carry out an automatic bad-sector remapping.
data bus bit 5 bidirectional
DD10 SD5 Usually, you can mask defective sectors and cylinders during the course of a low-level format-
data bus bit 10 bidirectional
DD4
data bus bit 4 SD10
bidirectional ting process via the defect list, and use error-free alternative sectors and tracks instead. But if,
DD11 10 data bus bit 11 SD4
bidirectional after such a low-level formatting, a sector or track is damaged, the mapping is no longer pos-
DD3 11 data bus bit 3 SD11
bidirectional
DD12 12 data bus bit 12 SD3
bidirectional
sible and the sector is lost for data recording. This becomes fiendish, especially in the case of
DD2 13 data bus bit 2 SD12 sneaking damage. The controller then always needs more retries to access the sector concerned
bidirectional
DD13 14 data bus bit 13 SD2 correctly. Using the in-built retry routine, the operating system seldom recognizes anything
bidirectional
DD1 l
* 15 data bus bit 1 SD13
bidirectional about this as the data is read or written correctly after several retries. But at some time the point
DD14 16 data bus bit 14 SD1
bidirectional is reached where even the retry routine is overtaxed, the sector is completely inaccessible, and
DDO 17 SD14
data bus bit 0 bidirectional
DD15 18 data bus bit 15 SDO bidirectional
all data is lost. Many IDE drives are much more clever: the controller reserves several sectors
GND2) 19 SD15 and tracks of the hard disk for later use during the course of bad-sector remapping. If the
ground bidirectional
20 pin 20 mark controller detects several failed accesses to a sector, but finally leads to a correct data access,
DMAQ 3) 21 DMA request then the data of the sector concerned is written into one of the reserved spare sectors and the
GND_ 22 ground DRQx drive->host
DiOW 23 bad sector is marked. Afterwards, the controller updates an internal table so that all future
write data via I/O channel
GND 24 ground
IOW host—>drive accesses to the damaged sector are diverted to the reserved one. The system, or you as its user,
DIOR 25 doesn't recognize this procedure. The IDE drive carries out this remapping without any inter-
read data via I/O channel
GND 26 IOR
IORDY3)
ground host-»d rive vention, in the background.
27
I/O access complete (ready)
28 IOCHRDY drive-^host The emergence of battery-powered laptops and notebooks gave rise to the need for power-
spindle synchronization
DMACK 3) 29
DMA acknowledge drive-»drive saving drives. In a computer, powerful hard disks are one of the most power-consuming com-
GND 30 DACKx
ground host-^drive ponents, as they require strong current pulses for fast head seeks, and unlike floppy drives the
!NTRQ_ 31
IOCS16
interrupt request [RQx_ hard disks are continuously running. Most specialist drives for portable computers can be
32 cfrive-»host
DA1_ 33 16 bit transfer via I/O channel I/OCS16 switched off or disabled by software commands to minimize power consumption. Also, for the
address bus 1 drive-»host
PDIAG 34 SA1 IDE hard disks according to the ATA standard such commands are optionally implemented. In
passed diagnostic from slave host-^d rive
DAO 35
address bus 0 drive-»drive the order of decreasing power consumption such hard disks can be operated in the active, idle,
DA2__ 36 SAO
address bus 2 host—xdrive standby and sleep modes. Of course, it takes the longest time to «awaken» a drive from sleep
CS|Fx 37 SA2
chip select for base addr. 1fOh host-»drive
CS3Fx 38 into the active state. For this purpose the disk has to be accelerated from rest to the operation
chip select for base addr. 3f0h host-^drive
DASP 39
host-xirive rpm, the head must be positioned, and the controller needs to be enabled.
GND
drive active/slave present
40
ground drive-»host
1)
inverted signal of AT bus signal 3162 Features of IDE Hard Disk Drives
2)
pin locked to prevent incorrect insertion of plug
3)
optional
Intelligent drives with an embedded controller, the most powerful among all IDE hard disks,
carry out a translation from logical to physical geometry. The high recording density allows
drives with up to 50 sectors per track in the outer zone with a large radius. IDE hard disks run
virtually exclusively with an interleave of 1:1. To reduce the average access time of the drives,
some hard disks are equipped with a cache memory which accommodates at least two tracks,
*rt most cases. Even If your PC is unable to stand an interleave value of 1:1 as the transfer via
the slowly clocked AT bus Is not fast enough, this is not a disaster. Because of the 1:1 interleave,

4. 889
the data is read very quickly Into the controller cache which Is acting as a buffer. The Q
fetches the data from the cache with the maximum transfer speed of the AT bus. An Interim Address Width Reac
value which is adjusted too low, therefore, has no unfavourable consequences as It would d Register
Write(W)
without the cache. [bit]
1fOh 16 R/W
data register
1f1h 8 R
For high-capacity IDE hard disks, the RLL encoding method Is mainly used; simpler ones % error register
1f1h 8 W
precompensation
also use the MFM method. High performance IDE drives enable data transfer rates betwee 1f2h 8 R/W
sector count
drive and main memory of up to 5 Mbytes/s; a value which comes near the top of the practice 1f3h 8 R/W
sector number
1f4h 8 R/W
values of SCSI On average, transfer rates of more than 3 Mbytes/s are realistic for usual IQ- finder LSB
1f5h 8 R/W
drlves. Thus they are located between the older ST412/506 controllers and the high-end S S" C; cylinder MSB
R/W
drive/head 1f6h 8
solutions. The simpler Interface electronics of the IDE host adapter and the support of the A] 1f7h 8 R
status register
bus drives by the AT's en-board BIOS make It appear that the IDE hard disks are a rather good' command register 1f7h 8 W
solution for personal computers in the region of medium performance. alternate status register 3f6h 8 R
An IDE Interface manages a maximum of two drives. As long as the connected drive meets the digital output register 3f6h 8 W
drive address 3f7h 8 R
IDE Interface specification, the internal structure of the drive Is insignificant. For example, it is
possible to connect a powerful optical drive by means of an IDE interface. Usually, one would Table 31.11: The AT task file
select an SCSI solution as this is more flexible In a number of ways than the AT bus.
One restriction of IDE Is the maximum cable length of 187/ (46 cm); some manufacturers also
allow up to 247/ (61 cm). For larger systems which occupy several cabinets, this Is too little, but 7 6 5 4 3 2 1 0
JABT
|NTO
O Q
BBK
for a personal computer even In a large tower case It is sufficient. These values are part of the Z
IDE standard. Thus, it is not Impossible that the cables may be longer; but the IDE standard
does not guarantee this. BBK: 1 =sector marked as bad by host 0=no error
UNC: 1 =uncorrectable data error 0=no or correctable data error
NID: 1=ID mark not found 0=no error
The AT File ABT: command abort
1 =command aborted 0=command executed
NTO: 1 =track 0 not found 0=no error
The CPU accesses the controller of the IDE hard disk by means of several data and control HUM: 1 =data address mark not found 0=no error
registers, commonly called the AT task file. The address and assignment of these registers is x: unused
identical to that of the hard disk controller with an ST506 interface In the IBM AT, but note that
the registers are not compatible with the XT task file, or other Interfaces such as ESDI or SCSI. Enhanced IDE only:
0=medium not changed
The AT task file is divided into two register groups with port base addresses ifOh and 3f0h. The MC: 1=medium changed
MCR: 1 =medium change required 0=no medium change required
following sections describe the registers of the AT task file and their meaning in more detail
Table 81.11 lists all the registers concerned.
Figure 31.16: Error register (Iflh).
The data register, which Is the only 16-bit register of the AT task file, can be read or written by
the CPU to transfer data between main memory and the controller. The original AT interface A set NDM bit indicates that the controller hasn't found a data address mark on the data carrier.
supported only programmed Input/output via registers and ports, but no data transfer by If NTO is set this means that after a corresponding command the drive was unable to position
means of DMA. The reading and writing Is carried out In units of 16 bits; only the ECC bytes the read/write head above track 0. If the controller had to abort execution of the active com-
during the course of a read-long command are passed byte by byte. In this case, you must use mand because of an error, the ABT bit is set. If the MD bit is equal to 1 the c o n t r o l wa
the low-order byte of the register. Note that the data in the data register is only valid if the DRQ unable to detect the ID address mark concerned on the data carrier. A set UNC bit shows that
bit In the status register Is set.
an uncorrectable data error has occurred; the data is invalid even after applying the ECC code^
If BBK is equal to 1 then the CPU has earlier marked the sector concerned as bad; it can no
The CPU can only read the error register; It contains error information concerning the last active longer be accessed.
command If the ERR bit In the status register Is set and the BSY bit In the status register Is
cleared; otherwise, the entries In the error register are not defined. Note that the meaning of this For supporting drives with removable volumes, enhanced IDE implements the (formerly
register differs for the diagnostics command. Figure 31.16 shows the structure of the error register. reserved) MC and MCR bits. A set MC bit indicates that the volume in the, dnve has been
changed, thus it corresponds to the disk change bit of the floppies. A set MCR bit shows that

5. 390
Chapters nard Disk Drives 891
the user has requested a medium change/ for example, by operating the eject key. The system
must complete all running accesses and send a pulse or command to the drive actually to ejec
the volume. 7 6 5 4 3
co
2
CM
1 0
o
1 L 1 a
a Q X Q
Q x X X
The precompensation register (l£lh) is only implemented for compatibility reasons with the AT
task file of the original AT. All data passed by the CPU is ignored. The IDE hard disk drives
oRV: drive
with an embedded controller process the precompensation Internally without any Intervention 1 =slave 0=masler
by the CPU. HD3-HD0: head number (binary)
0000=head0 0QQ1=head1 0010=head2 1111=head 15
The sector count register (If2h) can be read and written by the CPU to define the number of
sectors to be read, written or verified. If you pass the register a value of 0, then the hard disk Enhanced IDE only:
carries out the command concerned for 256 sectors, and not for 0 sectors. After every transfer L: 1=LBAmode 0=CHS mode
of a sector from or Into main memory, the register value is decreased by one. Thus the register's
contents, which can be read by an IN instruction, indicate the number of sectors still to be read, Figure 3117: Drive/head register (If6h).
written or verified. Also, during the course of a formatting process, the controller decrements
the register value. Note that the meaning of the register differs somewhat for the command set the register Is updated to carry out handshaking. If the CPU reads the status register an even-
drive parameters. tually pending interrupt request (via IRQ14 in the PC) is cancelled automatically. Note that all
bits of this register except BSY and all registers of the AT task file are Invalid if the BSY bit is
The sector number register (If3h) specifies the start sector for carrying out a command with disk set in the status register. Figure 31.18 shows the structure of the register.
access. After processing every sector the register contents are updated according to the executed
command. Thus the register always indicates the last processed sector Independently of whether
the controller was able to complete the concerned command successfully or not. 7 6 5 4 3 2 10
The two registers cylinder MSB (If5h) and cylinder LSB (If4h) contain the most-significant
(MSB) and least-significant byte (LSB) of the 10-bit cylinder number. The two most-significant
bits are held by the register cylinder MSB, the eight least-significant ones by the register cylinder BSY: busy
LSB. The six high-order bits of register cylinder MSB are Ignored, thus the registers are able to 1 =drive is busy 0=drive not busy
represent cylinder numbers between 0 and 1023, as Is also the case for the original AT. Because RDY: ready
many IDE hard disks carry out a translation, the physical cylinders of the hard disk are not 1 =drive is ready 0=drive not ready
WFT: write fault
limited to this range. The physical drive geometry Is then converted into a logical one, which 1= write fault 0=no write fault
has a maximum cylinder number of 1023. After processing of each sector, the contents of both SKC: head positioning (seek)
registers are updated, thus the registers always indicate the current cylinder number. Some IDE 1 =complete 0=in progress
drives, and especially hard disks corresponding to the enhanced IDE standard, also use the six DRQ: data
high-order bits in the MSB cylinder register If5h. Therefore, a total of 65 535 cylinders can be 1 =can be transferred 0=no data access possible
CORR: correctable data error
addressed at the most. 1 =data error 0=not data error
IDX: disk index
By means of the registers drive/head (If6h) you can determine the drive for which the com- 1 =disk index has just passed 0=disk index did not pass
mand concerned Is to be carried out. Furthermore, head defines the start head with which the ERR: error
disk access begins. Figure 31.17 shows the format of this register. 1=error register contains error information
O=error register does not contain error information
The three most-significant bits always have value of 101b. The DRV bit defines the addressed
drive, and the bits HD3-HD0 specify the number of that head with which the command con- %wre 3118: Status register (If7h).
cerned starts to execute. A maximum of 16 heads can therefore be accessed. IDE drives which
can carry out a logical block addressing (LBA), additionally Implement the L bit. If L equals 1/ ^he BSY bit is set by the drive to indicate that it Is currently executing a command. If BSY is
LBA Is enabled for the present access. se
t then no registers may be accessed except the digital output register. In most cases you get
The status register (If7h) can only be read by the CPU, and contains status information concerning any Invalid information; under some circumstances-you disturb the execution of the active
c
the last active command. The controller updates the status register after every command, or tf °namand. A set RDY bit shows that the drive has reached the operation rpm value and Is ready
to
an error occurs. Also, during the course of a data transfer between main memory and controller/ accept commands. If the revolution variations of the spindle motor are beyond the tolerable
ra
nge, for example because of an insufficient supply voltage, then the controller sets the RDY

6. 892
Chapters
T
-ard Disk Drives 893
bit to 0= A set WFT bit indicates that the controller has detected a write fault. If the SKC bit -
equal to 1, then the drive has completed the explicit or implicit head positioning. The drir 7 3 2 1 0
I I I I
IEN
te
clears the SXC bit immediately before a head seek. A set DRO bit shows that the data resist**
is ready for outputting or accepting data. If DRQ is equal to 0 then you may neither read dah
X X X X X
w
X
1
from the data register nor write data into it. The controller sets the CORK bit to inform the C UP
that it has corrected data by means of the ECC bytes. Note that this error condition doesn't abort SRST: system reset
1=reset all connected drives 0=accept command
the reading of several sectors- Upon the passage of the track beginning below the read/write
i i i ' •• interrupt enable
'
head of the drive, the controller sets the IDX bit for a short time. If the ERR bit is set, the error 1=!RQ14 always masked O=interrupt after every command
register contains additional error information.
figure 31.19: Digital output register (3f6h).
The command register (If7h) passes command codes; the CPU is only able to write to it. The
command register is located at the same port address as the read-only status register. The If you set the SRST bit you issue a reset for all connected drives. The reset state remains active
original AT has eight commands in total with several variations. The new IDE standard addi- until the bit is equal to 1. Once you clear the SRST bit again, the reset drives can accept a
tionally defines some optional commands, but I want to restrict the discussion to the requested command. With the IEN bit you control the interrupt requests of the drives to the CPU. If IEN
command set which is already implemented on the IBM AT. The execution of a command starts is cleared (that is, equal to 0) then an interrupt is issued via IRQ14 after every command carried
immediately after you have written the command byte into the command register. Thus you
out for one sector, or in advance of entering the result phase. If you set IEN to 1 then IRQ14
have to pass all other required data to the corresponding registers before you start the command
is always masked and the drives are unable to issue an interrupt. In this case, the CPU may only
execution by writing the command byte.
supervise the controller by polling.
Table 31.12 lists the requested IDE commands as well as the parameter registers that you must With the read-only drive address register (3f7h) you may determine which drive and which
prepare for the corresponding commands. head are currently active and selected. Figure 31.20 shows the structure of this register.
Command SC CY DR HD 7 6 5 4 3 2 1 0
| HS1
calibrate drive
| DSO
| HSO
I %
JHS3
|DSI
X
|HS2
XX
read sector XX XX XX XX XX
write sector XX XX XX XX XX
verify sector XX XX WTGT: write gate
XX XX XX
format track 1 =write gate closed 0=write gate open
XX XX XX
seek head HS3-HS0: currently active head as 1 'complement
XX XX XX
diagnostics DS1, DSO: currently selected drive
set drive parameters XX
XX
SC: sector count SN: sector number
figure 31.20: Drive address register (3f7h).
CY: cylinder MSB and LSB
DR: drive (in register drive/head)
HD: head (in register drive/head)
If the WTGT bit is cleared (that is, equal to 0), the write gate of the controller is open and the read/
xx: parameter necessary for corresponding command
write head is currently writing data onto disk. The bits HS3-HS0 indicate the currently active
head as 1' complement. Similarly, the bits DS1 and DSO determine the currently selected drive.
31.6.4 IDE Interface Programming and Command Phases
The programming and execution of the commands for an IDE interface proceed similar to a
floppy controller or other hard disk interface in three phases:
- Command phase: the CPU prepares the parameter registers and passes the command code
* * * > * *e CPU is only to start the execution.
C ntroller/S
"31.19. ° behaviour; its structure is shown in Figure "• Data phase: for commands involving disk access, the drive positions the read/write heads
"
and eventually transfers the data between main memory and hard disk.

7. 895
j3rd Disk Drives
- Result phase: the controller provides status information for the executed command in,
corresponding registers, and issues a hardware interrupt via IRQ14 (corresponding top
76h). "
Number of Sectors to Write
The controller's command and register are written and read by the CPU via ports, but uij. Sector Count (1f2h)
Sector Number (1f3h)
the PC/XT, the IBM AT and all compatibles don't use the DMA controller for transferring £ Cylinder LSB (1f4h)
sector and format data between main memory and controller. Instead, this data transfer is at Cylinder MSB (1f5h)
1 DRV HD3 HD2JHD1HD0
carried out by programmed I/O via CPU and data register. This means that the CPU writes sect
and format data into or reads them from the data register in units of 16 bits. Only the ECCbyfc.
are read and written in 8-bit portions via the low-order byte of the data register. To synchronize
CPU and controller for a data exchange, the controller issues a hardware interrupt at various long
0=without ECC bytes
=with ECC bytes
times via IRQ14:
retry
1 =carry out retry procedure 0=no retry procedure
- Read sector: the controller always enables IRQ14 when the CPU is able to read a sector.: sector count: number of sectors to be written onto disk
eventually together with the ECC bytes, from the sector buffer. Unlike all other commands, -. sector number (start sector)
this command doesn't issue an interrupt at the beginning of the result phase, thus tk • cylinder number (start cylinder)
number of hardware interrupts is the same as the number of read sectors. drive
1=drive1 0=drive 0
- Write sector: the controller always activates IRQ14 when it expects sector data from the C U I
P, head
1111=head15
Note that the first sector is transferred immediately after issuing the command, and t e j h
controller doesn't issue an interrupt for this purpose. Furthermore, the controller activates,
Yipire 31.21: Write sector command.
via IRQ14, a hardware interrupt at the beginning of the result phase. Thus the number of
hardware interrupts coincides with the number of written sectors.
bytes internally and writes them, together with trie data bytes, onto disk. Trie R bit controls the
- All other commands: the controller issues a hardware interrupt via IRQ14 at the beginning internal retry logic of the controller. If R is set, then the controller carries out an in-built retry
of the result phase.
procedure if it detects a data or address error during the course of the command execution. Only
The interrupt handler for INT 76h corresponding to IRQ14 in the PC must therefore be able to if these retries are also unsuccessful does the controller abort the command and return an error
determine whether the controller wants to output data, is expecting it or whether an interrupt code. If R is cleared, the controller aborts the command Immediately without any retry if an
has occurred which indicates the beginning of a result phase. If you intend to program such a error has occurred.
handler, use the status and error register to determine the interrupt source. The IRQ14 controller With sector count you may determine the number of sectors to be written onto disk. Possible
is disabled as soon as the CPU reads the status register (If 7h). If IRQ14 remains active, you must values are between 0 and 255; a value of 0 writes 256 sectors onto disk. The sector numbers
read the status information via the alternate status register (3f6h). S7-So indicate the number of the start sector to be written first. If the number of sectors to write
Note for your programming that the controller of the addressed drive starts command execution is larger than 1, the controller automatically counts up the sector number until It detects the end
immediately after the CPU has written the command code into the command register. Thus you of the track. Afterwards, it proceeds with the next head, and eventually with the next cylinder,
have to. load all necessary parameter registers with the required values before you start com- until all sectors have been written or an error occurs. The values C9-C0 of the cylinder number
mand execution by passing the command code. define trie start cylinder for the write process. The two bits C9 and C8 represent the two most
significant bits of the 10-bit cylinder number. Using DRV you can select one of the two drives,
Appendix H lists all requested controller commands for the IDE interface, and the three optional
commands for identifying the controller as well as reading and writing the sector buffer. As an and with HD3-HD0 trie head of the drive for which the command is to be carried out.
example one command is discussed here in more detail: write four sectors beginning with Immediately after the command byte has been written, the controller starts the command execu-
cylinder 167, head 3, sector 7 with ECC bytes. The format for this command Is shown in Figure tion, that is, the data phase. It sets the BSY bit in the status register to indicate that it has
31.21. decoded the command and prepared the sector buffer for accommodating the 512 data bytes,
as
well as the four ECC bytes. If this is finished, trie controller clears the BSY bit and sets the
If the L bit Is set then the four ECC bytes are also supplied by the CPU and not generated DRQ bit In the status register to inform the CPU that it now expects the sector data. The CPU
internally by the controller. The ECC logic then doesn't carry out an ECC check. For a single first transfers the 512 data bytes word by word, and afterwards the four ECC bytes byte by byte.
sector you therefore have to pass 516 bytes. If L is equal to 0 then this means a normal write K all 516 sector bytes have been passed the controller sets the BSY bit again and clears the DRQ
command. The CPU only passes the 512 data bytes, and the controller generates the four ECC
bit. Now it begins to write the data onto disk.

8. 896
897
Chapter. Hard Disk Drives
If the first sector has been written then the controller Issues an interrupt 76h via IRQ14. int_count++;
handler concerned now transfers the 516 bytes of the following sector data via the data registerJ
if (int_CQunt<4) { /* ignore interrupt at the beginning of result phase*/
to the controller in the same manner as described above. This process is repeated four timej
for (word__count = 0; word_count < 256; word_count++, word_pointer++) {
until all four sectors, together with their ECC bytes, have been written. | outpw(0xlf0# *word_pointer); /* transfer 256 words = 512 data bytes */
Example: Write four sectors starting with, cylinder 167^ head 3^ sector 7 together with E C I
C }
bytes onto master drive (languages Microsoft C 5.10). | for (byte_count = 0; byte_count < 4; byte_count++, byte_pointer++) {
outp(0xlf0# *byte__pointer); /* transfer 4 ECC bytes */
i
unsigned int word_buffer [1024]; |
unsigned char byte_buffer [16]; § return;
unsigned int *word_pointer; | }
unsigned char *byte_pointer; !
int int_count; |
In the example,
the handler for IRQ14 serves only for transferring the data; a more extensive
main () j function, for example for determining the interrupt source, is not implemented. The 2048 data
l;
{ int word_count^ byte_count; bytes in 1024 data words as well as the 16 ECC bytes must be suitably initialized. This is not
void far ^old_irql4;
word_pointer = &word_buf f er; /* initialize */ carried out here because of the lack of space. Furthermore, the procedure status_check() for
byte_pointer = &byte_bu£fer; /* pointer */ checking the status information is not listed in detail
init_buffers();
/* initialize buffer */
old_irql4 = _dos_getvect(0x76); Upon the last interrupt the result phase is entered. Figure 31.22 shows the task file registers that
/* set new interrupt */ contain valid status information after the command has been completed. The entries in the error
_dos_setvect (0x7 6, new_irgl4());
/* for IRQ14 */
while((inp(0xlf7) & 0x80) == 0x80);
register are only valid if the ERR bit in the status register is set and the BSY bit is cleared.
outp(0xlf2, 0x04); /* wait until BSY in status register is cleared */
©utp(0xl£3, 0x07); /* register sector counti 4 sectors */
outp(0x1f4, 0xa7); /* register sector number: 7 */ AT Task File Bit I
Registe 7 | 6 I 5 4 | 3 2 1 u
outp(0xl£5, 0x00); /* register cylinder LSBs 167 */
NDM NTO ABT x NID x UNCBBK 1
outp(Qxl£6^ 0xa3);
outp(0xlf7, 0x33);
/* register cylinder MSB? 0 */
/* register drive/head: DRV=0y head-3 */
/* register commands opcodesOOHOO^ Lsl, R=l */
Error (ifih)
Sector Count (1f2h)
Sector Number (1f3h)
Number of Sectors Written
S7 S6 S5 S4 S3 S 2 Si So
1
1
Cylinder LSB (1f4h) C7 C6 C5 C4 C3 C 2 C1 Co
/* write first sector (512 data bytes
+ 4 ECC bytes */
Cylinder MSB (1f5h) 0 0 0 0 0 0 C 9 c8 1
while ((inp(0xlf7) & 0x80) == 0x80 II
(inp(0xlf7) & 0x08) I =0x08); /* wait until BSY in Drive/Head (1f6h) 1 0 1 DRV HD3 HD2 HD1 HDo 1
status register is cleared and DRQ is set */ (1f7h) 1
BSY RDY WFT SKC DRQ COR IDX ERR
word_pointer = word_buf f er;
for (word_count = 0; word_count < 256; /* initialize pointer */
Status
1
outpw(0xlf0^ *word_pointer); word_count++, word_pointer+ +) {
} /* transfer 256 words = 512 data bytes */ NDM: 1 =data address mark not found 0=no error
NTO: 1=trackO not found 0=no error
byte_pointer = byte_buf f er; ABT: instruction abort
/* initialize pointer */ O=instruction executed
for (byte_count = 0; byte_count < 4; 1 instruction aborted
byte_count+ + ^ byte_pointer-f + ) {
outp(0xlf0, *byte_pointer); NID: 1=ID mark not found 0=no error
} /* transfer 4 ECC bytes */ 0=no or correctable data error
UNC: 1 =not-correctable data error
BBK: 1 =sector marked bad by host 0=no error
int_count=0;
/* initialize interrupt count */ DRV: drive
while (int__count < 4 ) ; 1 =slave 0=master
/* wait until all four sectors are transferred */ C9-C0, S 7 -S 0 , HD 3 -HD 0 : sector identification of last written sector
_dos_setvect(0x7 6, old_irql4());
/* set old IRQ14 #/
status_check();
/* check status information and determine error %wre 32.22: Result phase of «Write Sector» instruction.
code */
exit(0);
} According to the sector Identification, you can determine the last written sector or the sector
w
Mch gave rise to the command abortion. The sector count register specifies the number of
void interrupt far new_irql4()
{ int word_count# byte_count;
sectors still to be written, that is, a value of 0 If the command has been terminated without any
error.

9. 899
-;ard Disk Drives
-ontinuous transfer rates from hard disks, cannot yet be achieved, so there is still a little breath-
jug space In the IDE standard for a few years yet to come.
The main advantage of IDE over SCSI is the very simple structure oT the ';ost adapter for disk
drives using this interface. In fact the host adapter just switches the A i ous of the PC through
to the IDE drive controller. A complicated converting of the signals z he Independent per-
forming of (SCSI) bus cycles, is not necessary. For this reason, IDE adapters and IDE disk drives 31.7 SCSI
for a while, dearly had a price advantage, and so kept their nose in front. Not surprisingly, this
lias changed in the meantime. On the one hand, both SCSI disk drives and SCSI host adapters A very flexible and powerful option for connecting hard disks to a PC Is the SCSI {small computer
have become much better value for money (the price advantage of many IDE boards is purely systems interface). The term Itself Indicates that SCSI is intended for the PC and other small
the result of lower performance and, thus, cheaper drives). On the other hand, the integration systems (for example, workstations or the Mac). However, the characterization of PCs and
of an interface designed for an AT bus into an MCA or local bus system means Increased workstations as «small» has changed, at least as far as MIPS numbers are concerned, since the
.complexity and, therefore, a higher price. So as not to give the advantage to SCSI, the specifi- Pentium has been-on the market. SCSI was derived from the SASI of Shugart Associates (Shugart
cation has been expanded, and the result is enhanced IDE. Associates systems interface). SCSI comes with a somewhat older standard SCSI-1, which Is not
strict enough in some aspects, resulting in compatibility problems when Implementing SCSI-1
Enhanced IDE Is characterized by two essential points: the supporting of disk drives with The new standard SCSI-II determines the properties more precisely, and additionally defines
removable data volume devices; and a higher transfer rate between the host and the disk drive. some more commands and operation modes. SCSI follows a different philosophy to those hard
The former is achieved with a few new Instructions such as medium exchange confirmation disk interfaces already discussed; this section gives more Information on this subject.
(Odbh), secure drive shutter (Odeh), release drive shutter (Odfh), and also the MC and MCR bits
in the cylinder registers (If4h/lf5h). In addition, a high-level protocol Is planned so that the host
adapter can communicate with the disk drive; the SCSI model Is easy to spot. Furthermore, it 31.7.1 SCSI Bus and Connection t© the PC
should be possible to connect more than two disk drives to an IDE adapter. For this, a second
IDE task file Is provided at 170h-177h and 37611-37711, but which should only serve disk drives SCSI defines a bus between a maximum of eight units, as well as the protocol for data exchange
with a removable data volume device. among them. Such SCSI units may be hard disks, tape drives, optical drives, or any other device
that fulfils the SCSI specification. Thus, SCSI drives are intelligent, as are the IDE hard disks; the
The requirement for more performance affects not only the data transfer rate Itself (here, the PIO unit's controller is always Integrated on the drive. For connection to the PC a SCSI host adapter
and DMA modes, If available, prove themselves to be bottlenecks), but also the maximum is required, which establishes the connection to the PC's system bus similar to the IDE Interface.
capacity of the IDE hard disk. The most frequently used (and targeted at AT) CHS procedure The host adapter Itself is also a SCSI unit, so that only seven «free» units remain. Unlike an IDE
for addressing a sector (Cylinder Head Sector) limits the capacity to 504 Mbytes (cylinder 1024, host adapter, the SCSI host adapter Is thus rather complex, as it must recognize all the functions
head 16, sector 63). The IDE standard Itself (that Is, trie layout of the registers), with 255 sectors of the- SCSI bus and be able to carry them out. But the advantage is that SCSI is not limited to
per track and a maximum of 65 536 cylinders, would still permit 127.5 Gbytes. As a solution, the AT bus. There are also host adapters for EISA or the Mac. The enormous data transfer rate
enhanced IDE offers Logical Block Addressing (LBA), similar to SCSI. The disk drive then as well as the high-end performance of the SCSI hard disks doesn't suggest its use in a PC/XT,
appears as a continuous medium with sequential blocks. The quite laborious addressing of data however. With an accordingly adapted host adapter the same SCSI devices can also be inte-
by converting it Into cylinder, head and sector is no longer necessary as the disk drive controller grated into workstations or an Apple. The Mac has a SCSI interface as standard to connect up
accomplishes this automatically. This means no additional workload, because the controller to seven external SCSI devices. Apple thus elegantly bypasses Its lack of flexibility compared
must convert the logical into a physical geometry anyway. To activate LBA for an access, you with the IBM-compatible PCs.
must set the L bit in the disk drive/head register at If6h (Figure 31.17). From the 127.5 Gbyte Thus the SCSI bus serves only for a data exchange among the SCSI units connected to the bus.
maximum capacity of IDE, more than 7.8 Gbytes remain available for use by the BIOS. During A maximum of two units may be active and exchange data at any one time. The data exchange
booting, the BIOS uses the Identify drive instruction to determine the capacity, but can only can be carried out between host adapter and a drive, or (as a special feature of SCSI) also
cope with a maximum of 1024 cylinders (In place of the 65 536 offered by enhanced IDE). Only between two other SCSI devices (for example, a tape drive and a hard disk). It is remarkable that
special drivers can bypass this limitation and allow the full 127.5 Gbytes to be used. this data exchange is carried out without the slightest intervention from the CPU; the SCSI
With enhanced IDE, the transfer rate should be greatly Increased over that possible in current drives are intelligent enough to do this on their own. Figure 31.23 shows a scheme of the SCSI
EISA and local bus systems. For this, a new PIO mode #3 Is provided which should (theoreti- bus in the case of integrating a SCSI into a PC.
cally) perform a transfer in 120 ns. With a 16-bit data bus width to the disk drive, this produces
a maximum transfer rate of 16.6Mbytes/s. The also accelerated DMA block mode #1 transfers Every SCSI unit is assigned a SCSI address, which you can set by a jumper on the drive.
a 16-bit data packet within 150 ns; the transfer rate achieved Is 13.3 Mbytes/s. Both values, as Addresses in the range 0-7 are valid; according to the SCSI standard, address 7 Is reserved for
a
tape drive. The address Is formed by bytes where the least significant bit 0 corresponds to the