VMEbus is a computer architecture. The term VME stands for Vgsj^MtodulejEmocaffd and
was first coined in 1981 by the group of manufacturers who defined itTTFhis group was
composed of people from Motorola, Mostek and Signetics corporations who were
cooperating to define the standard. The term "bus" is a generic term describing a computer
data path, hence the name VMEbus.
VMEbus grew out of ae older standard called VERS Abus which was defined by Motorola
Corporation in 1979 for its 68000 microprocessor. While it is still used today? it has not
achieved the wide acceptance that VMEbus has* VERS Abus initially competed with other
blisses including Multibus™, IBM-PC™, S I B bus, S-100, Q-bus and many others.
The microcomputer bus industry began with the advent of the microprocessor, and in 1981
many busses were showing their age. Most worked well with only one or two types of
microprocessors, had a small addressing range and were rather slow. The VMEbus
architects were charged with defining a new bus that would be microprocessor
independent^ easily upgraded from 16 to 32-bit microprocessors, implement a reliable
mechanical standard^ and allow independent vendors to build compatible products* No
proprietary rights were assigned to the new bus which helped stimulate third party product
development. Anyone can make VMEbus products without royalty fees or licensing*
Since much work was already done on VERSAbus it was used as a framework for the new
bus. In addition^ §LI2££32^ chosen*
Eurocard is a term which loosely describes a family of products based around the DIN
41612 and EC 603-2 connector standards, and the DIN 41494 and IEC 297-3 rack
standards. When VMEbus was first developed, the Eurocard format had been well
established in Europe for several years. A large body of mechanical hardware such as card
cages? connectors and sub-racks were readily available. The pin and socket connector
Chapter 1 - Introduction to VMEbus 1 The VMEbus Handbook
scheme is more resilient to mechanical wear than older printed circuit board edge
connectors. The marriage of the VERSAbus electrical specification and the Eurocard
format resulted in VMEbus Revision A.
The VMEbus specification has since been refined through revisions B9 C, C.1, DEC 821
and IEEE 1014-1987. The DEC and IEEE standards are important because it makes it a
publicly defined specification. Since no proprietary rights are assigned to it, vendors and
users need not worry that their products will become obsolete at the whim of any single
Since its introduction VMEbus has generated thousands of products and attracted hundreds
of manufacturers of boards, mechanical hardware, software, and bus interface chips. It
continues to grow and support diverse applications such as industrial controls,
telecommunications, office automation and instrumentation systems.
1.1 Why Use A Microcomputer Bes?
When developing a system there are three solutions an integrator can choose from: beild it
from scratchy convert a standard computer or use microcomputer boards. The choice is
affected by time to market^ cost, volume, technology s compatibility and sometimes the "we
don't do hardware" mentality. Figure 1-1 shows these trade-offs.
The full custom system is the costliest in terms of development time and money. Its main
advantage is that it can be exactly tailored to an application and can be cheaply produced in
high volumes. It also might be the only choice if no other solution exists. Full custom
might be a poor choice if a simple machine control had to be built in six weeks, but it
would probably be the right choice if thousands of units needed to be built, and a year or
two were available for product development.
Figure 1-1. System integration trade-offs*
Adapting a standard mini or microcomputer is the most cost effective in modest volumes9
Valuable product development resources would be wasted if a standard system could be
Chapter 1 - Introduction to VMEbus The VMEbus Handbook
adapted to the application* The major drawbacks of this approach are inflexibility and high
unit cost. If special functions^ I/O or mechanical packaging are needed, the standard
system might be too inflexible. For example, a personal computer can be adapted to
perform bench top data acquisitioe, but might not be able to handle a sophisticated control
Integration with microcomputer boards is a compromise between custom and standard
systems. They can be pieced together with available parts and minimum tooling costs*
Generally they are used for small and moderate volume applications where 1-1000 units are
built. In many cases it can be done by people with little or no background in electronics.
Another advantage to microcomputer boards is flexibility. At the onset of product
development the requirements of the computer system are only generally known. As a
project progresses more of the application becomes obvious, and the computer architecture
must adjust accordingly. This is especially true of first generation products. As the
product becomes more refined so can the computer architecture* In many cases the
microcomputer bus is the most flexible because standard boards can be substituted in the
1.2 Why ¥MEbus?
Once it is decided to use a microcomputer bus, the choice of which one to use must be
made. There are a wide variety of buses available, with new ones introduced regularly 9
Table 1-1 shows a comparison between VMEbus and some other popular buses. The
choice depends on application, and is affected (again) by time to market, cost, volume,
technology f compatibility and the "we donft do hardware11 mentality.
A few VMEbus features are listed in Table 1-2. VMEbus has a 32-bit address bus (up to 4
gigabytes of memory), a 32-bit data bus? performs multiprocessing and it can smoothly
handle seven interrupt levels. Both the address and data busses can be dynamically
configured (they change size automatically). This allows system expansion as
microcomputer technology grows. It also handles data transfers at speeds in excess of 40
VMEbus uses a master-slave, architecture. Functional modules called masters transfer data
to and from modules called slaves.- Since many masters can reside on the bus it is called a
multiprocessing bus* Before a master cae transfer data it must first acquire the bus using a
central arbiter. This arbiter is part of a module called the system controller. Itfs function is
to determine which master gets the next access to the bus. Seven levels of interrupts are
All bus activity is perfomed by the four sub-busses shown in Figure 1-2. Data transfers
take place over the Data Transfer Bus, and arbitotion by the Data Transfer Arbitration Bus.
If interrupts are used these are handled by the Priority Interrupt Bus. A fourth, called the
Utility Busf carries generic signals like a 16 Mhz dock and power-up reset.
1 - Introduction to VMEbus 3 . The VMEbus Handbook
VMEbes modules are connected together by backplanes which can have between 2 and 21
slots. One or two backplanes may be used depending upon the system configuration* A
Pl/Jl backplane handles 24 address bits, 16 data bits, some power/ground and all control
signals. A second backplane called the P2/J2 can be used to expand capability to 32
address and 32 data bits. It also adds more power/ground and includes some user defined
pins. The two backplanes may be mounted separately or as a single unit depending upon
the style selected. Figure 1-3 shows a 12 slot combination (monolithic) Pl/Jl and P2/J2
backplane mounted in a sub-rack (the Pl/Jl portion of the backplane is at the top).
VMEbus modules are located on 0.8" centers in the backplane*
22.214.171.124 Styles of Bus Modules
Two styles of VMEbus boards called single and double height modules can be used* The
smallest is the single height module^ and connects to the Pl/Jl backplane. These can
generate or accept 16/24 bit addresses and 8/16 bit data transfers. They are commonly used
if space is limited or if only a small amount of circuitry is used. In addition they are more
resilient to vibration than the double height board. Figure 1-4 shows a single height
The larger and more popular size board is the double height module. These are electrically
compatible with single height modules since they use the same set of Pl/Jl address, data
and control signals. Unlike the single height module they can be expanded (optionally) to
use up to 32 bits of address and data. Modules that do 32 bit address or data ttansfers must
be double height modules. Figure 1-5 shows a double height module.
Single and double height boards are sometimes referred to as 3U and 6U modules. Some
manufacturers also offer triple height (9U) modules which use three DIN 41612
connectors. While these are not VMEbus compatible they are supported by most Eurocard
packaging systems. Proprietary busses which require a third DIN 41612 connector will
often use the VMEbus definition on the PI and P2 connectors, and define their own bus on
P3. This was done in the VXIbus specification* Standard VMEbus modules can then be
adapted to the proprietary bus with 3U/6U/9U card cages or adapter modules like that
shown in Figure 1-6.
The use of two backplanes has proven to be one of the biggest features of VMEbus because
it allows two card sizes. Many users require a smaller card because of size or vibration
constraints* This allows VMEbus to compete against smaller boards such as STD bus.
For example the size and vibration resilience of single height modules make them popular
in the aerospace industry. Double height modules allow it to compete effectively against
busses with larger form factors such as Multibus II™.
VMEbus is asynchronous and non-multiplexed Because it is asynchronous no clocks are
used to coordinate data transfers. Data is passed between modules using interlocked
handshaking signals where cycle speed is set by the slowest module participating in the
Chapter 1 - Introduction to VMEbus 4 The VMEbus Handbook
Table 1-2. VMEbus Features
Item Specification Notes
Transfer mechanism Asynchronous, No central clock used
16-Wt (short I/O)
Addressing range Address range selected
Data path width selected
Bate path width 8§ 16, 24 or 32-Wt
Unalgneddato Compatible with most
transfer support popular microprocessors
Error detection Yes Using BERR* (optional)
Data transfer rate 0 - 4 0 Mbytes/second
Priority interrupt system
Interrupt levels 7
with vector return
Multiprocessing 1-21 processors Flexible bus arbitration
Yes Using SYSFAIL* (optional)
Single height 160 X 100 mm eurocard
Mechanical standard Double height 160 X 233 mm eurocard
DIN 603-2 connected
International standards Yes IEC 821, IEEE 1014
Chapter 1 - Introduction to VMEbus The VMEbus Handbook
Figure 1-3. Sub-rack with 12 slot combination Pl/Jl and P2/J2 backplane. Photo
courtesy Motorola Microcomputer Division.
Chapter 1 - Introduction to VMEbits The VMEbus Handbook
Figure 1-4. Single height (3U) module. Photo courtesy National Instraments.
Chapter 1 - Introduction to VMEbus The VMEbus Handbook
Figure 1-6. 9U adapter with 6U bus module. This unit allows standard VMEbus modules
to be used with Sue 3 workstations. Photo courtesy of National Instalments.
The maximum speed of asynchronous busses is limited by the propagation delay of signals
across backplanes and through buffer ICs, as Figure 1-7 shows. A VMEbus backplane
can be up to 500 mm (19.68") in length and can have relatively high inductive and
capacitive loads on the signal Graces. If this bus were synchronous it would probably have
a system clock speed of around 10 Mhz. This would allow 100 nanoseconds for a signal
to propagate from a module at one end of a bus, through an interface IC, across the
backplane, and through another interface IC to its destination. This is about as fast as a
synchronous system could operate using 74LSXX IC technology* Asynchronous buses
have the same delays but they can take advantage of higher logic speeds as they become
available. This allows bus bandwidth to increase as faster IC technology becomes
Chapter 1 - Introduction to VM
n l i
Figure 1-7. Signal propagation path in a microcomputer system.
126.96.36.199 Non-multiplexed Architecture
VMEbus is non-multiplexed. Figure 1-8 shows how multiplexed buses share the same set
of pins for address and data lines* A two part bus cycle is required to transfer data. During
the first portion of the cycle an address is passed over the pins. Data is then moved during
the second half of the cycle* This slows down bus cycles because extra time is required to
multiplex these two functions. Non-multiplexed busses have separate pins for both
address and data lines* Unfortunately this also means that more bus interface circuitry and
signal pins are required
Address Data Address Data
Tranceiver Tranceiver Tranceiver Traeceiver
i i i
Common address & date
(a) Multiplexed bus Non-multiplexed bus
Figure 1-8. Multiplexed and non-multiplexed buses.
1.2.1 A Compatibility
Ae important part of a reliable bus architecture is vendor compatibility. This is an on-going
problem in the microcomputer board industry because many modules are developed and
Chapter 1 - Introduction to VMEbus 12 The VMEbus Handbook
tested independently. Two boards will often be tested together only by the end user
(sometimes with an embarrassing outcome for the board vendor). Due to the large
numbers of products it is impossible to verify every module, with all others. A bus
specification has to be robust enough to insure that products developed independently (past
and future) will work together. When VMEbus was developed it was thought that
asynchronous architectures were more compatible than synchronous ones. Whether they
are or not has been the subject of an on-going controversy. The bus doesf however,
provide reasonable compatibility. The sheer volume of independently developed VMEbes
products has shown that this is true*
To further insure vendor compatibility a private company called VMElabs will test and
certify conformance to the VMEbus specification. If a bus module carries the VMElabs
seal of approval it should be 100% bus compatible.
Using its asynchronous, non-multiplexed architecture, VMEbes modules can achieve a
throughput in excess of 40 Mbytes/second. Just as important, however, is its ability to let
fast processors transfer data to peripherals of any speed. This allows users to tailor their
system to specific needs based on cost and availability.
1.2.2 Functional Modules
The VMEbus specification uses functional modules to describe its operation. A functional
module is a conceptual model used to describe each of the various parts of the bus. They
were introduced to simplify its description and to provide a framework for its
understanding* They help to describe the interaction of the various parts of the bus. Figure
1-2 shows them. Circuits on VMEbus modules may or may not be designed as modular
functional modules. They are used only as a conceptual tool
A master is a functional module that can initiate data transfer bus cycles. CPU modules and
peripherals with DMA controllers are examples.
Masters drive the following signals (t optional):
AM0-AM5 DSO* LWORD*t
IACK* DS1* A01-A31t
WRITE* AS* D00-D31t
Masters monitor the following signals (f optional):
SYSRESET* ACFAIL*t DTACK*
BCLR*t BERR* D00-D31t
Slave modules detect bus cycles generated by masters and participate in them if they are
selected. Examples of slaves include memory and I/O modules.
Chapter 1 - Introduction to VMEbus 13 The VMEbus Handbook
Slaves drive the following signals (f optional):
DTACK* BERR*f DOO-DSlf
Slaves monitor the following signals (f optional):
SYSRESET* DS1* A01-A3it
AM0-AM5* DSO* D0G-D31f
IACK* AS*t WRTIE^
188.8.131.52 Location Monitor
The location monitor watches the bus and asserts an on-board signal if certain addresses are
selected. It allows messages to be broadcast to all modules.
The location monitor uses the following signals (f optional):
LWORD* DS1* A01-A31t
AM0-AM5* DSO* AS*t
184.108.40.206 Bus Timer
The bus timer measures how long each data transfer takes. If it takes too long it asserts
BERR* to terminate the cycle. It is used to prevent lockups due to memory sizing or
system failures, and is usually located on the slot 01 system controller module.
Bus timers monitor the following signals (t optional):
DS1* DSO* DTACK*f
An interrupter generates interrupt requests to an interrupt handler (another functional
module). During an interrupt acknowledge cycle the interrupter passes a STATUS/ID
word (8,16 or 32 bits) to the interrupt handler. Because they respond to these cycles they
are a type of slave. Interrupters are sometimes called interrupt requesters. An example of
an interrupter would be a serial I/O module that requests an interrupt every time it receives a
Intemipters drive the following signals (f optional):
Chapter 1 - Introduction to VMEbus 14 ' The VMEbes Handbook
Interrupters monitor the following signals (f optional):
DSO* DSl*t LWORDf
AS* WRTTE*t A01^A03
IACKIN* IACK*t SYSRESET*
An interrupt handler responds to requests from interrupters. These modules must be
capable of obtaining the data transfer bus? generating an Interrupt acknowledge cycle and
reading a STATUS/ID word from the Interrupter. Interrupt handlers are commonly found
on CPU modules.
Interrupt handlers drive the following signals (t optional):
AS* WRHE*f AQl^ACB
Interrupt handlers monitor the following signals (f optional):
BERR* D00-D31t DTACK*
220.127.116.11 IACK* Daisy-chain Driver
During an interrupt acknowledge cycle the IACK daisy chain driver starts the IACK* daisy
chain. It Insures that only one Interrupter will respond with a STATUS/ID word, and
provides the correct timing for the daisy chain. It resides on slot 01 system controller.
The IACK* daisy chain driver only drives IACKOUT*. It monitors the following signals
DS1* DSO* AS*
Bus masters and Interrupt handlers use a requester to obtain the data transfer bus* The
requester uses the data transfer arbitration bus to handshake with the arbiter. The arbiter
grants the bus to the requester, which allows the master to use the bus. The requester is
sometimes called a bus requester.
Requesters drive the following signals (f are optional):
BRQ* - BR3* (only one) BBSY*
BG0OUT* - BG3OUT*
Chapter 1 - Introduction to VMEbus 15 The ¥MEbus Handbook
Requesters monitor the following signals (f are optional):
The arbiter monitors bus requests (from requesters) and grants control of the data transfer
bus, one master at a time.
The bus arbiter drives the following signals (t are optional):
BGOOUT* - BG3OUT* (one or more)
The bus arbiter monitors the following signals (t are optional):
BRO* - BR3* (one or more)
18.104.22.168 System Clock Driver
The system clock driver provides a stable 16 Mhz utility clock (SYSCLK) to all the bus
modules. Because VMEbus is asynchronous this dock has no relationship to other bus
22.214.171.124 Serial Clock Driver
The serial clock driver generates SERCLK (used by VMSbus). The frequency of
SERCLK depends upon the length of VMSbus. Although this functional module is
described by lie VMEbus specification it is defined by the VMSbes specification.
126.96.36.199 Power Monitor
The power monitor is respoesible for generating system reset and monitoring the system's
AC power source. The power monitor asserts SYSRESET* and ACFADL*.
The VMEbus specification groups all of the bus signals into four sub-busses. Figure 1-2
showed the relationship of these busses to the various functional modules.
L2.3.1 Data Transfer Bus
The data transfer bus is used by masters to move binary data between themselves and
slaves. It is also used by interrupt handlers to fetch a STATUS/ID from interrupters during
an interrupt acknowledge cycle.This bus is composed of address lines, data lines and
control signals. The following signals are included in the Data Transfer Bus:
Chapter 1 - Intextocion to VMEbus 16 - The VMEbus Handbook
Address Data Control
A01-A31 D00-D31 AS*
188.8.131.52 Data Transfer Arbitration Bus
VMGbus systems can have multiple masters and interrupt handlers* The data transfer
arbitration bus guarantees that only one master or interrupt handler can acquire the data
ttansfer bus at any time. Signals used by the Data Transfer Arbitetion Bus include:
BRO* BGOIN* BGOOUT* BBSY*
BR1* BG1IN* BG1OUT* BCLR*
BR2* BG2IN* BG2OUT*
BR3* BG3IN* BG3OUT*
1.23.3 Priority Interrupt Bus
Interrupters send interrupt requests to interrupt handlers over the priority interrupt bus* Up
to seven levels of intemipts can be used. This bus uses the following signals:
IRQl* IRQ5* IACK*
IRQ2* IRQ6* IACKIN*
IRQ3* IRQ7* IACKOUT*
The data transfer and data transfer arbitration buses are used during interrupt acknowledge
The utility bus is a collection of signals used for system reset, periodic timing, system
diagnostics and power failures. Signals of the utility bus include:
SYSCLK* SYSRESET* SYSFAIL* ACFAIL*
L2o4 Data Transfer Cycles
VMEbus offers four types of data transfer bus cycles. This variety of cycles allow the bus
to adapt to the changing requirements of the system.
Chapter 1 - Introduction to VMEbus 17 The VMEbus Handbook
184.108.40.206 Read/write Cycle
Read/write cycles are used to transfer 8, 16, 24 or 32 bits of data between masters and
slaves. The cycle begins when the master broadcasts an address and an address modifier.
Slaves capture the address and respond to the cycle (if they are selected).
220.127.116.11 Read-modify-write Cycle
The read-modify-write cycle permits indivisible bus cycles. This cycle is especially useful
for arbitrating shared resources in multiprocessor or multiuser systems with semaphores.
1.2.43 Block Transfer Cycle
The block transfer cycle moves a block of data between masters and slaves. Read or write
block transfer cycles up to 256 bytes in length are permissible. This cycle is faster than
READ/WRITE cycles because slaves are addressed only once (at the beginning of the
cycle). It is especially useful for quickly moving large blocks of data.
1.2 A A Address-only Cycle
During the address-only cycle a master will generate a valid address but slaves will not
respond (the data strobes are never asserted). It allows slaves to decode an address at the
same time that a masters on-board memory doesf and speeds up the system.
1.2.5 Interrupt Acknowledge Cycle
The interrupt acknowledge cycle is initiated by interrupt handlers in response to an
interrupt. This cycle performs two functions. It passes a STATUS/ID byte (vector) and
arbitrates the interrupt sources.
1.2.6 Arbitration Cycle
An arbitration cycle is performed during bus arbitration. It begins when a requester
generates a bus request to the central arbiter. The arbiter grants the bus to the requester
when the bus is not busy, and the requester acquires the bus by asserting the bus busy
signal (BBSY*). The requester releases the bus by negating bus busy.
1.2.7 Signal Summary
Table 1-3 shows pin assignments for the Pl/Jl and P2/J2. backplanes* The Pl/Jl
backplane carries 24 address lines, 16 data lines, all control signals and some of the power
and ground traces. The P2/J2 connector carries the extra eight address and 16 data lines,
with additional power and ground pins. All of the defined P2/J2 signals are located on the
center row of pins. The outer two rows of that connector axe user defined, and can be used
for any purpose. In general these axe used for I/O signals or for a side bus such as
VMXbus, VSBbus or VXIbus.
Chapter 1 - Introduction to VMEbus 18 The VMEbus Handbook
i gl i |j | S ^ transition o f
Each VMEbes signal faEs into one of five classes, of electrical specification These classes
are called standard three-state, high current three state, standard totem»pole9 high current
totem-pole and open collector sigeals^ Chapter 6 describes the characteristics of these
classes in detail
The address bus A01-A31 is driven by masters and interrupt handlers. During data ttansfer
cycles they are used to broadcast short I/O (16 bit), standard (24 bit) or extended (32 bit)
addresses. During these bus cycles the number of valid address lines is broadcast using the
address modifier code AMQ-AM5.
During inteixupt acknowledge cycles interrupt handlers use AQ1-AG3 to broadcast the level
of inteixupt being acknowledged.
A01-A31 are standard three-state class signals*
The AC power failure signal ACFADL* is driven by the power monitor module. When
asserted it signals to all modules that the system power source is about to stop. It is not
used in all VMEbus systems. ACFAIL* is an open-collector class signal
Chapter 1 - Introduction to vM&ons 19 The VMHbus Handbook
Table 1-3. VMEbes pin assignments*.
Kn Number Row A RowB RowC
O BBSY* D08
2 D01 BCLR* D09
3 D02 ACFAIL* D10
4 DOS BGOM* Dll
5 D04 BGOOUT* D12
6 DOS BG1IN* D13
7 D06 BG1OUT* D14
8 D07 BG2IN* D15
9 GND BG2OUT* GND
10 SYSCLK BG3IN* SYSFAIL*
11 GND BG3OUT* BERR*
12 DS1* BRO* SYSRESET*
13 DSO* BR1* LWORD*
14 WRITE* BR2* AM5
15 GND BR3* A23
16 DTACK* AMO A22
17 GND AMI A21
18 AS* AM2 A20
19 GND AM3 A19
20 IACK* GND A18
21 IACKIN* SERCLK A17
22 IACKOUT* 8ERDAT* A16
23 AM4 GND A15
24 A07 IRQ7* A14
25 A06 IRQ6* A13
26 A05 IRQ5* A12
27 A04 IRQ4* All
28 A03 IRQ3* A10
29 A02 IRQ2* A09
30 A01 IRQ1* A08
31 -12VDC +5VSTDBY -t-12 VDC
32 +5VDC + 5VDC +5 VDC
The address modifier code AM0-AM5 is driven by masters. It accompanies an address and
indicates both the size and type of address transfer. It is used by slaves to determine which
address lines should be decoded AM0-AM5 are standard three-state class signals.
Chapter 1 - Introduction to VMEbus 20 bus Handbook
Table 1-3 (con't).
Pin Number Row A RowB RowC
1 User Defined +5VBC User Defined
2 User Defined GND User Defined
3 User Defined RESERVED User Defined
4 User Defined A24 User Defined
5 User Defined A25 User Defined
6 User Defined A26 User Defined
7 User Defined A27 User Defined
8 User Defined A28 User Defined
9 User Defined A29 User Defined
10 User Defined A30 User Defined
11 User Defined A31 User Defined
12 User Defined GNB User Defined
13 User Defined +5VDC User Defined
14 User Defined D16 User Defined
15 User Defined D17 User Defined
16 User Defined D18 User Defined
17 User Defined D19 User Defined
18 User Defined D20 User Defined
19 User Defined D21 User Defined
20 User Defined D22 User Defined
21 User Defined D23 User Defined
22 User Defined GND User Defined
23 User Defined D24 User Defined
24 User Defined D25 User Defined
25 UserBeleed D26 User Defined
26 User Defined D27 User Defined
27 UserBeleed D28 User Defined
28 User Defined D29 User Defined
29 User Defined D30 User Defined
30 . User Defined D31 User Defined
31 User Defined GND User Defined
32 User Defined +5VBC User Defined
Address strobe AS* Is driven by masters and interrupt handlers. When it is asserted if
indicates that a valid address and address modifier have been placed onto the bus. The
signal also qualifies other signals such as LACK*. AS* is a high current three-state signal
Chapter 1 - Introduction to VMEbus The VMEbus Handbook
Bus busy BBS Y* is driven by masters and interrupt handlers when they are using the bus.
The arbiter monitors this signal to determine when it should grant the bus to another master
or interrupt handler. BBS Y* is an open-collector class signal
Bus clear BCLR* is driven by the bus arbiter. When asserted it informs the current master
or interrupt handler that another module is requesting the bus. The conditions under which
it is asserted depend upon the arbitration method being esed (see Chapter 3). BCLR* is a
high ceront totem»pole class signal.
Bus error BERR* is driven by slave or bes timer modules. A slave asserts it if an error has
occurred during the bus cycle. The bus timer asserts it when the bus has locked-up.
BERR* is an open-collector class signal.
18.104.22.168 BGQIN*^BG3IN* / BG0OUT*-BG3OUT*
The signals BGQIN* - BG3IN* and BG0OUT*-BG3OUT* are part of the bus grant daisy
chain and are driven by arbiters and bus requesters. The slot 01 arbiter asserts a bus grant
in response to a bos request on the same level (BRO* - BR3*)* The bes grant daisy chain
will start at the slot 01 system controller and propagate from module to module until the
requester that initially needed the bus receives it. Each VMEbus module has a bus grant
input and a bus grant output. They are standard totem-pole class signals.
BGOIN* - BG3IN* are part of the bus grant daisy chain. Each VMEbus module has an
incoming BGXIN* signal and an outgoing BGXOUT*. The arbiter in the slot 01 card
position monitors bus request signals BR0*-BR3* and grants the bus by asserting
Bus requests BR0*-BR3* are asserted by a requester whenever its master or interrupt
handler needs the bus. Before accepting the bus the master must wait until the arbiter
grants the bus by way of the bus grant daisy chain BG0IN*-BG3IN*o BRO* - BR3* are
open-collector class signals.
Data bus D00-D31 is driven by masters, slaves or interrupters. These are bi-directional
signals and are used for data teasferSo Different portions of the data bus are esed
depending upon the state of.DSO*, DS1*, A01 and LWORD*. BOO - D31 are standard
Chapter 1 - Introduction to YMEbes 22 The VMBbus Handbook
Data strobes BSD* and DS1* axe driven by masters and interrupt handlers and serve two
purposes. When combined with LWGRJD* and A01 they indicate the size and type of data
transfer. They also indicate valid data on the data bus during a write cycle9 and infomi a
slave that it should place data onto the data bus during a read cycle. DSO* - DS1* are high
current three-state class signals.
Data transfer acknowledge DTACK* is driven by slaves or interrupters. During a write
cycle DTACK* is asserted after the slave has latched the data on the data bus. During a
read cycle or interrupt acknowledge cycle DTACK* is asserted after valid data is placed
onto the data bus. DTACK* is an open-collector class signal.
Ground GND is used both as a signal reference and a power return path.
Interrupt acknowledge IACK* is driven by interrupt handlers in response to interrupt
requests. It is connected to IACKIN* at slot 01 (on the backplane) to start propagation of
the interrupt acknowledge daisy chain. IACK* can be either an open-collector or a
standard three-state class signal.
The interrupt acknowledge daisy chain IACKIN* - IACKOUT* is driven by the IACK
daisy chain.driver. They are used both to indicate that an interrupt acknowledge cycle is in
progress and to determine which interrupters should return a STATUS/ID. They are
standard totem-pole class signals,
Priority interrupt requests IRQ1*-IRQ7* are asserted by intemipters. Level seven is the
highest priority and level one the lowest. They are open-collector class signals.
Long word LWORD* is driven by masters. It is used in conjunction with A01, DSO* and
DS1* to indicate the size of the current data-transfer. LWORD* is a standard three-state
Chapter I - Introduction to VMEbus 23 The VMEbus Handbook
VMEbus data is transferred using a sub-bus called the Data Transfer Bus* Masters use this
sub-bus to transfer data to and from slaves9 and interrapters use it to pass STATUS/ID
words to handlers. Modules with location monitors can also monitor this sub-bus looking
for specific types of bus cycles aed interrupt an on-board processor in response. The Data
Transfer Bus is asynchronous and non-multiplexed.
2.1 Bus Cycles
The Data Transfer Bus allows several types of bus cycles. These include the read/write,
block transfer, read-modify-write and address-only cycles. Chapter 4 covers an additional
cycle called the interrapt acknowledge cycle. Not ail bus modules are compatible with all
types of bus cycles. When evaluating or designing VMEbes modules, be sere that slaves
are compatible with the cycles generated by the masters. For example^ a master may
generate a read-modify-write cycle9 but not all slaves respond to it
2.1.1 Read/Write Cycle
Of all the cycle types, the read/write cycle is the most common. It is used to pass data
between a master and a slave 8,16,24 or 32 bits at a time.
Chapter 2 - Data Transfers 40 The VMEbus Handbook
Slave addressing takes place during every read/write cycle. This is done with address lines
A01-A31, a six bit address modifier code AMQ-AM5, and two control signals IACK* and
LWORD*. All of these signals are qualified by the falling edge of address strobe AS*. In
addition, the two data strobes BSD* and DSl* determine which byte location within a four
byte group data should be read or written to, and provide the information usually given by
the missing address line A00.
22.214.171.124 Address Sizing
Three sizes of address can be used as Table 2-1 shows. These are called short I/O,
standard, and extended addressing modes9 and correspond to lengths of 16, 24 and 32 bits.
The size can be changed on every bus cycle which allows a wide variety of system
configurations. Its most obvious advantage is to enable older microprocessors to share the
bus with newer ones. For example, a CPU module with a 68GGG microprocessor capable
of generating 24-bit addresses may share the bus with a 32 bit 68020.
Table 2-1. Dynamic address widths.
Address Modifier Address Active
Address Lines Mnemonic
Short I/O 16 AOl - A15 A16
Stuncfeffd 24 AOl - A23 A24
Extended 32 AOl - A31 A32
126.96.36.199 Address Modifier Code
The number of address lines that are decoded by slaves is given by the six bit address
modifier code AMQ-AM5. This code accompanies each address, with their meanings
shown in Table 2»2* During a bus cycle the slave will monitor the address modifier, and
then determine which address lines to decode. Short I/O addresses are decoded from A01-
A15, standard addresses from A01»A23t and extended from A01-A31. All slave modules
do not respond to all address modifier codes.
Chapter 2 - Data Transfers The VMEbus Handbook
Table 2-2. Address modifier codes.
Modifier IACK* Address Transfer Type
3F 1 24 Standard Supervisory Block Transfer
3E 1 24 Standard Supervisory Program Access
3D 1 24 Standard Supervisory Data Access
3B 1 24 Standard Non-Privileged Block Transfer
3A 1 24 Standard Non-Privileged Program Access
39 1 24 Standard Noe»Wvileged Data Access
2D 1 16 Short Supervisory Access
29 1 16 Short Non-Privileged Access
IF 1 User Defined
IE 1 User Defined
ID 1 — User Defined
IC 1 — User Defined
IB 1 User Defined
1A 1 — User Defined
19 1 — User Defined
18 1 - User Defined
17 1 — User Defined
16 1 — User Defined
15 1 — User Defined
14 1 User Defined
13 1 User Defined
12 1 User Defined
11 1 — User Defined
10 1 - User Defined
OF 1 32 Extended Supervisory Block Transfer
0E 1 32 Extended Supervisory Program Access
OD 1 32 Extended Supervisory Data Access
OB 1 32 Extended Noe-Privileged Block Transfer
OA 1 32 Extended Non-Privileged Program Access
09 1 32 Extended Noe-Privileged Data Access
XX 0 3 Interrupt Acknowledge Cycle (uses A01-A03)
Note: All codes other than those shown are reserved for future use.
Don't care state = (XX), Undefined = (-).
Besides address size, the address modifier also shows the type of bus cycle. It
discriminates between instruction fetches, data read/write cycles, block ttansfer cycles and
whether the cycle is generated by user or non-privileged (supervisory) programs.
The function of the IACK* signal can be associated with the address modifier codes.
IACK* is asserted by interrupt Handlers to show that the current cycle is an interrupt
acknowledge cycle, and negated by masters to show that it is a data transfer cycle. When
Chapter 2 - Data Transfers The VMEbus Handbook
evaluating or designing slave modules IACK* can be treated like a seventh address
modifier bit. When IACK* is asserted, AM0-AM5 can be ignored by slaves.
The address modifier is an important tool With it, VMEbus modules can be as simple or
as complex as the application requires. Slaves, such as a serial I/O modules, require only
several bytes of address space and can use short I/O addressing. This reduces part count
by decreasing the number of comparators and control logic. This is important to lower the
cost of the interface as well as to conserve board space. More complex boards such as
memory or graphic controllers require standard or extended addresses because of their large
The address modifier also makes single (3U) and double height (6U) modules compatible,
Since single height modules ese the PI connector they can monitor only A01-A23. This
limits these modules to the short I/O and standard cycles. Double height modules,
however^ can monitor an additional eight address lines on the P2 connector, and can
perform 32 bit address transfers. Without the address modifier the simple P2 expansion
bus would be awkward.
To help select compatible modules, a series of mnemonics have been developed which
classify the addressing modes shown in Table 2»3* A16, A24 and A32 mnemonics
correspond to the number of address lines used in a transfer. For example an A16 si we,
will respond to bus cycles generated by an A16 master.
The IEEE-1014-87 VMEbus specification requires that A32 masters generate A24 and AU
cycles. Similarly A24 masters must also generate A16 cyclese Slaves do not have any
such requirements. Earlier versions of the bus specification did not make h i
When selecting master modules make sure that they will generate all the cycles < ocfMiiPd by
the slaves (this is not guaranteed by the VMEbus specification).
188.8.131.52 Typical Read/Write Cycle
During a typical read/write cycle a master addresses a slave (described above)
transfers data. The data is transferred using D00-O31, WRITE*, data
acknowledge (DTACK*) and bus error (BERR*). The data lines and the WRITE* si,
are qualified using data strobes DSO* and
The timing waveform for a read cycle is shown in Figure 2-1. Here a master addresses a
slave by driving A01-A31, AM0-AM5, IACK* and LWORD*. These are qualified by the
falling edge of AS*. The master also negates WRITE* and asserts data strobes DSO*
and/or DSl* e The slave decodes the address^ places data onto D00-D31 and asserts data
transfer acknowledge DTACK*. When the master has latched the data, it informs the
slave by negating the data strobe(s). The slave then negates DTACK* and the cycle is
Chapter 2 - Data Transfers 43 The- VMFbus Handbook
Table 2-3. Mnemonics describing the various addressing modes.
A16 Generates (master) or accepts (slave, location monitor)
bus cycles with short I/O (16-bit) addresses*
A24 Generates (master) or accepts (slave, location monitor)
bus cycles with standard (24-bit) addresses. A24 masters
must also be A16 compatible,,
A32 Generates (master) or accepts (slave, location monitor)
bus cycles with extended (32-bit) addresses* A32 masters
must also be A16 and A24 compatible.
Figure 2-1. Read cycle with address pipelining.
A write cycle is similar to a read cycle as Figure 2-2 shows. The main difference is that
data is placed onto the data lines before the data strobes are asserted Once the slave asserts
BTACK* or BERR*, the master can negate WRITE* and change the data lines. For this
reason a slave must latch the data before it asserts BTACK*.
184.108.40.206 Data Strobes
The data strobes BSO* and BS1* serve a dual function a level sensitive signal they
select which bytes are accessed As an edge sensitive are used to qualify data.
Chapter 2 - Data Transfers 44 •bus Handbook
Figure 2-2. Write cycle with address pipelining.
The VMEbus specification does not use the terms DSQ* and DS1* in its timing diagrams.
Instead it refers to DSA* and DSB*» This notation was introduced to prevent confusion in
cases where bus skew (propagation delay) causes one data strobe to fall before the other.
Propagation delay times through buffers at the master may also cause these signals to be
sent at slightly different times.
220.127.116.11 Cycle Termination
Slaves terminate all bus cycles by asserting DTACK* or BERR*. DTACK* is the normal
way to end the cycle* During read cycles the slave asserts DTACK* after driving the data
bus, and during write cycles the slave asserts it after it has latched the data.
BERR* can be asserted by a slave or a bus timer. When it is asserted by a slave it indicates
that an error has occurred during the cycle. The VMEbus specification does not say what
may have caused the error. For example^ a memory module can assert BERR* when a
parity error occurs. The bus timer asserts BERR* if the bus has locked up, sometimes
caused by a data strobe which has been stuck low for a long period of time.
VMEbus uses a fully interlocked handshaking mechanism with data strobes DSG* and
DS1*9 DTACK* and BERR*9 At the beginning of a cycle a master must not assert either
data strobe until DTACK* and BERR* (from the last bus cycle) have been negated*
Failing to do so may cause data to be corrupted on the current or the previous cycle. The
680XX microprocessors don't do this and external circuitry must be provided on CPU
boards to make them compliant.
18.104.22.168 Address Pipelining
Some microprocessors use address pipelining to speed up data transfers. Simply stated,
the bus master will broadcast the address of the next bus cycle before the current cycle is
Chapter 2 - Data Transfers The VMEbus Handbook
completed. As Figures 2-1 and 2-2 showed^ once the slave acknowledges the data transfer
(by asserting BTACK*) the master negates AS*, places a new address oe the bus, and then
asserts AS* again. By overlapping the address broadcast with the previous cycle, bus
transfers can be speeded up significantly. Slaves must be designed to function properly In
the presence of an address pipelining cycle.
The removal of a valid address before DTACK* or BERR* are negated is sometimes called
address rot Similarly, changing the data lines after DTACK* or BERR* Is asserted during
a write cycle Is called data rot.
When designing or evaluating slave ieterfacesf be sure they latch all addresses and address
modifiers before asserting DTACK* or BERR*. The address Is often latched on the falling
edge of either data strobe. Failing to do so may cause the slave to change Its data lines
before the end of a read cycle because its on-board address has changed. During a write
cycle the slave's Internal timing may be disrupted.
When evaluating or designing slaves that do not utilize address pipelining (all slaves mest
function properly In the presence of these cycles), care should be taken when latching the
address on the falling edge of AS*. On read cycles, AS* can be negated and re-asserted
Immediately after they assert DTACK* or BERR*. If the address Is latched on the falling
edge of AS*, the slave could be presented with a new address before It negates DTACK*
or BERR*, and corrupt the data. On slaves which do not implicitly participate in address
pipelining cyclesf It Is better to latch the addresses on the falling edge of either data strobe.
Often the the data strobes are forfed together and used to latch the addresses.
When evaluating or designing modules that support block transfer cycles (discussed
below), special care should be taken to Insure that address pipelining will work. During
the block transfer cycle the master may change A01-A31 and LWORD* after the first
falling edge of DTACK*. The address modifier code AM0-AM5 must remain stable until
the last falling edge of DTACK* In the block transfer cycle.
Address pipelining is conceptually related to the early BBSY* release mechanism (see
Chapter 3 on Multiprocessing). During bus arbitration, a new master can assume
ownership of the data transfer bus after the current master negates address strobe AS**
With address pipelining the new master can begin addressing a slave even before the
previous master has completed the data transfer cycle (signified by negating the data
strobes). This reduces the overhead necessary to change masters.
22.214.171.124 Data Sizing
Like the addresses, the data bus can be dynamically configured. Data transfers of 8? 16,24
and 32 bits can be made, usually without any software overhead whatsoever. This makes
VMEbus products compatible over wide ranges of technology, and offers the same benefits
that dynamic address sizing does.
Data bus sizing Is achieved by splitting the data lines into four byte wide banks: D00-D07,
BQ8-O15, D16-D23 and D24-D31. The individual banks are used depending upon the size
of data transfer. The master signals the type and size of transfer by way of data strobes
BSD* and DS1*, address line A01 and LWORD*. The slave then routes data to or from
the coixect bank
VMEbus uses a B YTE(n) convention to specify how data Is stored in memory, where (n) Is
the address offset from an even 32-Mt boundary. Table 2=4 shows this convention*
Chapter 2 - Data Transfers 46 The VMEbus Handbook
Table 2-4 Data organization in memory.
X = Don't care
During a transfer the master asserts DS0*f DS1*, A01 and LWORD* depending epon
where it expects to read or write data. The level of these signals and the associated data
paths are shown in Table 2-5.
VMEbus offers four styles of bus interface which adds to its flexibility. These options are
classified using the mnemonics D08(O), D08(EO), D16 and B32. As with dynamic
address sizing, dynamic data sizing allows older technology to work with newer* For
example, a CPU with a 68000 microprocessor (8 and 16 bit data path) can share VMEbus
with a 68020 based CPU (8,16,24 and 32 bit data path). The same is true for slaves.
The D08(O) slave can transfer data over D00-D07. It is called a D08(O) because transfers
of eight bits can be made only at odd addresses (such as byte transfers at $XXXXXX01»
$XXXXXXQ3). A typical example would be an 8-bit serial I/O port. D08(O) masters are
not specifically allowed under the VMEbus specification since these are simply a subset of
the D08(EO) master.
The D08(EO) slave is slightly different from a D08(O) because a byte can be read from this
module at even or odd addresses. Transfers to or from these modules must be done eight
bits at a time, and only one data strobe may go low at any time. An example of a master
with this interface would be a CPU module with an 8-bit processor such as a 68008. A
slave module could be an I/O board with an 8-bit RAM IC capable of transferring data at
even and odd addresses.
The D16 and D32 interfaces monitor or drive •-D31. These are most
common among CPU or memory modules.
The DEEE-1014-87 version of the bus specification requires that D16 masters, slaves and
location monitors include the D08(EO) capability. It also requires that D32 masters, slaves
and location monitors include the D16 and D08(EO) capabilities. These were both optional
under the Revision B, C, C.1 and EEC 821 versions of the bus specification.
Chapter 2 - Data Transfers 47 The VMEbus Handbook
The VMEbus specification does not allow slaves to acknowledge their port size during a
transfer. Some popular microprocessors (like the 68020 and 68030) require their slaves to
do so. A common way to interface these microprocessors is to memory map the port sizes.
For example, a 32-bit CPU module may configure its bus interface as a D16 master during
bus access between $00000000 and $Q0FFFFFf and 32;bits between $01000000 and
$01FFFFFFs In this way 16 bit and 32 bit modules can reside on the same bus.
Chapter 2 - Data Transfers The VMEbus Handbook
Selection of a data port size may also be done with a mode bit. A mode bit is simply a bit
the CPU sets depending upon what type of access it requires. For instance, the bit could
be set when the master generates a D32 cycle, and cleared for a B16® The advantage of this
method is simplicity of design. The disadvantage is that the software may need to be
continually setting and clearing the bit if a mix of boards is used in the system.
126.96.36.199 Unaligned Data Transfers
Unaligned data transfers are allowed under the VMEbes specification. As Table 2-5
shows9 a VMEbus module can place two and four bytes of data at other than two or four
byte boundaries. These are called unaligned transfers* Unalgned transfers can speed up a
VMEbus system by allowing 32 bits of data to be transferred at odd addresses in two bus
cycles instead of three.
When a master reads or writes data it can do so in a variety of ways. For example,
consider case B of Figure 2-3. Here a four byte transfer takes place at an unaligned
boundary. The master can transfer the data using one of two methods. Using the first
method the master transfers a Single Byte(l), a Double byte(2-3) and a Single Byte(0)o
This means that the whole transfer takes three bus cycles to complete* Using the second
method the master will do Unaligned Byte(l-3) and a Single Byte(0) transfer. This second
method takes only two bus cycles. Unaligned transfer can substantially reduce the number
of VMEbus cycles to ttansfer data.
Figure 2-3* Four ways that 32-bits of data can be saved in memory.
The VMEbus specification does not stipulate the order in which data is transferred
to or from memory. In the example above? the Single Byte(O) transfer could take place
before or after the Unaligned Byte( 1 -3) transfer.
Figure 2-4 shows four ways that 16-bit words may be stored in memory.
Chapter 2 - Data Transfers 49 The VMEbus Handbook
Figure 2-4 Four ways that 16-bits of data can be saved in memory.
A special mnemonic called UAT specifies whether an unaligned transfer can be generated
by a master, accepted by a slave or monitored by a location monitor*
The IEEE-1014-87 version of the bus specificatioii also requires that D32 slaves and
location monitors must accept unaligned (UAT) data transfers, D32 masters are not
required to generate these cycles, however. The UAT function was optional for slaves and
location monitors under earlier versions of the bus specification.
Some software compilers can be set to generate code only on even boundaries. This
reduces the number of unaligned transfers and therefore speeds up the system. Many
compilers with this feature will not prevent data transfers at enaligned boundaries, only
2.1.2 Block Transfer Cycle
The block transfer cycle is used to speed up VMEbus data transfers. Blocks of data up to
256 bytes in length are moved at high speeds across the bus. The block transfer cycle is
sometimes called burst mode* Few VMEbus modules support the block transfer cycle.
To understand what the block transfer cycle is used for, consider a CPU module fetching
program instructions* When instructions axe read they are fetched in ascending order. For
example, if an instruction is read at address $100? it will probably read the next one at $101
or $102. Some computers take advantage of this by "thinking ahead" and reading data
from the next few bytes of memory while the CPU is busy with the current instruction.
Circuits which do this are often called instruction prefetch or pipelining circuits. Special
dynamic memories^ called page mode and nibble mode memories, are often used to
simplify instruction prefetch. These memories can be placed into a high speed "dump"
mode which allow fast burst transfers^ and are often double or triple the speed of normal
The block transfer cycle also improves the performance of multiprocessing systems. Here
it can be used to transfer data in small bursts, reducing the overhead of bus arbitration.
The block transfer cycle is also faster than read/write cycles because the master presents an
address only once during the cycle. The extra overhead of computing and changing
addresses does not take place. An example of a block transfer cycle is shown in Figure 2-
Chapter 2 - Data Transfers 50 The VMEbus Handbook
Figure 2-5o Block transfer cycle (write).
During the cycle both an address and a block transfer address modifier is presented by the
master to the slave. Once the slave is addressed, multiple bytes of data can be read or
written (in ascending order) by toggling the data strobes. Block transfer counters on the
slave automatically increment their on»board addresses. This relieves the master from
competing and changing the address during every cycle.
To reduce the complexity of block transfer slavesf a rule was introduced in the revision C
VMEbus specification which forbids block transfers from crossing 256 byte boundaries.
This provision solved several problems that existed with the block transfer cycle. It
prevented board-to-board crossings during a cycle, it reduced the address counter
requirements to eight bits, and allowed the use of commonly available nibble or page mode
memories (many standard memories require that block transfers don't cross 256 byte
boundaries). If it must cross the boundary the master can stop the cycle, re-submit a new
address, and do another block transfer.
The 256 byte rale also prevents a master from hogging the bes with large numbers of bus
cycles. Since VMEbus arbitration cannot take place with AS* asserted (see Chapter 3) a
bus arbitration cannot occur in the middle of a block transfer cycle. This rale will allow at
least one arbitration to occur every 256 bes cycles.
The ability to generate or accept a block transfer cycle is optional To prevent
incompatibility between modules^ a mnemonic caled BLT is used. If a master can generate
a block transfer cycle it is called a BLT master. If a slave can accept a block transfer cycle
it is called a BLT slave. When integrating a VMEbus system make sure that compatible
modules are used.
The BLT mnemonic is not to be confused with the bacon, lettuce and tomato cycle which is
not supported by VMEbus.
Chapter 2 - Data Transfers 51 Hie VMEbus Handbook
2olo3 Eead-Moilfy-Wrlte Cycle
The read-modify-write cycle is used in multiprocessor and multiuser systems. This special
cycle allows multiple processes to share common resources such as disk controllers, serial
ports or blocks of memory. As the name implies, the read-modify-write cycle will read and
write data to a memory location using one bus cycle instead of two. This prevents a
common resource from being allocated to two processes because software flags are
checked and changed in one cycle.
The read-modify-write cycle is sometimes called an indivisible cycle or a test-and-set cycle.
A possible application for the test-and-set cycle would be an airline ticket reservation
system. Consider the situation where two people (at different locations) reserve seats on a
flight from New York to London. Without the read-modify-write cycle both people could
be assigned the same seat if both reservations were made at exactly the same time* In this
case two processes (ticket offices) could both acquire a single resource (airline seat).
For example, assume the ticket reservations software were set up so that each seat on the
fight was represented by a bit in memory. If the bit is a zero the seat is empty s and if it's a
one then it's reserved. To reserve a seat, the ticketing software would first read the bit to
see if the seat were occupied. If the bit is zero the software would set it to a one. If it the
bit was already set (the seat was occupied), then the software would look for another seat.
In 680XX assembly code it would look something like this:
* AO = LOCATION OF MEMORY BIT REPRESENTING SEAT
BTST.B #7s(A0) * IS THE SEAT TAKEN?
BEQ GETSEAT * BRANCH IF SO
GETSEAT: BSET.B #7,(A0) * RESERVE THE SEAT
The problem occurs between the time the bit is tested (BTST.B) and it is set (BSET.B)O
During this time several instructions are perforaied, such as BEQ. In a multiprocessing or
multitasking system, a bus arbitration could take place between the time the bit is checked
and when it is set. If another processor were running the same codes at the same time, both
coeld get the same seat because they both read the bit as zero. The outcome would be two
passengers booked on the same seat, an embarrassing problem for the airline.
This problem can be solved using the read-modify-write cycle. In the 680XX family, a
CPU can generate this cycle using the TAS (test-and-set) instruction. This instruction
reads a byte, tests the condition of bit #7, sets it to a one, and writes the byte back to
memory. Rewriting the program using TAS would look something iike this:
* AO = LOCATION OF MEMORY BIT REPRESENTING SEAT
TAS (AO) * TEST BIT Al
BEQ GETSEAT * BRANCH IF AVAILABLE
(Chapter 2 - B a a Transfers 52 The VMEbus Handbook
The airline reservation example is rather simplistic bet does illustrate the use of the read-
modify-write cycle. Many multiprocessing systems must contend for system resources
such as memory buffers and peripherals.
Not all VMEbes masters or slaves will participate in the read-modify-write y
that generate or accept the cycle are said to be RMW compatible (all modules must tolerate
RMW cycles on the bosf however). When evaluating or designing bus modules, look at
the software requirements to determine if modules need to be RMW compatible.
The read-modify-write cycle is shown in the timing diagram of Figure 2=6. During the
cycle9 back-to-back read, and write cycles are performed while AS* is asserted In the first
half of the cycle WRITE* is negated^ and data is read from memory. The master modifies
ihe-data, asserts WRITE*, and puts the data back. Keeping AS* asserted prevents bus
arbitration from occurring in the middle of the cycle (see Chapter 3), and keeps more than
one processor from reading data*
Figure 2-6. The read-modify-write cycle.
When evaluating or designing VMEbes masters capable of read-modify-write cycles, make
sure they do not change their address lines during the cycle. This can cause problems on
processors such as the 68020 which utilizes a special RMC (Read»Modify-Control) pin.
Under certain conditions the 68020 can change its address lines during the read-modify-
write cycle. A possible solution is to latch the address lines of the microprocessor before
the start of every cycle.
Problems can also happen on read-modify-write slaves. A common mistake is to use AS*
to drive the slave's DTACK* generator. Once the slave has been selected, use the data
strobes DSO* and DS1* to assert and negate DTACK*a If this is not done, the module
could generate DTACK* on the first (read) half of ihe read-modify-write cycle, and lock
the bus up on the second
Chapter 2 - Data Transfers 53 The YMEbus Handbook
The address-only cycle is used to broadcast an address. No data is transferred during the
cycle. This cycle is differentiated from read/write cycles in that masters do not assert either
data strobe. Because the data strobes are not asserted, the slave does not terminate the
cycle with DTACK* or BERR*. Figure 2-7 shows the cycle.
AMO - AM5
Figure 2-7. Address-only cycle.
The address-only cycle allows a master's local memory address decoder to work in parallel
with a slave's, and can speed up the bus in some cases. It can also simplify the design of
some masters. For example9 a 68010 MPU with 68451 MMU can terminate a bus cycle
after the 68451 asserts AS* (the MMU aborts the external cycled The bus interface design
is simplified if these cycles are allowed to happen onto VMEbos.
The ADO mnemonic is used to describe modules that can initiate or tolerate address-only
cycles. When evaluating or designing slave modules, make sure they tolerate ADO cycles.
The IEEE-1014-87 version of the VMEbus specification requires that all slaves do so.
Modules designed under earlier specifications do not have to.
2@2 Circuit Example - Simple 8-bit Parallel I/O Module
While most boards in a system can be purchased through established vendors^ the need
often arises where the user must design and build at least one VMEbus module. These are
usually specialized I/O modules that are customized to the application. Often the resources
dedicated to these custom projects are larger than those given to the rest of the system.
Several circuits (all have been built and tested) axe presented here to aide the user in
understanding and designing simple VMEbus interface circuits.
Figure 2-8 shows a simple circuit for an 8-bit parallel I/O module with an
A16:D32:D16:D08(O) interface. This module illustrates some basic slave interfacing
concepts including address decoding, bus timing and use of the control signals. It can be
used as a building block for real time clocks-, A/D converters, D/A converters and other
simple I/O functions.
A write cycle to this board causes U7 to latch and output one byte of data. A read cycle
will return data present at the input of U6. The address modifiers and address lines are
decoded with an 8-bit magnitude comparator UL Since the board is an A16 module,
address modifiers $29 and $2D must be decoded as Table 2-6 shows. Note that Ul does
not monitor AM2. This bit is considered a don't care state which simplifies the circuit
Chapter 2 - Data Transfers 54 The VMEbus Handbook
Table 2-6. Address modifier codes for 8-bit I/O module.
$29 1 0 1 0 0 1
$2D 1 0 1 1 0 I
Chapter 2 - Data Transfers 55 The VMEbus Handbook
A16 slaves only need to decode address bits A01-A15, and A16-A31 can be ignored. By
decoding only the upper three address bits A13-A15 the circuit cae be built using one 8-bit
comparator IC. The only drawback to this is the 8 Kbytes of address space the medeie
takes up. Since the A16 address space is usually reserved for simple I/O devices^ large
holes in memory can be tolerated.
The P=Q output of Ul is latched using flip-flop U3e This is because the address lines on
VMEbus slaves must be latched at the beginning of every cycle. To understand why,
consider the timing diagram of Figure 2-9. The timing roles of the VMEbus specification
require that slavesjoNosU)^ after the data strobe is
asserted. Once the slave asserts DTACK*f however, the master may immediately negate
AS* and change the address lines. If the address lines are not latched9 the module could be
de-selected in the middle of the cycle. If this happened during a read cycle the module
could torn off its data transceiver and conupt the data latched by a master*
Figure 2-9. Bus timing shows why slaves should latch address lines.
The 8-bit I/O module uses DSO* to latch the addresses instead of AS*. If a slave does not
support address pipelining (it mest always tolerate those cycles), it may latch its address
lines using either of these* Using the falling edge of DSO* instead of AS* in this case
simplifies the design of the module.
The master may negate and then re-assert AS* immediately after DTACK* is asserted by
the slavef as Figure 2-9 shows. This is also known as address pipelining or address rot.
If the address were latched on the falling edge of AS*f and a second falling edge occurred
before the end of the cycle, it could cause the module to turn off its output driver during a
read cycle. During a write cycle it could latch unwanted data.
Since the 8-bit I/O module is a D08(O) slave, data is written and read over DQG-DG7 (see
Table 2-5). This means that the module can be written to one byte at a time at odd
addresses, and that only DSO* need be used. By strict interpretation of the VMEbus
specification this circuit is actually a A16:B32:B16:BG8(G) slave because it does not decode
DS1* and LWORD*? and responds to D32 and D16 cycles. If the board is presented with
D32 or D16 cycles it will still respond but will ignore all data lines other than D00-D07.
For example, during read cycles the backplane termination networks pull all the data lines
up, during write cycles unused data lines are ignored.
Input data is read from a 74F374 octal flip-flop (U6). This circuit was set up so it latches
data at the falling edge of every data strobe, and holds it steady while the master reads it.
Any metastable glitches at the output of U6 will damp out before the master latches the data
Chapter 2 - Data Transfers 57 Handbook
(from the delays on U2 and U8). Data Is held at the output of the device until the master
negates data strobe DSO*.
A write cycle is similar except that data is latched using octal flip-flop U7* Data is latched
before the module asserts DTACK* because the master is pennitted to change the datelines
immediately after the slave asserts DTACK*,
When evaluating'or designing VMEbus modules, the driver and receiver characteristics of
the interface ICs must be closely checked. For examplef the circuit of Figure 2-8 asserts
DTACK* with a 74F38 open-collector driver. The data lines, however, are driven with a
74F374 which has standard 3-state outputs. For more information on interface
characteristics see Chapter 6.
By strict interpretation of the diagrams in the VMEbus specification, this module should
monitor SYSRESET*. Since that signal would perform no useful function on the board, it
was not used. During system reset this module is required to negate DTACK*, and stop
driving data lines DQ0-DG7 within 30 microseconds after SYSRESET* is asserted Since
masters are required to negate the data strobes after only 20 microseconds, and this circuit
resets itself every time the data strobes are negated, the monitoring of SYSRESET* is
useless. For more information on system reset refer to Chapter 5.
23 Circuit Example - A simple 16-bit Memory Module
A 16-bit memory module with 16 Kbytes of memory is shown in Figure 240* This circuit
has an A24:D16:D08(EO) interface. Address decoding is similar to that of the 8-bit parallel
I/O module except that it responds to A24 addresses and decodes more bits.
Table 2-7 shows the address modifiers to which it responds. Since there are four of them,
a programmable logic device (U6) is used as a decoder* The logic equations for this device
are shown in Figure 2-11. U6 asserts /STAM if IACK* and LWORD* are both negated,
and an A24 address.modifier is detected Flip-flop U4 then latches /STAM after the falling
edge of either data strobe (signal CYC).
The lower VMEbus addresses are latched by U10 and Ul 1 on the falling edge of either data
strobe. Address bits A16-A23 are compared to the base address select switch using Ul,
whose output is latched with U4. Since it responds to A24 addresses it does not decode
address lines A24-A31 •
Those unfamiliar with programmable logic may wish to consult the tutorial given at the end
of this chapter (MMI). The logic equations are not hard to understand though. Those
given in Figure 2-11 are written in PALASM™. Here the state of each output (on the left
side of the equal sign) is asserted or negated depending upon the state of the inputs (on the
right side of the equal sign). The Boolean operators of AND (*), OR (+) and NOT (/) can
be-used in the equations. For example, the equation for the latching signal CYC is:
Chapter 2-Data Transfers 58 The VMEbus Handbook
Table 2-7» Address modifier codes for 16-bit memory module.
M M M M M M
5 4 3 2 1 0
$3E 1 1 1 1 1 0 Standard Supervisory Program
$3D 1 1 1 1 0 1 Standard Supervisory Data
$3A 1 1 1 0 10 Standard Non-Privileged Program
$39 1 1 1 0 0 1 Standard Non-Privileged Data
This means that the output (CYC) will go low if the inputs (DS0 and DSl) are both high.
Schematically it would be the same as the circuit of Figure 2-12.
Figure 2=12. Circuit which dees the same function as
PLD equation /CYC = DS0 * DS1.
Because the PLD does not assert /STAM if LWORD* is asserted, the module will not
respond to D32 or to misaligned cycles (see Table 2-5). Only single and double byte cycles
are accepted. The byte locations that data is read from or written to is controlled by the
level of data strobes DS0* and DS1*. These, plus the state of the WRITE* signal, are
used to control /OE, WE0f WEI and BTACK*. The module will accept D16 as well as
Data is buffered to and from the memory ICs using 74LS645A-1 bus transceivers U13 and
U14. These supply the 48 mA drive current required by the VMBbos specification.
The cycle time of the memory ICs is confrolled by delay line U5.
By strict interpretation of the diagrams in the VMEbus specification, this module should
monitor SYSRESET*. Since that signal would perform no useful function on the boards it
was not used. During system reset this module is required to negate DTACK* and stop
driving data lines DGG-B15 within 30 microseconds after SYSRESET* is asserted Since
masters are required to negate the data strobes after only 20 microseconds, and this circuit
resets itself every time the data strobes are negated, the monitoring of SYSRESET* is
useless. For more information on system reset refer to Chapter 5.
Chapter 2 - Data Transfers 61 The VMEbus Handbook
TITLE ADDRESS DECODER CONTROL
PATTERN VH0004. PDS
AUTHOR WADE PETERSON
COMPANY CC) 1988 WADE PETERSON. ALL RIGHTS RESERVED
DATE JANUARY 29, 1988
CHIP DECODE PAL16L8
AL AM5 LST AM4 AMD AM3 IACK AMI LWORD 6ND
OE BDS1 BDSO DSO DS1 BDSEL DTK CYC STAM VCC
; VJffiBUS CYCLE SELECT
/CYC = DSO * DS1
; BUFFERED DATA STROBES
/BDSO = DSO
/BDS1 = DS1
; BOARD SELECT
/BDSEL = /LST * /AL
/DTK = BDSEL
; STANDARD ADDRESS MODIFIER DECODE
/STAM = IACK * LWORD * AM5 * AM4 * AM3 * Mil * /AMO
+ IACK * LWORD * AM5 * AM4 * AM3 * /AMI * AMD
Figure 2-11. Logic equations for U6 in Figure 2-10.
Chapter 2 - Data Transfers 62 Hie VMEbus Handbook