The document discusses failure analysis techniques in semiconductor IC development, emphasizing both electrical and physical analysis to improve yield before mass production. It details various methods such as X-ray, EMMI, and OBIRCH, alongside specific case studies highlighting failure modes and the importance of design and equipment performance. Additionally, it serves as training material for new workers, showcasing best practices and innovative approaches in failure analysis.

1. FAILURE ANALYSIS FOR YIELD
improve yield at the very beginning stage of IC
development and enter mass production
sat, obirch, emmi, cross section, correlation, process
control spec, defect map, mask design leakage current
CH Shen
沈志豪

2. Scenario 1
2
Define
Problem
capacit
ance
design
process
window
leakage
resistan
ce
equipm
ent
control
spec
mapping &
correlation
design of
experiment
confirm
failure
mode
EMMI
OBIRC
H
SEM
physical
electrical

3. Scenario 2
3
Pin-Pin
leakage
Check I-V curve (Fail)
Check X-ray (good)
Check SAT (good)
Thermal EMMI (found
leak spot)
De-cap
OM check die sensor (good)
OM check wire bond (good)
OM check die pad (good)
Check IV curve (good)
Symptom
Symptom disappeared
Check I-V (fail)
symptom repeated
Found fail path
repeat failure
mechanism
confirm failure mode
Measur
e &
Analyze

4. This is to prepare training course material for new onboard fellow workers who
interest in failure analysis technique of semiconductor IC.
Some irrelevant parameters, names, dates, and details have been removed for
better understanding and focus on key considerations.
In this report, a lot of attention is given to establishing the thinking process and
experience-based instinct. This is one of best failure analysis reports I have
ever working alone and excellent ideas from third party laboratories and test
program compilers.
What makes the failure analysis distinct is innovative skill and knowledge of
physical/chemical theory. Accumulation of tons of failure analysis experience
grows good quality instinct determining how effective process will be.
Cheers,
CH Shen
4

5. 1. Failure analysis
a. Electrical failure analysis
1. Check mask design (NPI)
2. Check COB image (NPI)
3. Check CP test spec (NPI)
4. Check I-V Measurement
5. Check fail bin def.
6. Check wafer map
7. Check wafer odd/even
8. Check relevant WAT
9. Check relevant inline chart
10. Check “sensor pixels” (FPS)
b. Physical failure analysis
1. X-ray, SAT/SAM
2. De-capsulation
3. OBIRCH analysis
4. EMMI analysis
5. FIB/SEM/TEM analysis
6. EDX Analysis
7. Auger analysis

6. • Principle:
Measurement is base on the comparison of
reflected echoes. Ultrasonic waves is
generated by vibrations (probe), trigger by a
pulse voltage.
• Main features:
o If there’s an air gap at least 5nm, it can be
detected easily even at frequency 15Mhz.
o Minimum detectable defect size is roughly
half the diameter of probe beam.
o Higher frequency has higher both surface
resolution and depth resolution.
• Preparation
o Cross-check the first time measurement.
o Ascertain the suitable frequency.
1.Scanning Acoustic Tomography
principle
Acoustic impedance (Z)= density of the sample
* sound speed of the sample
Z2 - Z1
The reflectivity R is: -------------
Z2 + Z1
for example:
Si Z=20.4, resin Z=6.76, air Z=0, H2O Z=1.48
R air->water: (1.48-0)/(1.48+0)=1
it’s another way to explain immersed probe.

7. principle
• ΔI= (ΔR/R)I.
Converting the value of current change into brightness change of
pixels in the image and recording the position, The pixel positions
can then be overlapped with the positions scanned by the laser
beam where the current changes.
• Detect the following defects:
Metal short/bridge. Gate oxide pin hole. Active area short. Poly
short or contact spiking. Well short or source / drain short. Higher
via / contact / metal / poly / AA resistance fail. Any IC failure (short
or bridge or leakage or high resistance) associated with a
differential material or its thickness.
1.Physical failure analysis (OBIRCH)

8. VDD33_1 to GND
case study
Process: 1P6M, 0.18um
Failure History: Chip allay fail.
1.Physical failure analysis (OBIRCH)

9. principle
• Detects 350 nm ~ 1100 nm.
Highly-sensitive CCD capable of detecting photons emitted when
the electron/electric-hole pair reunites in the device.
• Detect the following defects:
Junction Leakage; Contact spiking; Hot electrons; Latch-Up; Gate
oxide defects / Leakage(F-N current); Poly-silicon filaments;
Substrate damage; Mechanical damage and Junction Avalanche;
etc. (Limitation: Defects without light spots - Ohmic shorts and Metal
shorts. OR Light spots being blocked - Buried Junctions and
Leakage sites under metals.)
1.Physical failure analysis (EMMI)

10. case study
Process: 1P6M, 0.18um
Failure History: Chip allay fail.
1.Physical failure analysis (EMMI)
VDD33_1 to GND

11. case study
Focused Ion (Ga+) Beam
1.Physical failure analysis (FIB)
Cross-section
1 2
3 4

12. Shmoo plotting check voltage, clock,
temperature, etc. Optimize the process
parameter windows and final test condition.
Sample wafer: #14[TT]
Test voltage: VDD33A2, 3.0V~3.6V Ramp-up: 50mV.
2. Identify failure mode
The failure mode can be marginal design issue.

13.  M6 A/B ver WAT comparison: RSM6 is comparable
RSM6
T ID:PHRG0.1 conditioin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
S1223-4U75B1 o o o o o o o o o o o o o o o o o o o o o o
S1223-4U75A1 v v v
M6 mask split
2. Identify failure mode
The failure mode can be metal resistance issue.
SpecH :1.0E-6

14.  Major failure are Bin9, Bin7, Bin13, Bin28, Bin29.
 Bin7 with 2N characteristic.
ODD
EVEN
Compositemap
2. Identify failure mode
The failure mode can be equipment performance issue.

15.  Check lot history with 2N, Now commonality show TMET etcher MET11B
VIA1 etch
TMET etch
lot A
lot A
lot A
lot B
MET11B
MET11B
2. Identify failure mode
The failure mode can be equipment performance issue.

16. Process: MIXED_MODE18-1.8V/3.3V-1P6M-80UM. The
passivation thickness is different from generic 0.18um.
The IMD thickness designed for capacitance characters.
2. Identify failure mode
The failure mode can be process spec limit issue.

17. Good die TEM images CD measurement
EdgeCenter
EdgeCenter
Bad die TEM images CD measurement
Obviously, the dielectric thickness deviation
is the main contribution to capacitance. The
IMD5 thickness has unacceptable variation
within wafer and within die.
3. Verify failure mode

18. 4. Develop failure analysis
defect distribution analysis

19. parameter correlation analysis
挑選
PCM
與CP
關連
晶片
PCM V.S. Yield
Auto
ranking
based on
R-Square
4. Develop failure analysis

20. 5. Validate the design of experience
Group 4
Standard Flow
Group 3
IMD Window
change
Group 2
passivation
change
Group 1
mask change
G1
G2
G3 G4