The document discusses several topics related to semiconductor manufacturing processes and design for manufacturability (DFM). It summarizes resolution enhancement techniques used in lithography like RET and OPC. It also discusses DFM techniques like process characterization of IP libraries using yield models, addressing systematic and random yield loss mechanisms, and the need for proactive DFM using accurate process models early in the design flow. Finally, it briefly mentions the use of automated test equipment for testing chips after manufacturing.

1. BY V.P.SAMPATH
EDA TECH MEMBER

2.  Blessings frommy great revered teachers
 Dr.E.Janardhanan B.tech M.S(USA) PhD(USA),Former
Isro Scientist,SeniorProf,SSN College of
Engineering,Chennai.
 Dr.Kaliyugavardan Phd,Visiting Professor,University of
Minnesota,USA

3. Market share

11.  Resolution Enhancement Technology (RET)
 Resolution Enhancement Technology, first used in the 90 nanometer
generation, using the mathematics of diffraction optics to specify multi-
layer phase-shift photomasks that use interference patterns in the
photomask that enhance resolution on the printed wafer surface.
 Optical Proximity Correction (OPC)
 Optical proximity correction uses computational methods to counteract the
effects of diffraction-related blurring and under-exposure by modifying
on-mask geometries with means such as:
 adjusting linewidths depending on the density of surrounding geometries
(a trace surrounded by a large open area will be over-exposed compared
with the same trace surrounded by a dense pattern)
 adding "dog-bone" endcaps to the end of lines to prevent line shortening
 correcting for electron beam proximity effects

13.  Chemical Mechanical Polishing/Planarization is a
process of smoothing surfaces with the combination of
chemical and mechanical forces, it can be thought of as
a hybrid of chemical etching and free abrasive polishing.

17. Critical area analysis

18.  IC realibility issues
 Predict reliability failures.
 Analyses physical layout of a chip and computes the
total area where shorts and opens could occur when the
center axis of a random particle occurs in that area.

21.  The scanning electron microscope (SEM) is a type of
electron microscope that images the sample surface by
scanning it with a high-energy beam of electrons in a
raster scan pattern. The electrons interact with the
atoms that make up the sample producing signals that
contain information about the sample's surface
topography, composition and other properties such as
electrical conductivity

25.  Extreme ultraviolet lithography (also known as EUV or
EUVL) is a next-generation lithography technology using
an EUV wavelength, currently expected to be 13.5 nm.

27.  Sub resolution assist features.
 Sub Resolution Assist Features (SRAFs) or scatter bars
are added to the mask to allow isolated features diffract
light as dense features but they do not print. Adding
SRAFs to intermediate pitches can be tough resulting in
suboptimal printing performance for these features.

29. GoalsGoals ToolsTools
DefineDefine Obtain customers needs and wantsObtain customers needs and wants
Translate customers needs andTranslate customers needs and
wants to VOC listwants to VOC list
Market/Customer Research, KanoMarket/Customer Research, Kano
analysis, stakeholders analysis,analysis, stakeholders analysis,
operation cross walkoperation cross walk
Concept DevelopmentConcept Development Develop Design Feature/functionalDevelop Design Feature/functional
requirements based on VOCrequirements based on VOC
QFD. TRIZ, Axiomatic DesignQFD. TRIZ, Axiomatic Design
Design DevelopmentDesign Development Identify engineering and processIdentify engineering and process
parameters based on the designparameters based on the design
features/functional requirementsfeatures/functional requirements
CTX, DFX, DOE, TaguchiCTX, DFX, DOE, Taguchi
methodsmethods
Optimize DesignOptimize Design Identify optimal settings for theIdentify optimal settings for the
engineering and process parametersengineering and process parameters
based on the performance,based on the performance,
robustness, production and otherrobustness, production and other
requirements.requirements.
RSM, FMEA update, sensitivityRSM, FMEA update, sensitivity
analysis, Taguchi Methodsanalysis, Taguchi Methods
Verify CapabilityVerify Capability Establish the designedEstablish the designed
product/process is capable ofproduct/process is capable of
meeting the design target andmeeting the design target and
requirements.requirements.
Verification/qualification tests,Verification/qualification tests,
validation tests, simulation,validation tests, simulation,
statistical analysisstatistical analysis

31.  Determine criticality of a part
 a part is critical if
 - move relative to all other parts already assembled,
or
 - different material than all being assembled
 - separated from other parts assembled.
 Physical coupling of “un-critical” parts with a
“critical part”
 Reassess assembly time for new configured
parts
 Analyze the manufacturability of new configured

32. Dfma

33.  Total actual assembly Time T1= 163 s
 Theoretical total part count is 4 and average assembly time is 3 s.
Theoretical assembly time T2= 4 x 3 s = 12 s
 Calculate Design Efficiency :


 or 7.362%

34. Design guides
 Minimize the number of setup and stages.
 Analyze the existing manufacturing and assembly function.
 Revisit the physical structure (of the design) which
customize to the local processing capability
 Apply the most appropriate (not latest) technology.
 Use Axiomatic design to create Modular design of the
parts.
 Design for minimum number of parts using physical
coupling
 Choose the appropriate material for easy manufacturing
 Apply the layer assembly principles.

35. Technology Roadmap
Challenges
65nm
 Lithography
 OPC/PSM integr. w/
photo-window
 Front-end/Transistor
 Layout dependent
performance
 Parametric variation
65nm
 Lithography
 OPC/PSM integr. w/
photo-window
 Front-end/Transistor
 Layout dependent
performance
 Parametric variation
45nm
 Lithography
 Layout pattern
dependence
Immersion litho,
OPC/PSM integration
w/ photo window
 Front end/Transistor
New gate/oxide
architectures
 Reliability
45nm
 Lithography
 Layout pattern
dependence
Immersion litho,
OPC/PSM integration
w/ photo window
 Front end/Transistor
New gate/oxide
architectures
 Reliability
90nm
 Back-end integration
Low-k
CMP
 Product ramp issues
Yield vs.
performance
90nm
 Back-end integration
Low-k
CMP
 Product ramp issues
Yield vs.
performance

36.  Random defects are no longer the dominantRandom defects are no longer the dominant
yield loss mechanismyield loss mechanism
 Yields are limited by design featuresYields are limited by design features
Yield Limiters by Technology Node
40%
50%
60%
70%
80%
90%
100%
0.8um
0.5um
0.35um
0.25um
0.18um
0.13um
90nm
Technology
Yield
Random Defect Limited Yield
Design Feature Limited Yield
Total Yield
The Evolution of Product Yields

37.  The Copernican Revolution refers to the paradigm shift
away from the Ptolemaic model of the heavens, which
postulated the Earth at the center of the universe,
towards the heliocentric model with the Sun at the
center of our Solar System. It was one of the starting
points of the Scientific Revolution of the 16th Century.

38. From Reactive to Proactive DFM:
A Copernican Revolution…
 Accurate Yield Models
Characterized
in Silicon
 Fully integrated in standard
design tools and flows
 Design rules guarantee yield!…
well, not really…
 …then recommended rules
 …and opportunistic design data
base post-processing to enforce
them
Yield Revolved Around Rules
Yield Models are the driving force in the DFM universe

39. Rule-based DFM?
MUX4X1AFY_Y1 - 20 tracks
MUX4X1AFY_COY4 - 25 tracksMUX4X1AFY_PMSY4 - 21 tracks
MUX4X1AFY1_Y16 - 27 tracks
32 FPB32 FPB
19 FPB19 FPB
20 FPB20 FPB25 FPB25 FPB

40. Proactive DFM
 Designer access to process data is limited
 DFM today is Reactive
 Increased design cycle time
 Risky design feature changes
 Misaligned mask GDSII and design database
 DFM needs to be Proactive
 Up-front accurate process characterization
 Occurring early in the design flow
 Model based IP characterization
 Manufacturable -by-co nstructio n designs

41. DFM characterization Of IP
libraries
 Characterize IP library for yield (.pdfm)
 Extract design attributes of yield models
 Include random, design systematic and
litho effects
 New yield library view (.pdfm)
 Enable hierarchical large capacity DFM chip analysis
Design SYSTEMATIC

42. Random Yield Loss: Physical
Mechanisms
Contact and via opens due to formationContact and via opens due to formation
defectivitydefectivity
Active, poly and metal shorts and opensActive, poly and metal shorts and opens
due to particle defectsdue to particle defects
RandomRandom
Yield Loss MechanismsYield Loss MechanismsTypeType
MaterialMaterial
opensopens
MaterialMaterial
shortsshorts

43. Random Yield Loss: Test
Structures
 Extract Metal layer open
and short defectivity  Extract Metal layer openExtract Metal layer open
and short Defect Sizeand short Defect Size
Distribution (DSD)Distribution (DSD)

44. Systematic Yield Loss: Physical
Mechanisms
Misalignment, line-ends/bordersMisalignment, line-ends/borders
Contact/via opens due to local neighborhoodContact/via opens due to local neighborhood
effects (e.g. pitch/hole size)effects (e.g. pitch/hole size)
Leakage from STI related stressLeakage from STI related stress
Impact of micro/macro loading design ruleImpact of micro/macro loading design rule
marginalitiesmarginalities
SystematiSystemati
cc
Yield Loss MechanismsYield Loss MechanismsTypeType
Failure Rate
0
20
40
60
80
100
120
140
160
0.4 1.8 4.2 9
Pitch (um)
ViaFailureRate(fpb)

45. Systematic Yield Loss: Test
Structures
Without Neighborhood With Neighborhood
STI
M1
To Pad A To Pad B To Pad C
N+
PWL
N+ P+

46. Printability Yield Loss: Physical
Mechanisms
Material opensMaterial opens
Poor contact coverage due to misalignment andPoor contact coverage due to misalignment and
defocus/pull backdefocus/pull back
SystematicSystematic
Yield Loss MechanismsYield Loss MechanismsTypeType
Poly/Metal shortsPoly/Metal shorts

47. Printability Yield Loss: Modeling
Process Margin
0
0.2
0.4
0.6
0.8
1
1.2
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
Spacing
Yield
0
0.05
0.1
0.15
0.2
0.25
0.3
p(spacing)
LayoutLayout
MetricMetric
MisalignmentMisalignment
Mask Error
Mask Error
Defocus
Defocus
Exposure
Exposure
Yield Loss
Defocus
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Misalignment
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
−3.0
σ
−2.5
σ
−2.0
σ
−1.5
σ
−1.0
σ
−0.5
σ
0.0
σ
0.5
σ
1.0
σ
1.5
σ
2.0
σ
2.5
σ
3.0
σ
Exposure
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
coverage

48. The .pdfm View
 Library characterized to
generate manufacturability
view (.pdfm)
 Random and design
systematic yield
 Litho process window
 Using calibrated yield models
 Multi-layer litho process
window incorporated
Cell
Characteristic
Library
View
Lay out GDS
Schematic SPICE
Netlist
P&R Footprint LEF
Performance .lib
Logic Function Verilog
Power
Noise
… …
Manufacturabilit
y
.pDFM

49. Yield aware synthesys and
place&route
 Proactive DFM
 Maximize manufacturability by construction
RTL Design
Hierarchical
Floorplan
Physical
Synthesis
Chip Assembly
Sign-off
VERIFICATION
Models
Yield Gap
Estimator
Yield
Optimizer Extended IP
Yield ModelsYield
Estimation
Yield
Optimization
DFM SW plug-ins Yield View (.pdfm)
DFM
LIBRARIES
Standard Libraries

50.  Impact of design systematic and lithography
yield loss mechanisms crossed over random
phenomena
 Rule-based, reactive DFM is impractical
 Model-based, proactive DFM is the answer
 Early in the design flow
 Find the best trade-off based on actual process
capabilities
 Before verification

60.  LFD is the first production-proven EDA tool to
address the urgent issue of how to manage
lithographic process variability in the early
stages of design creation. Calibre LFD
accurately models the impact of lithographic
processes on “as-drawn” layout data to
determine the actual “as-built” dimensions of
fabricated gates and metal interconnects.

70. ATE
 Manufacturing test and failure analysis remain at the
forefront of determining why and how chips fail.
Defective chips (i.e., those that fail the production test)
offer a goldmine of information. If properly mined, they
can provide valuable insight into the defects and failure
mechanisms that are limiting yield. The industry
standard for testing digital integrated circuits (ICs) after
manufacturing is to place them into a piece of
automated test equipment (ATE). Various logic test
patterns are then run on them to find defects in the
circuit. This process is scan test. Most of the test
patterns are created by an automated-test-pattern-
generation (ATPG) tool. This tool is based on fault
models, which are designed to model the various
failure behaviors that are found in the ICs when defects
are present.

78. Thanks