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Research Advance04032016
- 1. My Research Advanceduring February and April Supervisor :Prof. Lihong Zhang Lecturer: Zhongliang Zhou Date:04/04/2016
- 2. Overview Initial latency 21clk Inthe last lecture: • We gave a wireless sensor networks prototype based on Atmel’s Bitcloud solution In this lecture: • We will introduce an advanced version of prototype. • It integrate another zigbee solution :Xbee, which act as an coordinator and link routers for a larger network coverage • It is able to send information of WSNs through satellite communicate channels • Also It is capable of hardware encryption(AES algorithm)
- 3. 6 Sensor Nodes 1Router Nodes1 Coordinator Iridium 9603 Satellite Server And Antenna SOM Xbee The advanced prototype Router Nodes and Sensor Nodes are all under Atmel’s Bitcloud Zigebee procotol USB with Xbee UART with Iridium 9603
- 4. The network topologyunder XBEE software Xbee Coordinator Access Router Node Sensor Node Sensor Node Sensor Node Sensor Node Sensor Node Sensor Node • Access Router Node can support access up to 600 Sensor Nodes • Coordinator can only support up to 12 Sensor Nodes but unlimited in Router Node • Link Router Node(no shown in the fig)
- 5. Coordinator Router email Data flow ofthe system WSN Satellite End user
- 6. The embedded systemin SOM AES † † †† † † † Linux based multithreading program A hardware and software co-design embedded system
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- 8. The AES design PS PL AddressMap: AXI_Lite AXI_Full DMA Ctlr AES128 ARMAXI_Lite bus AXI_full bus Just highlight the AES part
- 9. The AES core TheAES core is an hardware open source from: http://opencores.org/. The core support AES-128, AES- 192 and AES-256 encryption separately, we used AES-128bit mode.The maximum frequency is 324.6 MHz. The throughput is 37.5 G bytes/second if with a 300 MHz clock. The features are as follows. Pipeline architecture Only one clock domain in entire core No latch Vendor-independent code calculation latency 21clk Initial latency 21clk
- 10. The AXI bus TheAXI4 (Advanced eXtensible interface), based on the ARM, Ltd. AMBA bus Architecture, is a performance optimized point-to-point bus interconnect technology for system on-chip design. AXI4 burst write
- 11. Results Real AXI Bustranscations burst Write and Read 224bytes, real signals catch from the internal by hardware debugger
- 12. The software architecture RB-treeis highly scalable High efficiency for node search, add, delete Achieve best performance for maintaining up to 64K node Link list is used to traverse • Extracting Sensor data from message bittream • Packaging Sensor data into a satellite message • interThread Circular buffer read and write Thread 1 • Managing a RB node tree • Every RB node is correspond to a WSN node • interThread Circular buffer read and write Thread 2 Thread 3 typedef struct _WSN_MonData { uint8_t read_flg; ShortAddr_t; ShortAddr_t pareshortAddrntShortAddr; ExtAddr_t extAddr; GPS_LOC_t gps_loc; uint64_t loc_tm; int32_t battery; int32_t temperature; /*new types of monitor can adder here*/ }WSN_MonData_t; • Managing the satellite communication status • Sending Sensor data message when satellite is available • Sensor data message AES encryption Circular buffer for MonData
- 13. Software: Petalinux linux SDK:for linux kernel/driver configuration/bootloader setup XSDK: for linux based programming/debugging SW-HW co-debug Hardware: Vivado: for FPGA hardware synthesis/implementation/debug SW-HW co-debug Development tool chain
- 14. • enclosure forWSN nodes • Backend database and User interface(UI) to display statistic sensor data • Downstream link(message path from users to every nodes in WSNs) Works to do
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