This document analyzes the performance of lattice quantum chromodynamics (QCD) simulations using the asynchronous partitioned global address space (APGAS) programming model on GPUs. It implements lattice QCD in X10 CUDA and compares performance to other implementations. Results show a 19.4x speedup from using X10 CUDA on 32 nodes of the TSUBAME 2.5 supercomputer compared to the original X10 implementation. Optimizations like data layout transformation and communication overlapping contributed to this acceleration.
Parallel Implementation of K Means Clustering on CUDAprithan
K-Means clustering is a popular clustering algorithm in data mining. Clustering large data sets can be
time consuming, and in an attempt to minimize this time, our project is a parallel implementation of KMeans
clustering algorithm on CUDA using C. We present the performance analysis and implementation
of our approach to parallelizing K-Means clustering.
customization of a deep learning accelerator, based on NVDLAShien-Chun Luo
This document discusses customizing a deep learning accelerator. It begins with a demonstration of object detection using a Tiny YOLO v1 model on an FPGA-based prototype. It then discusses designing a high-efficiency accelerator with three steps: 1) increasing MAC processing elements and utilization, 2) increasing data supply, and 3) improving energy efficiency. Various neural network models are profiled to analyze memory bandwidth and computational power tradeoffs. The document proposes a customizable architecture and discusses solutions like layer fusion, quantization-aware training, and post-training quantization. Performance estimates using an equation-based profiler for sample models are provided to demonstrate the customized accelerator design.
Performance Analysis of Lattice QCD with APGAS Programming ModelKoichi Shirahata
The document analyzes the performance of a lattice quantum chromodynamics (QCD) application implemented using the Asynchronous Partitioned Global Address Space (APGAS) programming model in X10. It finds that the X10 implementation achieves a 102.8x speedup in strong scaling up to 256 places. However, the MPI implementation outperforms X10, being 2.26-2.58x faster due to more optimized communication overlapping in MPI. Analysis shows the X10 implementation suffers overhead from thread activation and synchronization. Communication using one-sided operations also outperforms two-sided in X10. The work contributes an X10 implementation of lattice QCD and evaluates its scalability and performance compared to MPI.
We updated the DLA system introductions here, from design, add-on functions, and applications. During the 2018~2019, we developed the tools needed for IC simulation and verification, constructed a quantize-aware & HW-aware training flow, and improved the automation of the verification. We have verified this system through FPGA and solid-state SoC.
The search for faster computing remains of great importance to the software community. Relatively inexpensive modern hardware, such as GPUs, allows users to run highly parallel code on thousands, or even millions of cores on distributed systems.
Building efficient GPU software is not a trivial task, often requiring a significant amount of engineering hours to attain the best performance. Similarly, distributed computing systems are inherently complex. In recent years, several libraries were developed to solve such problems. However, they often target a single aspect of computing, such as GPU computing with libraries like CuPy, or distributed computing with Dask.
Libraries like Dask and CuPy tend to provide great performance while abstracting away the complexity from non-experts, being great candidates for developers writing software for various different applications. Unfortunately, they are often difficult to be combined, at least efficiently.
With the recent introduction of NumPy community standards and protocols, it has become much easier to integrate any libraries that share the already well-known NumPy API. Such changes allow libraries like Dask, known for its easy-to-use parallelization and distributed computing capabilities, to defer some of that work to other libraries such as CuPy, providing users the benefits from both distributed and GPU computing with little to no change in their existing software built using the NumPy API.
Achitecture Aware Algorithms and Software for Peta and Exascaleinside-BigData.com
Jack Dongarra from the University of Tennessee presented these slides at Ken Kennedy Institute of Information Technology on Feb 13, 2014.
Listen to the podcast review of this talk: http://insidehpc.com/2014/02/13/week-hpc-jack-dongarra-talks-algorithms-exascale/
The document summarizes four presentations from the USENIX NSDI 2016 conference session on resource sharing:
1. "Ernest: Efficient Performance Prediction for Large-Scale Advanced Analytics" proposes a framework that uses results from small training jobs to efficiently predict performance of data analytics workloads in cloud environments and reduce the number of required training jobs.
2. "Cliffhanger: Scaling Performance Cliffs in Web Memory Caches" presents algorithms to dynamically allocate memory across queues in Memcached to smooth out performance cliffs and potentially save memory usage.
3. "FairRide: Near-Optimal, Fair Cache Sharing" introduces a caching policy that provides isolation guarantees, prevents strategic behavior, and
The document discusses dense linear algebra solvers and algorithms. It provides an overview of existing software for dense linear algebra including LINPACK, EISPACK, LAPACK, ScaLAPACK, PLASMA, and MAGMA. It then discusses challenges with dense linear algebra on modern hardware including distributed memory, heterogeneity, and the high cost of communication. It introduces tile algorithms as an approach to address these challenges compared to traditional LAPACK algorithms.
Parallel Implementation of K Means Clustering on CUDAprithan
K-Means clustering is a popular clustering algorithm in data mining. Clustering large data sets can be
time consuming, and in an attempt to minimize this time, our project is a parallel implementation of KMeans
clustering algorithm on CUDA using C. We present the performance analysis and implementation
of our approach to parallelizing K-Means clustering.
customization of a deep learning accelerator, based on NVDLAShien-Chun Luo
This document discusses customizing a deep learning accelerator. It begins with a demonstration of object detection using a Tiny YOLO v1 model on an FPGA-based prototype. It then discusses designing a high-efficiency accelerator with three steps: 1) increasing MAC processing elements and utilization, 2) increasing data supply, and 3) improving energy efficiency. Various neural network models are profiled to analyze memory bandwidth and computational power tradeoffs. The document proposes a customizable architecture and discusses solutions like layer fusion, quantization-aware training, and post-training quantization. Performance estimates using an equation-based profiler for sample models are provided to demonstrate the customized accelerator design.
Performance Analysis of Lattice QCD with APGAS Programming ModelKoichi Shirahata
The document analyzes the performance of a lattice quantum chromodynamics (QCD) application implemented using the Asynchronous Partitioned Global Address Space (APGAS) programming model in X10. It finds that the X10 implementation achieves a 102.8x speedup in strong scaling up to 256 places. However, the MPI implementation outperforms X10, being 2.26-2.58x faster due to more optimized communication overlapping in MPI. Analysis shows the X10 implementation suffers overhead from thread activation and synchronization. Communication using one-sided operations also outperforms two-sided in X10. The work contributes an X10 implementation of lattice QCD and evaluates its scalability and performance compared to MPI.
We updated the DLA system introductions here, from design, add-on functions, and applications. During the 2018~2019, we developed the tools needed for IC simulation and verification, constructed a quantize-aware & HW-aware training flow, and improved the automation of the verification. We have verified this system through FPGA and solid-state SoC.
The search for faster computing remains of great importance to the software community. Relatively inexpensive modern hardware, such as GPUs, allows users to run highly parallel code on thousands, or even millions of cores on distributed systems.
Building efficient GPU software is not a trivial task, often requiring a significant amount of engineering hours to attain the best performance. Similarly, distributed computing systems are inherently complex. In recent years, several libraries were developed to solve such problems. However, they often target a single aspect of computing, such as GPU computing with libraries like CuPy, or distributed computing with Dask.
Libraries like Dask and CuPy tend to provide great performance while abstracting away the complexity from non-experts, being great candidates for developers writing software for various different applications. Unfortunately, they are often difficult to be combined, at least efficiently.
With the recent introduction of NumPy community standards and protocols, it has become much easier to integrate any libraries that share the already well-known NumPy API. Such changes allow libraries like Dask, known for its easy-to-use parallelization and distributed computing capabilities, to defer some of that work to other libraries such as CuPy, providing users the benefits from both distributed and GPU computing with little to no change in their existing software built using the NumPy API.
Achitecture Aware Algorithms and Software for Peta and Exascaleinside-BigData.com
Jack Dongarra from the University of Tennessee presented these slides at Ken Kennedy Institute of Information Technology on Feb 13, 2014.
Listen to the podcast review of this talk: http://insidehpc.com/2014/02/13/week-hpc-jack-dongarra-talks-algorithms-exascale/
The document summarizes four presentations from the USENIX NSDI 2016 conference session on resource sharing:
1. "Ernest: Efficient Performance Prediction for Large-Scale Advanced Analytics" proposes a framework that uses results from small training jobs to efficiently predict performance of data analytics workloads in cloud environments and reduce the number of required training jobs.
2. "Cliffhanger: Scaling Performance Cliffs in Web Memory Caches" presents algorithms to dynamically allocate memory across queues in Memcached to smooth out performance cliffs and potentially save memory usage.
3. "FairRide: Near-Optimal, Fair Cache Sharing" introduces a caching policy that provides isolation guarantees, prevents strategic behavior, and
The document discusses dense linear algebra solvers and algorithms. It provides an overview of existing software for dense linear algebra including LINPACK, EISPACK, LAPACK, ScaLAPACK, PLASMA, and MAGMA. It then discusses challenges with dense linear algebra on modern hardware including distributed memory, heterogeneity, and the high cost of communication. It introduces tile algorithms as an approach to address these challenges compared to traditional LAPACK algorithms.
Exploring Compiler Optimization Opportunities for the OpenMP 4.x Accelerator...Akihiro Hayashi
Third Workshop on Accelerator Programming Using Directives (WACCPD2016, co-located with SC16)
While GPUs are increasingly popular for high-performance
computing, optimizing the performance of GPU programs is a time-consuming and non-trivial process in general. This complexity stems from the low abstraction level of standard
GPU programming models such as CUDA and OpenCL:
programmers are required to orchestrate low-level operations
in order to exploit the full capability of GPUs. In terms of
software productivity and portability, a more attractive approach
would be to facilitate GPU programming by providing high-level
abstractions for expressing parallel algorithms.
OpenMP is a directive-based shared memory parallel programming model and has been widely used for many years.
From OpenMP 4.0 onwards, GPU platforms are supported
by extending OpenMP’s high-level parallel abstractions with
accelerator programming. This extension allows programmers to
write GPU programs in standard C/C++ or Fortran languages,
without exposing too many details of GPU architectures.
However, such high-level parallel programming strategies generally impose additional program optimizations on compilers,
which could result in lower performance than fully hand-tuned
code with low-level programming models.To study potential
performance improvements by compiling and optimizing high-level GPU programs, in this paper, we 1) evaluate a set of
OpenMP 4.x benchmarks on an IBM POWER8 and NVIDIA
Tesla GPU platform and 2) conduct a comparable performance
analysis among hand-written CUDA and automatically-generated
GPU programs by the IBM XL and clang/LLVM compilers.
This document describes designing a real-time heat map service using Apache Storm. It involves collecting check-in data from various locations, geocoding the addresses, building heat maps for time intervals, and persisting the results. The key components are a check-ins spout to generate sample data, geocode lookup bolt to geocode addresses, heat map builder bolt to accumulate locations into intervals and emit maps, and persistor bolt to store results. Stream groupings and parallelism across workers allow the topology to horizontally scale for high throughput processing of location data.
CUDA performance study on Hadoop MapReduce Clusterairbots
This document summarizes a study on using GPUs (CUDA) to accelerate Hadoop MapReduce workloads. It introduces CUDA into Hadoop clusters, evaluates the performance speedup and power efficiency on matrix multiplication and molecular dynamics simulations, and concludes that GPU acceleration provides up to 20x speedup and reduces power consumption by up to 19/20, making it a cost-effective approach compared to CPU-only upgrades. Future work is outlined to port more applications and support heterogeneous GPU/CPU clusters.
FPGAs can compete with GPUs for some applications but with some key differences:
1) FPGAs are configured to create custom hardware for an algorithm rather than using predefined hardware like GPUs. This allows high efficiency but is more difficult to program.
2) While OpenCL provides a common language, FPGAs and GPUs have very different architectures and optimizing algorithms requires different approaches for each.
3) For applications with high bandwidth I/O or flexibility requirements, FPGAs may have advantages over GPUs, but GPUs typically have higher performance for compute-heavy applications and better energy efficiency. Overall, FPGAs have become more accessible but still require more programming effort than GPUs.
MapReduce: A useful parallel tool that still has room for improvementKyong-Ha Lee
The document discusses MapReduce, a framework for processing large datasets in parallel. It provides an overview of MapReduce's basic principles, surveys research to improve the conventional MapReduce framework, and describes research projects ongoing at KAIST. The key points are that MapReduce provides automatic parallelization, fault tolerance, and distributed processing of large datasets across commodity computer clusters. It also introduces the map and reduce functions that define MapReduce jobs.
Utilizing AMD GPUs: Tuning, programming models, and roadmapGeorge Markomanolis
A presentation at FOSDEM 2022 about AMD GPUs, tuning, programming models and software roadmap. This is continuation from the previous talk (FOSDEM 2021)
CC-4005, Performance analysis of 3D Finite Difference computational stencils ...AMD Developer Central
The document discusses performance analysis of 3D finite difference computational stencils on Seamicro fabric compute systems. It provides an overview of the hardware including chassis, compute cards, storage cards, and 3D torus fabric topology. It then describes the software stack and various microbenchmarks performed, including CPU, memory, network and storage benchmarks. It also describes modeling of 3D Laplace's equation using an 8th order finite difference scheme and its discretization over a 25 point stencil for computation on the system.
Designing High Performance Computing Architectures for Reliable Space Applica...Fisnik Kraja
This document summarizes Fisnik Kraja's PhD defense on designing high performance computing architectures for reliable space applications. Kraja proposed an architecture using parallel processing nodes connected via a radiation-hardened management unit. Benchmarking of the 2DSSAR image reconstruction application showed optimizing for shared memory, distributed memory, and heterogeneous CPU/GPU systems. The best performance was achieved using a heterogeneous node with a multi-core CPU and dual GPUs, providing a 34.46x speedup. Kraja's conclusions recommended a design using powerful shared memory parallel processing nodes each with CPUs, GPUs, and distributed memory only if multiple nodes are needed.
Direct3D 12 aims to reduce CPU overhead and increase scalability across CPU cores by allowing developers greater control over the graphics pipeline. It optimizes pipeline state handling through pipeline state objects and reduces redundant resource binding by introducing descriptor heaps and tables. Command lists and bundles further improve performance by enabling parallel command list generation and reuse of draw commands.
The document compares on-heap and off-heap caching options. It discusses heap memory usage in the JVM and alternatives like off-heap memory using memory mapped files, ByteBuffers, and Unsafe. Popular off-heap caches like Chronicle, Hazelcast, and Redis are presented along with comparisons of their features, performance, and garbage collection impact. The document aims to help developers choose the most suitable cache for their application needs.
For the full video of this presentation, please visit:
http://www.embedded-vision.com/platinum-members/arm/embedded-vision-training/videos/pages/may-2016-embedded-vision-summit-iodice
For more information about embedded vision, please visit:
http://www.embedded-vision.com
Gian Marco Iodice, Software Engineer at ARM, presents the "Using SGEMM and FFTs to Accelerate Deep Learning" tutorial at the May 2016 Embedded Vision Summit.
Matrix Multiplication and the Fast Fourier Transform are numerical foundation stones for a wide range of scientific algorithms. With the emergence of deep learning, they are becoming even more important, particularly as use cases extend into mobile and embedded devices. In this presentation, lodice discusses and analyzes how these two key, computationally-intensive algorithms can be used to gain significant performance improvements for convolutional neural network (CNN) implementations.
After a brief introduction to the nature of CNN computations, Iodice explores the use of GEMM (General Matrix Multiplication) and mixed-radix FFTs to accelerate 3D convolution. He shows examples of OpenCL implementations of these functions and highlights their advantages, limitations and trade-offs. Central to the techniques explored is an emphasis on cache-efficient memory accesses and the crucial role of reduced-precision data types.
The document discusses NVIDIA data center GPUs such as the A100, A30, A40, and A10 and their performance capabilities. It provides examples of GPU accelerated application performance showing simulations in Simulia CST Studio, Altair CFD, and Rocky DEM achieving excellent speedups on GPUs. It also discusses Paraview visualization being accelerated with NVIDIA OptiX ray tracing, further sped up using RT cores. Looking ahead, the document outlines NVIDIA Grace CPUs which are designed to improve memory bandwidth between CPUs and GPUs for giant AI and HPC models.
Optimize Single Particle Orbital (SPO) Evaluations Based on B-splinesIntel® Software
Orbital representations that are based on B-splines are widely used in quantum Monte Carlo (QMC) simulations of solids, which historically take as much as 50 percent of the total runtime. Random access to a large four-dimensional array make it challenging to efficiently use caches and wide vector units in modern CPUs. So, we present node-level optimizations of B-spline evaluations on multicore and manycore shared memory processors.
To increase single instruction multiple data (SIMD) efficiency and bandwidth utilization, we first apply data layout transformation from an array of structures (AoS) to a structure of arrays (SoA). Then, by blocking SoA objects, we optimize cache reuse and get sustained throughput for a range of problem sizes. We implement efficient nested threading in B-spline orbital evaluation kernels, paving the way towards enabling strong scaling of QMC simulations, resulting with performance enhancements. Finally, we employ roofline performance analysis to model the impacts of our optimizations.
This document discusses new graphics APIs like DX12 and Vulkan that aim to provide lower overhead and more direct hardware access compared to earlier APIs. It covers topics like increased parallelism, explicit memory management using descriptor sets and pipelines, and best practices like batching draw calls and using multiple asynchronous queues. Overall, the new APIs allow more explicit control over GPU hardware for improved performance but require following optimization best practices around areas like parallelism, memory usage, and command batching.
For the full video of this presentation, please visit:
http://www.embedded-vision.com/platinum-members/synopsys/embedded-vision-training/videos/pages/may-2016-embedded-vision-summit-mirchandaney
For more information about embedded vision, please visit:
http://www.embedded-vision.com
Seema Mirchandaney, Engineering Manager for Software Tools at Synopsys, presents the "Using the OpenCL C Kernel Language for Embedded Vision Processors" tutorial at the May 2016 Embedded Vision Summit.
OpenCL C is a programming language that is used to write computation kernels. It is based on C99 and extended to support features such as multiple levels of memory hierarchy, parallelism and synchronization. This talk focuses on the benefits and ease of programming vision-based kernels by using the key features of OpenCL C. In addition, Mirchandaney describes language extensions that allow programmers to take advantage of hardware features typical of embedded vision processors, such as wider vector widths, sophisticated accumulator forms of instructions, and scatter/gather capabilities. This talk also addresses advanced topics, such as whole function vectorization support available in the compiler and the benefits of hardware support for predication in the context of lane-based control flow and OpenCL C.
This document provides an introduction to GPU programming using OpenMP. It discusses what OpenMP is, how the OpenMP programming model works, common OpenMP directives and constructs for parallelization including parallel, simd, work-sharing, tasks, and synchronization. It also covers how to write, compile and run an OpenMP program. Finally, it describes how OpenMP can be used for GPU programming using target directives to offload work to the device and data mapping clauses to manage data transfer between host and device.
Anima Anadkumar, Principal Scientist, Amazon Web Services, Endowed Professor,...MLconf
Large-scale Machine Learning: Deep, Distributed and Multi-Dimensional:
Modern machine learning involves deep neural network architectures which yields state-of-art performance on multiple domains such as computer vision, natural language processing and speech recognition. As the data and models scale, it becomes necessary to have multiple processing units for both training and inference. Apache MXNet is an open-source framework developed for distributed deep learning. I will describe the underlying lightweight hierarchical parameter server architecture that results in high efficiency in distributed settings.
Pushing the current boundaries of deep learning requires using multiple dimensions and modalities. These can be encoded into tensors, which are natural extensions of matrices. We present new deep learning architectures that preserve the multi-dimensional information in data end-to-end. We show that tensor contractions and regression layers are an effective replacement for fully connected layers in deep learning architectures. They result in significant space savings with negligible performance degradation. These functionalities are available in the Tensorly package with MXNet backend interface for large-scale efficient learning.
Bio: Anima Anandkumar is a principal scientist at Amazon Web Services and a Bren professor at Caltech CMS department. Her research interests are in the areas of large-scale machine learning, non-convex optimization and high-dimensional statistics. In particular, she has been spearheading the development and analysis of tensor algorithms. She is the recipient of several awards such as the Alfred. P. Sloan Fellowship, Microsoft Faculty Fellowship, Google research award, ARO and AFOSR Young Investigator Awards, NSF Career Award, Early Career Excellence in Research Award at UCI, Best Thesis Award from the ACM Sigmetrics society, IBM Fran Allen PhD fellowship, and several best paper awards. She has been featured in a number of forums such as the yourstory, Quora ML session, O’Reilly media, and so on. She received her B.Tech in Electrical Engineering from IIT Madras in 2004 and her PhD from Cornell University in 2009. She was a postdoctoral researcher at MIT from 2009 to 2010, an assistant professor at U.C. Irvine between 2010 and 2016, and a visiting researcher at Microsoft Research New England in 2012 and 2014.
improve deep learning training and inference performances.rohit
factors affecting gpu performance for machine learning training and inference.
1. Deep Learning Performance Benchmarks
2. Gpu hardware basics
3. Internal data Transfer
4. Models, Datasets and Parallelism
5. Data training pipeline
6. Performance Tuning
7. Deep Learning Load Distribution Strategies.
8. Misc algorithms like Automatic Differentiation etc.
1) The document discusses implementing and evaluating deep neural networks (DNNs) on mainstream heterogeneous systems like CPUs, GPUs, and APUs.
2) Preliminary results show that an APU achieves the highest performance per watt compared to CPUs and GPUs for DNN models like MLP and autoencoders.
3) Data transfers between the CPU and GPU are identified as a bottleneck, but APUs can help avoid this issue through efficient data sharing and zero-copy techniques between the CPU and GPU.
Exploring Compiler Optimization Opportunities for the OpenMP 4.x Accelerator...Akihiro Hayashi
Third Workshop on Accelerator Programming Using Directives (WACCPD2016, co-located with SC16)
While GPUs are increasingly popular for high-performance
computing, optimizing the performance of GPU programs is a time-consuming and non-trivial process in general. This complexity stems from the low abstraction level of standard
GPU programming models such as CUDA and OpenCL:
programmers are required to orchestrate low-level operations
in order to exploit the full capability of GPUs. In terms of
software productivity and portability, a more attractive approach
would be to facilitate GPU programming by providing high-level
abstractions for expressing parallel algorithms.
OpenMP is a directive-based shared memory parallel programming model and has been widely used for many years.
From OpenMP 4.0 onwards, GPU platforms are supported
by extending OpenMP’s high-level parallel abstractions with
accelerator programming. This extension allows programmers to
write GPU programs in standard C/C++ or Fortran languages,
without exposing too many details of GPU architectures.
However, such high-level parallel programming strategies generally impose additional program optimizations on compilers,
which could result in lower performance than fully hand-tuned
code with low-level programming models.To study potential
performance improvements by compiling and optimizing high-level GPU programs, in this paper, we 1) evaluate a set of
OpenMP 4.x benchmarks on an IBM POWER8 and NVIDIA
Tesla GPU platform and 2) conduct a comparable performance
analysis among hand-written CUDA and automatically-generated
GPU programs by the IBM XL and clang/LLVM compilers.
This document describes designing a real-time heat map service using Apache Storm. It involves collecting check-in data from various locations, geocoding the addresses, building heat maps for time intervals, and persisting the results. The key components are a check-ins spout to generate sample data, geocode lookup bolt to geocode addresses, heat map builder bolt to accumulate locations into intervals and emit maps, and persistor bolt to store results. Stream groupings and parallelism across workers allow the topology to horizontally scale for high throughput processing of location data.
CUDA performance study on Hadoop MapReduce Clusterairbots
This document summarizes a study on using GPUs (CUDA) to accelerate Hadoop MapReduce workloads. It introduces CUDA into Hadoop clusters, evaluates the performance speedup and power efficiency on matrix multiplication and molecular dynamics simulations, and concludes that GPU acceleration provides up to 20x speedup and reduces power consumption by up to 19/20, making it a cost-effective approach compared to CPU-only upgrades. Future work is outlined to port more applications and support heterogeneous GPU/CPU clusters.
FPGAs can compete with GPUs for some applications but with some key differences:
1) FPGAs are configured to create custom hardware for an algorithm rather than using predefined hardware like GPUs. This allows high efficiency but is more difficult to program.
2) While OpenCL provides a common language, FPGAs and GPUs have very different architectures and optimizing algorithms requires different approaches for each.
3) For applications with high bandwidth I/O or flexibility requirements, FPGAs may have advantages over GPUs, but GPUs typically have higher performance for compute-heavy applications and better energy efficiency. Overall, FPGAs have become more accessible but still require more programming effort than GPUs.
MapReduce: A useful parallel tool that still has room for improvementKyong-Ha Lee
The document discusses MapReduce, a framework for processing large datasets in parallel. It provides an overview of MapReduce's basic principles, surveys research to improve the conventional MapReduce framework, and describes research projects ongoing at KAIST. The key points are that MapReduce provides automatic parallelization, fault tolerance, and distributed processing of large datasets across commodity computer clusters. It also introduces the map and reduce functions that define MapReduce jobs.
Utilizing AMD GPUs: Tuning, programming models, and roadmapGeorge Markomanolis
A presentation at FOSDEM 2022 about AMD GPUs, tuning, programming models and software roadmap. This is continuation from the previous talk (FOSDEM 2021)
CC-4005, Performance analysis of 3D Finite Difference computational stencils ...AMD Developer Central
The document discusses performance analysis of 3D finite difference computational stencils on Seamicro fabric compute systems. It provides an overview of the hardware including chassis, compute cards, storage cards, and 3D torus fabric topology. It then describes the software stack and various microbenchmarks performed, including CPU, memory, network and storage benchmarks. It also describes modeling of 3D Laplace's equation using an 8th order finite difference scheme and its discretization over a 25 point stencil for computation on the system.
Designing High Performance Computing Architectures for Reliable Space Applica...Fisnik Kraja
This document summarizes Fisnik Kraja's PhD defense on designing high performance computing architectures for reliable space applications. Kraja proposed an architecture using parallel processing nodes connected via a radiation-hardened management unit. Benchmarking of the 2DSSAR image reconstruction application showed optimizing for shared memory, distributed memory, and heterogeneous CPU/GPU systems. The best performance was achieved using a heterogeneous node with a multi-core CPU and dual GPUs, providing a 34.46x speedup. Kraja's conclusions recommended a design using powerful shared memory parallel processing nodes each with CPUs, GPUs, and distributed memory only if multiple nodes are needed.
Direct3D 12 aims to reduce CPU overhead and increase scalability across CPU cores by allowing developers greater control over the graphics pipeline. It optimizes pipeline state handling through pipeline state objects and reduces redundant resource binding by introducing descriptor heaps and tables. Command lists and bundles further improve performance by enabling parallel command list generation and reuse of draw commands.
The document compares on-heap and off-heap caching options. It discusses heap memory usage in the JVM and alternatives like off-heap memory using memory mapped files, ByteBuffers, and Unsafe. Popular off-heap caches like Chronicle, Hazelcast, and Redis are presented along with comparisons of their features, performance, and garbage collection impact. The document aims to help developers choose the most suitable cache for their application needs.
For the full video of this presentation, please visit:
http://www.embedded-vision.com/platinum-members/arm/embedded-vision-training/videos/pages/may-2016-embedded-vision-summit-iodice
For more information about embedded vision, please visit:
http://www.embedded-vision.com
Gian Marco Iodice, Software Engineer at ARM, presents the "Using SGEMM and FFTs to Accelerate Deep Learning" tutorial at the May 2016 Embedded Vision Summit.
Matrix Multiplication and the Fast Fourier Transform are numerical foundation stones for a wide range of scientific algorithms. With the emergence of deep learning, they are becoming even more important, particularly as use cases extend into mobile and embedded devices. In this presentation, lodice discusses and analyzes how these two key, computationally-intensive algorithms can be used to gain significant performance improvements for convolutional neural network (CNN) implementations.
After a brief introduction to the nature of CNN computations, Iodice explores the use of GEMM (General Matrix Multiplication) and mixed-radix FFTs to accelerate 3D convolution. He shows examples of OpenCL implementations of these functions and highlights their advantages, limitations and trade-offs. Central to the techniques explored is an emphasis on cache-efficient memory accesses and the crucial role of reduced-precision data types.
The document discusses NVIDIA data center GPUs such as the A100, A30, A40, and A10 and their performance capabilities. It provides examples of GPU accelerated application performance showing simulations in Simulia CST Studio, Altair CFD, and Rocky DEM achieving excellent speedups on GPUs. It also discusses Paraview visualization being accelerated with NVIDIA OptiX ray tracing, further sped up using RT cores. Looking ahead, the document outlines NVIDIA Grace CPUs which are designed to improve memory bandwidth between CPUs and GPUs for giant AI and HPC models.
Optimize Single Particle Orbital (SPO) Evaluations Based on B-splinesIntel® Software
Orbital representations that are based on B-splines are widely used in quantum Monte Carlo (QMC) simulations of solids, which historically take as much as 50 percent of the total runtime. Random access to a large four-dimensional array make it challenging to efficiently use caches and wide vector units in modern CPUs. So, we present node-level optimizations of B-spline evaluations on multicore and manycore shared memory processors.
To increase single instruction multiple data (SIMD) efficiency and bandwidth utilization, we first apply data layout transformation from an array of structures (AoS) to a structure of arrays (SoA). Then, by blocking SoA objects, we optimize cache reuse and get sustained throughput for a range of problem sizes. We implement efficient nested threading in B-spline orbital evaluation kernels, paving the way towards enabling strong scaling of QMC simulations, resulting with performance enhancements. Finally, we employ roofline performance analysis to model the impacts of our optimizations.
This document discusses new graphics APIs like DX12 and Vulkan that aim to provide lower overhead and more direct hardware access compared to earlier APIs. It covers topics like increased parallelism, explicit memory management using descriptor sets and pipelines, and best practices like batching draw calls and using multiple asynchronous queues. Overall, the new APIs allow more explicit control over GPU hardware for improved performance but require following optimization best practices around areas like parallelism, memory usage, and command batching.
For the full video of this presentation, please visit:
http://www.embedded-vision.com/platinum-members/synopsys/embedded-vision-training/videos/pages/may-2016-embedded-vision-summit-mirchandaney
For more information about embedded vision, please visit:
http://www.embedded-vision.com
Seema Mirchandaney, Engineering Manager for Software Tools at Synopsys, presents the "Using the OpenCL C Kernel Language for Embedded Vision Processors" tutorial at the May 2016 Embedded Vision Summit.
OpenCL C is a programming language that is used to write computation kernels. It is based on C99 and extended to support features such as multiple levels of memory hierarchy, parallelism and synchronization. This talk focuses on the benefits and ease of programming vision-based kernels by using the key features of OpenCL C. In addition, Mirchandaney describes language extensions that allow programmers to take advantage of hardware features typical of embedded vision processors, such as wider vector widths, sophisticated accumulator forms of instructions, and scatter/gather capabilities. This talk also addresses advanced topics, such as whole function vectorization support available in the compiler and the benefits of hardware support for predication in the context of lane-based control flow and OpenCL C.
This document provides an introduction to GPU programming using OpenMP. It discusses what OpenMP is, how the OpenMP programming model works, common OpenMP directives and constructs for parallelization including parallel, simd, work-sharing, tasks, and synchronization. It also covers how to write, compile and run an OpenMP program. Finally, it describes how OpenMP can be used for GPU programming using target directives to offload work to the device and data mapping clauses to manage data transfer between host and device.
Anima Anadkumar, Principal Scientist, Amazon Web Services, Endowed Professor,...MLconf
Large-scale Machine Learning: Deep, Distributed and Multi-Dimensional:
Modern machine learning involves deep neural network architectures which yields state-of-art performance on multiple domains such as computer vision, natural language processing and speech recognition. As the data and models scale, it becomes necessary to have multiple processing units for both training and inference. Apache MXNet is an open-source framework developed for distributed deep learning. I will describe the underlying lightweight hierarchical parameter server architecture that results in high efficiency in distributed settings.
Pushing the current boundaries of deep learning requires using multiple dimensions and modalities. These can be encoded into tensors, which are natural extensions of matrices. We present new deep learning architectures that preserve the multi-dimensional information in data end-to-end. We show that tensor contractions and regression layers are an effective replacement for fully connected layers in deep learning architectures. They result in significant space savings with negligible performance degradation. These functionalities are available in the Tensorly package with MXNet backend interface for large-scale efficient learning.
Bio: Anima Anandkumar is a principal scientist at Amazon Web Services and a Bren professor at Caltech CMS department. Her research interests are in the areas of large-scale machine learning, non-convex optimization and high-dimensional statistics. In particular, she has been spearheading the development and analysis of tensor algorithms. She is the recipient of several awards such as the Alfred. P. Sloan Fellowship, Microsoft Faculty Fellowship, Google research award, ARO and AFOSR Young Investigator Awards, NSF Career Award, Early Career Excellence in Research Award at UCI, Best Thesis Award from the ACM Sigmetrics society, IBM Fran Allen PhD fellowship, and several best paper awards. She has been featured in a number of forums such as the yourstory, Quora ML session, O’Reilly media, and so on. She received her B.Tech in Electrical Engineering from IIT Madras in 2004 and her PhD from Cornell University in 2009. She was a postdoctoral researcher at MIT from 2009 to 2010, an assistant professor at U.C. Irvine between 2010 and 2016, and a visiting researcher at Microsoft Research New England in 2012 and 2014.
improve deep learning training and inference performances.rohit
factors affecting gpu performance for machine learning training and inference.
1. Deep Learning Performance Benchmarks
2. Gpu hardware basics
3. Internal data Transfer
4. Models, Datasets and Parallelism
5. Data training pipeline
6. Performance Tuning
7. Deep Learning Load Distribution Strategies.
8. Misc algorithms like Automatic Differentiation etc.
1) The document discusses implementing and evaluating deep neural networks (DNNs) on mainstream heterogeneous systems like CPUs, GPUs, and APUs.
2) Preliminary results show that an APU achieves the highest performance per watt compared to CPUs and GPUs for DNN models like MLP and autoencoders.
3) Data transfers between the CPU and GPU are identified as a bottleneck, but APUs can help avoid this issue through efficient data sharing and zero-copy techniques between the CPU and GPU.
This document discusses QGATE, a quantum circuit simulator that can accelerate simulations using GPUs. QGATE uses several techniques to optimize simulations, including gate cancellation, dynamic qubit grouping, and operator reordering. Gate cancellation removes redundant gates, dynamic qubit grouping reduces the number of variables needed for state vectors when qubits are not entangled, and operator reordering maximizes the effects of dynamic qubit grouping by rearranging gates and measurements. These optimizations aim to improve simulation performance by reducing calculation amounts. Benchmark results show QGATE achieves up to a 220x speedup over CPU simulations for a circuit with 30 qubits and 10 Hadamard gates on each qubit.
This document discusses GPU computing and CUDA programming. It begins with an introduction to GPU computing and CUDA. CUDA (Compute Unified Device Architecture) allows programming of Nvidia GPUs for parallel computing. The document then provides examples of optimizing matrix multiplication and closest pair problems using CUDA. It also discusses implementing and optimizing convolutional neural networks (CNNs) and autoencoders for GPUs using CUDA. Performance results show speedups for these deep learning algorithms when using GPUs versus CPU-only implementations.
byteLAKE's expertise across NVIDIA architectures and configurationsbyteLAKE
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1. OpenCL caffe aims to enable cross-platform machine learning by porting the popular Caffe framework to use OpenCL instead of CUDA. This allows deployment of deep learning models on a variety of devices.
2. Performance optimizations included batching data to improve parallelism, and using multiple command queues to increase concurrent tasks. These provided up to 4.5x speedup over the baseline clBLAS library.
3. While OpenCL caffe performance matched CUDA caffe, a 2x gap remained versus proprietary cuDNN library, indicating potential for further hardware-specific optimizations to close this gap. The work helps address challenges of cross-platform deep learning.
Exploring the Performance Impact of Virtualization on an HPC CloudRyousei Takano
The document evaluates the performance impact of virtualization on high-performance computing (HPC) clouds. Experiments were conducted on the AIST Super Green Cloud, a 155-node HPC cluster. Benchmark results show that while PCI passthrough mitigates I/O overhead, virtualization still incurs performance penalties for MPI collectives as node counts increase. Application benchmarks demonstrate overhead is limited to around 5%. The study concludes HPC clouds are promising due to utilization improvements from virtualization, but further optimization of virtual machine placement and pass-through technologies could help reduce overhead.
Monte Carlo simulation is one of the most important numerical methods in financial derivative pricing and risk management. Due to the increasing sophistication of exotic derivative models, Monte Carlo becomes the method of choice for numerical implementations because of its flexibility in high-dimensional problems. However, the method of discretization of the underlying stochastic differential equation (SDE) has a significant effect on convergence. In addition the choice of computing platform and the exploitation of parallelism offers further efficiency gains. We consider here the effect of higher order discretization methods together with the possibilities opened up by the advent of programmable graphics processing units (GPUs) on the overall performance of Monte Carlo and quasi-Monte Carlo methods.
SOM (Self-Organizing Map) is one of the most popular artificial neural network algorithms in the unsupervised learning category. For efficient construction of large maps searching the best-matching unit is usually the computationally heaviest operation in the SOM. The parallel nature of the algorithm and the huge computations involved makes it a good target for GPU based parallel implementation. This paper presents an overall idea of the optimization strategies used for the parallel implementation of Basic-SOM on GPU using CUDA programming paradigm.
Presentació a càrrec d'Adrián Macía, cap de Càlcul Científic del CSUC, duta a terme a la "3a Jornada de formació sobre l'ús del servei de càlcul" celebrada el 29 d'octubre de 2020 en format virtual.
This document provides an outline of manycore GPU architectures and programming. It introduces GPU architectures, the GPGPU concept, and CUDA programming. It discusses the GPU execution model, CUDA programming model, and how to work with different memory types in CUDA like global, shared and constant memory. It also covers streams and concurrency, CUDA intrinsics and libraries, performance profiling and debugging. Finally, it mentions directive-based programming models like OpenACC and OpenMP.
The document summarizes the available high performance computing (HPC) resources at CSUC. It describes the hardware facilities including the Canigó and Pirineus II clusters, which provide a total of 3,072 cores and 317 TFlop/s of computing power. The working environment is a shared Linux system managed by Slurm. Users can access compilers, libraries and development tools. Support is provided through documentation and a service desk.
The document summarizes several AI accelerators for cloud datacenters including Google TPU, HabanaLabs Gaudi, Graphcore IPU, and Baidu Kunlun. It discusses their architectures, performance, and how they address challenges in datacenters like workload diversity and energy efficiency. The accelerators use specialized hardware like systolic arrays and FPGA/ASIC designs to achieve much higher performance and efficiency than CPUs and GPUs for AI tasks like training deep learning models.
Large-Scale Training with GPUs at FacebookFaisal Siddiqi
This document discusses large-scale distributed training with GPUs at Facebook using their Caffe2 framework. It describes how Facebook was able to train the ResNet-50 model on the ImageNet dataset in just 1 hour using 32 GPUs with 8 GPUs each. It explains how synchronous SGD was implemented in Caffe2 using Gloo for efficient all-reduce operations. Linear scaling of the learning rate with increased batch size was found to work best when gradually warming up the learning rate over the first few epochs. Nearly linear speedup was achieved using this approach on commodity hardware.
A Dataflow Processing Chip for Training Deep Neural Networksinside-BigData.com
In this deck from the Hot Chips conference, Chris Nicol from Wave Computing presents: A Dataflow Processing Chip for Training Deep Neural Networks.
Watch the video: https://wp.me/p3RLHQ-k6W
Learn more: https://wavecomp.ai/
and
http://www.hotchips.org/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
CUDA is a parallel computing platform that allows developers to use GPUs for general purpose processing. It provides a programming model for writing C/C++ applications that leverage the parallel compute engines on Nvidia GPUs. CUDA applications use a data-parallel programming model where the GPU runs many lightweight threads concurrently. The CUDA programming model exposes a hierarchical memory structure including registers, shared memory, and global memory. Developers can write CUDA programs that transfer data from CPU to GPU memory, launch kernels on the GPU, and copy results back to the CPU.
DPDK is a set of drivers and libraries that allow applications to bypass the Linux kernel and access network interface cards directly for very high performance packet processing. It is commonly used for software routers, switches, and other network applications. DPDK can achieve over 11 times higher packet forwarding rates than applications using the Linux kernel network stack alone. While it provides best-in-class performance, DPDK also has disadvantages like reduced security and isolation from standard Linux services.
In this deck from the UK HPC Conference, Gunter Roeth from NVIDIA presents: Hardware & Software Platforms for HPC, AI and ML.
"Data is driving the transformation of industries around the world and a new generation of AI applications are effectively becoming programs that write software, powered by data, vs by computer programmers. Today, NVIDIA’s tensor core GPU sits at the core of most AI, ML and HPC applications, and NVIDIA software surrounds every level of such a modern application, from CUDA and libraries like cuDNN and NCCL embedded in every deep learning framework and optimized and delivered via the NVIDIA GPU Cloud to reference architectures designed to streamline the deployment of large scale infrastructures."
Watch the video: https://wp.me/p3RLHQ-l2Y
Learn more: http://nvidia.com
and
http://hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Similar to Performance Analysis of Lattice QCD on GPUs in APGAS Programming Model (20)
Hybrid Map Task Scheduling for GPU-based Heterogeneous ClustersKoichi Shirahata
This document proposes a hybrid scheduling technique for MapReduce jobs on GPU-based heterogeneous clusters. It aims to accelerate MapReduce by efficiently scheduling Map tasks to both CPUs and GPUs to minimize total job execution time. The technique was implemented in Hadoop using its Pipes feature to invoke CUDA programs from Java. Evaluation on a K-means application showed the hybrid scheduling approach was 1.93 times faster than CPU-only execution at 64 nodes by better utilizing multiple GPUs.
A GPU Implementation of Generalized Graph Processing Algorithm GIM-VKoichi Shirahata
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This document summarizes an approach for out-of-core GPU memory management for large-scale graph processing on heterogeneous supercomputers. The approach introduces techniques for out-of-core GPU data management in a GPU-MapReduce framework. It implements out-of-core GPU sorting and investigates balancing scale-up and scale-out approaches. Performance tests on two supercomputers show up to 2.1x speedup over CPUs and 1.71x power efficiency from scaling up GPU usage.
A Scalable Implementation of a MapReduce-based Graph Processing Algorithm for...Koichi Shirahata
The document proposes implementing a scalable multi-GPU version of the graph processing algorithm GIM-V using MapReduce on large-scale heterogeneous supercomputers. It aims to optimize load balancing between GPU devices for large graph processing. The key contributions are: 1) Implementing GIM-V on a multi-GPU MapReduce framework called Mars by extending it with MPI for inter-GPU communication; 2) Optimizing GIM-V and load balancing for graph partitioning across GPUs. Evaluation on a 768-GPU supercomputer showed up to 1.52x speedup over CPU-based processing.
Performance Analysis of MapReduce Implementations on High Performance Homolog...Koichi Shirahata
This document describes performance analyses of MapReduce implementations for large-scale homology searches. It introduces homology searches and their use in metagenome analysis using sequence databases that are growing enormously in size. Two MapReduce designs for homology searches are proposed: one replicates the database on all nodes, while the other distributes the database. Preliminary experiments show MapReduce exhibits good scaling and comparable performance to MPI implementations. The goal is high-performance MapReduce homology searches for extremely large databases.
Removing Uninteresting Bytes in Software FuzzingAftab Hussain
Imagine a world where software fuzzing, the process of mutating bytes in test seeds to uncover hidden and erroneous program behaviors, becomes faster and more effective. A lot depends on the initial seeds, which can significantly dictate the trajectory of a fuzzing campaign, particularly in terms of how long it takes to uncover interesting behaviour in your code. We introduce DIAR, a technique designed to speedup fuzzing campaigns by pinpointing and eliminating those uninteresting bytes in the seeds. Picture this: instead of wasting valuable resources on meaningless mutations in large, bloated seeds, DIAR removes the unnecessary bytes, streamlining the entire process.
In this work, we equipped AFL, a popular fuzzer, with DIAR and examined two critical Linux libraries -- Libxml's xmllint, a tool for parsing xml documents, and Binutil's readelf, an essential debugging and security analysis command-line tool used to display detailed information about ELF (Executable and Linkable Format). Our preliminary results show that AFL+DIAR does not only discover new paths more quickly but also achieves higher coverage overall. This work thus showcases how starting with lean and optimized seeds can lead to faster, more comprehensive fuzzing campaigns -- and DIAR helps you find such seeds.
- These are slides of the talk given at IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW 2022.
Infrastructure Challenges in Scaling RAG with Custom AI modelsZilliz
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In the rapidly evolving landscape of technologies, XML continues to play a vital role in structuring, storing, and transporting data across diverse systems. The recent advancements in artificial intelligence (AI) present new methodologies for enhancing XML development workflows, introducing efficiency, automation, and intelligent capabilities. This presentation will outline the scope and perspective of utilizing AI in XML development. The potential benefits and the possible pitfalls will be highlighted, providing a balanced view of the subject.
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Further emphasis will be placed on the role of AI in developing XSLT, or schemas such as XSD and Schematron. We will address the techniques and strategies adopted to create prompts for generating code, explaining code, or refactoring the code, and the results achieved.
The discussion will extend to how AI can be used to transform XML content. In particular, the focus will be on the use of AI XPath extension functions in XSLT, Schematron, Schematron Quick Fixes, or for XML content refactoring.
The presentation aims to deliver a comprehensive overview of AI usage in XML development, providing attendees with the necessary knowledge to make informed decisions. Whether you’re at the early stages of adopting AI or considering integrating it in advanced XML development, this presentation will cover all levels of expertise.
By highlighting the potential advantages and challenges of integrating AI with XML development tools and languages, the presentation seeks to inspire thoughtful conversation around the future of XML development. We’ll not only delve into the technical aspects of AI-powered XML development but also discuss practical implications and possible future directions.
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Pushing the limits of ePRTC: 100ns holdover for 100 daysAdtran
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What will you get from this session?
1. Insights into integrating generative AI.
2. Understanding how this integration enhances test automation within the UiPath platform
3. Practical demonstrations
4. Exploration of real-world use cases illustrating the benefits of AI-driven test automation for UiPath
Topics covered:
What is generative AI
Test Automation with generative AI and Open AI.
UiPath integration with generative AI
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
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Webinar Recording: https://www.panagenda.com/webinars/hcl-notes-and-domino-license-cost-reduction-in-the-world-of-dlau/
The introduction of DLAU and the CCB & CCX licensing model caused quite a stir in the HCL community. As a Notes and Domino customer, you may have faced challenges with unexpected user counts and license costs. You probably have questions on how this new licensing approach works and how to benefit from it. Most importantly, you likely have budget constraints and want to save money where possible. Don’t worry, we can help with all of this!
We’ll show you how to fix common misconfigurations that cause higher-than-expected user counts, and how to identify accounts which you can deactivate to save money. There are also frequent patterns that can cause unnecessary cost, like using a person document instead of a mail-in for shared mailboxes. We’ll provide examples and solutions for those as well. And naturally we’ll explain the new licensing model.
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These topics will be covered
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HCL Notes and Domino License Cost Reduction in the World of DLAU
Performance Analysis of Lattice QCD on GPUs in APGAS Programming Model
1. Performance
Analysis
of
La1ce
QCD
on
GPUs
in
APGAS
Programming
Model
Koichi
Shirahata1,
Jun
Doi2,
Mikio
Takeuchi2
1:
Tokyo
InsGtute
of
Technology
2:
IBM
Research
-‐
Tokyo
2. Programming
Models
for
Exascale
CompuGng
• GPU-‐based
heterogeneous
clusters
– e.g.)
TSUBAME
2.5
(3
GPUs
x
1408
nodes)
– AcceleraGon
using
GPUs
• High
peak
performance/memory
bandwidth
• Programming
models
for
GPU-‐based
clusters
– Massage
passing
(e.g.
MPI)
• High
tuning
efficiency
• High
programming
cost
– APGAS
(Asynchronous
ParGGoned
Global
Address
Space)
• Abstract
distributed
memory
and
deep
memory
hierarchy
• X10:
an
instance
of
APGAS
programming
languages
→
Highly
scalable
and
producGve
compuGng
on
GPUs
using
APGAS
3. Problem
Statement
• How
much
do
GPUs
accelerate
applicaGons
using
APGAS?
– Tradeoff
between
performance
and
producGvity
• Performance
– The
abstracGon
of
memory
hierarchy
may
limit
performance
– Scalability
on
mulG-‐GPU
• ProducGvity
– Can
we
use
GPUs
with
li`le
programming
cost?
4. Goal
and
ContribuGons
• Goal
– Scalable
and
producGve
compuGng
on
GPUs
• Approach
– Performance
analysis
of
la1ce
QCD
in
X10
CUDA
• Implement
la1ce
QCD
in
X10
CUDA
• ComparaGve
performance
analysis
of
X10
on
GPUs
• Confirm
acceleraGon
using
GPUs
in
X10
– 19.4x
speedup
from
X10
by
using
X10
CUDA
on
32
nodes
of
TSUBAME
2.5
5. The
APGAS
Model
using
GPUs
Child
Place
0
Child
Place
M-‐1
...
...
...
...
...
...
GPU
Place
...
Place
0
Place
1
Place
N-‐1
AcGvity
at
async
at
asyncCopy
asyncCopy
asyncCopy
at
at
asyncCopy
Object
CPU
Place
X10
provides
CUDA
support
for
GPUs
[1]
[1]
Cunningham,
D.
et
al.
"GPU
programming
in
a
high
level
language:
compiling
X10
to
CUDA."
Proceedings
of
the
2011
ACM
SIGPLAN
X10
Workshop.
ACM,
2011.
6. La1ce
QCD
• La1ce
QCD
– SimulaGon
of
Quantum
ChromoDynamics
(QCD)
of
quarks
and
gluons
on
4D
grid
of
points
in
space
and
Gme
– A
grand
challenge
in
high-‐performance
compuGng
• Requires
high
memory/network
bandwidth
and
computaGonal
power
• CompuGng
la1ce
QCD
– Monte-‐Carlo
simulaGons
on
4D
grid
– Dominated
solving
linear
equaGons
of
matrix-‐vector
mulGplicaGon
using
iteraGve
methods
(etc.
CG
method)
– Parallelizable
by
dividing
4D
grid
into
parGal
grids
for
each
place
• Boundary
exchanges
are
required
between
places
in
each
direcGon
7. ImplementaGon
of
La1ce
QCD
in
X10
CUDA
• We
extend
our
la1ce
QCD
in
X10
into
X10
CUDA
– PorGng
whole
solvers
into
CUDA
kernels
• Wilson-‐Dirac
operator,
BLAS
level
1
operaGons
• Avoid
waste
memory
copy
overheads
between
CPU
and
GPU,
except
boundary
data
transfers
– Implement
boundary
data
transfer
among
GPUs
• Add
memory
copy
operaGons
– (1)
GPU
à
CPU,
(2)
CPU
à
CPU,
(3)
CPU
à
GPU
– OpGmizaGons
• Data
layout
transformaGon
• CommunicaGon
overlapping
8. Data
Layout
TransformaGon
• Two
types
of
data
layouts
for
quarks
and
gluons
– AoS
(Array
of
Structure)
• Non-‐conGguous
data
• Used
in
our
original
CPU
implementaGons
– SoA
(Structure
of
Array)
• ConGguous
data
• Suitable
for
vectorizaGon
• We
translate
from
AoS
to
SoA
– GPU
is
suitable
for
coalesced
memory
access
(0,
0,
0,
0)
(1,
0,
0,
0)
(x,
y,
z,
t):
…
Spin
1
Spin
2
…
Spin:
…
…
AoS
…
…
SoA
(n-‐1,
n-‐1,
n-‐1,
n-‐1)
Spin
m
…
…
9. CommunicaGon
OpGmizaGons
in
X10
CUDA
• Two
communicaGon
opGmizaGons
– mulG-‐dimensional
parGGoning
– CommunicaGon
overlapping
• Overlap
memory
copy
between
GPU
and
CPU
in
addiGon
to
between
CPU
and
CPU
• Overlapping
domain
is
limited
by
finish-‐based
synchronizaGon
Comp.
Comm.
GPU Kernel
Transfer btw. CPU and GPU
Exchange btw. CPU and CPU
Time
Synchronization (using finish)
T:
X:
Y:
Z:
Inner:
10. Experimental
Setup
• Performance
comparison
with
other
implementaGons
– X10
C++,
MPI
C,
MPI
CUDA
– Use
one
GPU
per
node
• Measurements
– Weak
scaling
– Strong
scaling
• ConfiguraGon
– Measure
average
iteraGon
Gme
of
one
convergence
of
CG
method
• Typically
300
–
500
iteraGons
– Problem
size
• (x,
y,
z,
t)
=
(24,
24,
24,
96)
(unless
specified)
• Fit
on
one
Tesla
K20X
GPU
11. Experimental
environments
• TSUBAME2.5
supercomputer
(unless
specified)
– Use
up
to
32
nodes
(32
GPUs)
– CPU-‐GPU:
PCI-‐E
2.0
x16
(8
GB/sec)
– Internode:
QDR
IB
dual
rail
(10
GB/sec)
• Setup
– 1
place
per
node
– 1
GPU
per
place
(X10
CUDA)
– 12
threads
per
place
(X10
C++,
MPI
C)
• Sotware
– X10
version
2.4.3.2
– CUDA
version
6.0
– OpenMPI
1.6.5
2
CPUs
/
node
3
GPUs
/
node
Model
Intel®
Xeon®
X5670
Tesla
K20X
#
Cores
6
2688
Frequency
2.93
GHz
0.732
GHz
Memory
54
GB
6
GB
Memory
BW
32
GB/sec
250
GB/sec
Compiler
gcc
4.3.4
Nvcc
6.0
11
12. Comparison
of
Weak
Scaling
with
CPU-‐based
ImplementaGons
1
10
100
1000
1
2
4
8
16
32
Performance
[Gflops]
Number
of
Nodes
MPI
C
X10
C++
X10
CUDA
DP
X10
CUDA
SP
• X10
CUDA
exhibits
good
weak
scaling
– 19.4x
and
11.0x
faster
than
X10
C++
and
MPI
C
each
on
32
nodes
– X10
CUDA
does
not
incur
communicaGonal
penalty
with
large
amount
of
data
on
GPUs
0
500
1000
1500
2000
2500
3000
1
2
4
8
16
32
Elapsed
Time
per
Itera@on
[ms]
Number
of
Nodes
MPI
C
X10
C++
X10
CUDA
DP
X10
CUDA
SP
13. Comparison
of
Weak
Scaling
with
MPI
CUDA
• Comparison
on
TSUBAME-‐KFC
– X10
2.5.1,
CUDA
5.5,
OpenMPI
1.7.2
– Problem
Size:
24
x
24
x
24
x
24
per
node
• X10
CUDA
performs
similar
scalability
with
MPI
CUDA
• Increase
performance
gap
as
using
larger
number
of
nodes
1
10
100
1000
1
2
4
8
16
32
Performance
[Gflops]
Number
of
Nodes
MPI
CUDA
DP
X10
CUDA
DP
0
10
20
30
40
50
60
70
80
1
2
4
8
16
32
Elapsed
Time
per
Itera@on
[msec]
Number
of
Nodes
MPI
CUDA
DP
X10
CUDA
DP
14. Strong
Scaling
Comparing
with
CPU-‐
based
ImplementaGons
• X10
CUDA
outperforms
both
X10
C++
and
MPI
C
– 8.27x
and
4.57x
faster
each
on
16
Places
– Scalability
of
X10
CUDA
gets
poorer
as
the
number
of
nodes
increases
1
10
100
1000
1
2
4
8
16
32
Performance
[Gflops]
Number
of
Nodes
MPI
C
X10
C++
X10
CUDA
DP
X10
CUDA
SP
15. Comparison
of
Strong
Scaling
with
MPI
CUDA
• Comparison
on
TSUBAME-‐KFC
– X10
2.5.1,
CUDA
5.5,
OpenMPI
1.7.2
• X10
CUDA
exhibits
comparaGve
performance
up
to
4
nodes
• X10
CUDA
suffers
heavy
overheads
on
over
8
nodes
1
10
100
1000
1
2
4
8
16
32
Preformance
[Gflops]
Number
of
Nodes
MPI
CUDA
DP
X10
CUDA
DP
0
20
40
60
80
100
120
140
160
180
200
0
10
20
30
40
Elapsed
Time
per
Itera@on
[msec]
Number
of
Nodes
MPI
CUDA
DP
X10
CUDA
DP
16. Performance
Breakdown
of
La1ce
QCD
in
X10
CUDA
• CommunicaGon
overhead
increases
– Both
boundary
communicaGon
and
MPI
Allreduce
• ComputaGon
parts
also
do
not
scale
linearly
0
10
20
30
40
50
60
70
80
90
100
0
20
40
60
80
100
120
1
2
4
8
16
32
Comm.
Overhead
[%]
Elapsed
Time
per
Iteratoin
[ms]
Number
of
Nodes
Bnd
Comm.
Allreduce
BLAS
Wilson-‐Dirac
Comm.
RaGo
17. Comparison
with
MPI
CUDA
using
Different
Problem
Sizes
• Comparison
on
TSUBAME-‐KFC
– X10
2.5.1,
CUDA
5.5
• X10
CUDA
suffers
heavy
overhead
on
small
problem
sizes
– 6.02x
slower
on
4
x
4
x
4
x
8
– We
consider
X10
CUDA
suffers
constant
overhead
1
10
100
1000
10000
4x4x4x8
8x8x8x16
12x12x12x48
24x24x24x96
Performance
[Gflops]
Problem
Size
(X
x
Y
x
Z
x
T)
MPI
CUDA
DP
X10
CUDA
DP
18. Comparison
of
ProducGvity
with
MPI
CUDA
• Lines
of
code
– X10
CUDA
version
contains
1.92x
larger
lines
of
code
compared
with
MPI
CUDA
in
total
• Since
currently
X10
CUDA
cannot
call
device
funcGons
inside
CUDA
kernels
• Compiling
Gme
– X10
CUDA
takes
11.3x
longer
Gme
to
compile
MPI
CUDA
X10
CUDA
Total
4667
8942
Wilson
Dirac
1590
6512
MPI
CUDA
X10
CUDA
Compiling
Time
[sec]
15.19
171.50
19. Pros/Cons
of
X10
CUDA
from
Our
Study
• Advantages
of
X10
CUDA
– Straighxorward
porGng
from
X10
to
X10
CUDA
• Simply
porGng
computaGon
kernels
into
CUDA
• inserGng
memory
copy
operaGons
between
CPU
and
GPU
– X10
CUDA
exhibits
good
weak
scaling
• Drawbacks
of
current
version
of
X10
CUDA
– LimitaGons
of
programmability
• X10
CUDA
cannot
call
a
funcGon
inside
a
kernel
– LimitaGons
of
performance
• finish-‐based
synchronizaGon
incurs
overhead
• X10
CUDA
does
not
support
creaGng
CUDA
streams
20. Related
Work
• High
performance
large-‐scale
la1ce
QCD
computaGon
– Peta-‐scale
la1ce
QCD
on
a
Blue
Gene/Q
supercomputer
[Doi
et
al.
2012]
• Fully
overlapping
communicaGon
and
applying
node-‐mapping
opGmizaGon
for
BG/Q
• La1ce
QCD
using
many-‐core
accelerators
– QUDA:
A
QCD
library
on
GPUs
[Clark
et
al.
2010]
• Invokes
mulGple
CUDA
streams
for
overlapping
– La1ce
QCD
on
Intel
Xeon
Phi
[Joo
et
al.
2013]
• PGAS
language
extension
for
mulG-‐node
GPU
clusters
– XcalableMP
extension
for
GPU
[Lee
et
al.
2012]
• Demonstrated
their
N-‐body
implementaGon
scales
well
21. Conclusion
• Conclusion
– GPUs
accelerate
la1ce
QCD
significantly
in
APGAS
programming
model
• X10
CUDA
exhibits
good
scalability
in
weak
scaling
• 19.4x
speedup
from
X10
by
using
X10
CUDA
on
32
nodes
of
TSUBAME
2.5
– We
reveal
limitaGons
in
current
X10
CUDA
• Performance
overheads
in
strong
scalability
• Increase
of
lines
of
code
• Future
work
– Performance
improvement
in
strong
scaling
• More
detailed
analysis
of
overheads
in
X10
CUDA
23. Breakdown
of
Wilson-‐Dirac
ComputaGon
in
X10
CUDA
• CommunicaGon
becomes
dominant
when
using
more
than
16
places
– A
cause
of
the
limit
of
strong
scaling
• Possible
ways
to
improve
the
scalability
– Applying
one-‐to-‐one
synchronizaGon
– Improving
communicaGon
and
synchronizaGon
operaGons
themselves
in
X10
0
10
20
30
40
50
60
70
1
2
4
8
16
32
Elapsed
Time
[ms]
Number
of
Places
Gamma5
Bnd
Set
Copy
CPU
to
GPU
max(Bulk,
Bnd)
Bulk
Bnd
(Make
+
Comm.)
24. Comparison
with
Different
Dimensions
of
La1ce
ParGGoning
• Comparison
between
4D
and
1D
parGGoning
– 1D
parGGoning
exhibits
be`er
strong
scalability
– 1.35x
be`er
on
32
GPUs
– SGll
saturate
using
over
16
GPUs
0
50
100
150
200
250
0
5
10
15
20
25
30
35
Gflops
Number
of
Nodes
(=
Number
of
GPUs)
Strong
Scaling
(24x24x24x96)
X10
CUDA
SP
X10
CUDA
SP
(div
t)
25. Comparison
with
QUDA
• QUDA
[1]:
A
QCD
library
on
GPUs
– Highly
opGmized
for
GPUs
• QUDA
exhibits
be`er
strong
scalability
– Currently
30.4x
slower
in
X10
CUDA
1
10
100
1000
10000
1
2
4
8
16
32
Gflops
Number
of
Places
(number
of
GPUs)
X10
CUDA
DP
(div
t)
X10
CUDA
SP
(div
t)
QUDA
SP
recon
18
QUDA
SP
recon
12
[1]:
Clark,
Michael
A.,
et
al.
"Solving
La1ce
QCD
systems
of
equaGons
using
mixed
precision
solvers
on
GPUs."
Computer
Physics
CommunicaGons
181.9
(2010):
1517-‐1528.