Traffic simulation software is becoming increasingly popular as more cities worldwide use it to better manage their crowded traffic networks. An important requirement for such software is the ability to produce accurate results in real time, requiring great computation resources. This work proposes an ASICbased hardware accelerated approach for the AIMSUN traffic simulator, taking advantage of repetitive tasks in the algorithm. Different system configurations using this accelerator are also discussed. Compared with the traditional software simulator, it has been found to improve the performance by as much as 9x when using a single processing element approach, or more depending on the chosen hardware configuration.
Visual analytics of 3D LiDAR point clouds in robotics operating systemsjournalBEEI
This paper presents visual analytics of 3D LiDAR point clouds in robotics operating system. In this study, experiment on simultaneous localization and mapping (SLAM) using point cloud data derived from the light detection and ranging (LiDAR) technology is conducted. We argue that one of the weaknesses of the SLAM algorithm is in the localization process of the landmarks. Existing algorithms such as grid mapping and monte carlo have limitations in dealing with 3D environment data that have led to less accurate estimation. Therefore, this research proposes the SLAM algorithm based on real-time appearance-based (RTAB) and makes use of the red green blue (RGB) camera for visualisation. The algorithm was tested by using the map data that was collected and simulated on the robot operating system (ROS) in Linux environment. We present the results and demonstrates that the map produced by RTAB is better compared to its counterparts. In addition, the probability for the estimated location is improved which allows for better vehicle maneuverability.
High-Speed Neural Network Controller for Autonomous Robot Navigation using FPGAiosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Visual analytics of 3D LiDAR point clouds in robotics operating systemsjournalBEEI
This paper presents visual analytics of 3D LiDAR point clouds in robotics operating system. In this study, experiment on simultaneous localization and mapping (SLAM) using point cloud data derived from the light detection and ranging (LiDAR) technology is conducted. We argue that one of the weaknesses of the SLAM algorithm is in the localization process of the landmarks. Existing algorithms such as grid mapping and monte carlo have limitations in dealing with 3D environment data that have led to less accurate estimation. Therefore, this research proposes the SLAM algorithm based on real-time appearance-based (RTAB) and makes use of the red green blue (RGB) camera for visualisation. The algorithm was tested by using the map data that was collected and simulated on the robot operating system (ROS) in Linux environment. We present the results and demonstrates that the map produced by RTAB is better compared to its counterparts. In addition, the probability for the estimated location is improved which allows for better vehicle maneuverability.
High-Speed Neural Network Controller for Autonomous Robot Navigation using FPGAiosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Vehicle Detection using Camera
Vehicle Detection Using Cameras for Self-Driving Cars |
Using machine learning and computer vision I create a pipeline that detects nearby vehicles from a dash-cam.
AN EFFICIENT SYSTEM FOR FORWARD COLLISION AVOIDANCE USING LOW COST CAMERA & E...aciijournal
Forward Collision Avoidance (FCA) systems in automobiles is an essential part of Advanced Driver Assistance System (ADAS) and autonomous vehicles. These devices currently use, radars as the main sensor. The increasing resolution of camera sensors, processing capability of hardware chipsets and advances in image processing algorithms, have been pushing the camera based features recently. Monocular cameras face the challenge of accurate scale estimation which limits it use as a stand-alone sensor for this application. This paper proposes an efficient system which can perform multi scale object
detection which is being patent granted and efficient 3D reconstruction using structure from motion (SFM)
framework. While the algorithms need to be accurate it also needs to operate real time in low cost
embedded hardware. The focus of the paper is to discuss how the proposed algorithms are designed in such
a way that it can be provide real time performance on low cost embedded CPU’s which makes use of only Digital Signal processors (DSP) and vector processing cores.
Road traffic jam becomes a serious issue for highly crowded metropolitan cities. India is that the
second most populated country within the world and may be a fast growing economy. it's facing terrible road
congestion within the cities. consistent with Times of India about 30 percent of deaths are caused thanks to delayed
ambulance to succeed in at hospital. In proposed system we try to scale back the delay for the ambulance. To
smoothen the ambulance movement, we come up with “Auto Traffic Management System”. We try to supply the
green signals for ambulance by switching the signals. We are getting to use the technologies like RFIDs. Whenever
signal detects the ambulance almost signal, then signal switches to green. As this technique is fully automated, it
recognize the ambulance and control traffic signals. this technique controls traffic signal and saves the time in
emergency period. Also we've automated camera which can help in monitoring the traffic jam . Thus it act as a
life saver project.
Monitoring traffic in urban areas is an important task for intelligent transport applications to alleviate the traffic problems like traffic jams and long trip times. The traffic flow in urban areas is more complicated than the traffic flow in highway, due to the slow movement of vehicles and crowded traffic flows in urban areas. In this paper, a vehicle detection and classification system at intersections is proposed. The system consists of three main phases: vehicle detection, vehicle tracking and vehicle classification. In the vehicle detection, the background subtraction is utilized to detect the moving vehicles by employing mixture of Gaussians (MoGs) algorithm, and then the removal shadow algorithm is developed to improve the detection phase and eliminate the undesired detected region (shadows). After the vehicle detection phase, the vehicles are tracked until they reach the classification line. Then the vehicle dimensions are utilized to classify the vehicles into three classes (cars, bikes, and trucks). In this system, there are three counters; one counter for each class. When the vehicle is classified to a specific class, the class counter is incremented by one. The counting results can be used to estimate the traffic density at intersections, and adjust the timing of traffic light for the next light cycle. The system is applied to videos obtained by stationary cameras. The results obtained demonstrate the robustness and accuracy of the proposed system.
A Solution to Partial Observability in Extended Kalman Filter Mobile Robot Na...TELKOMNIKA JOURNAL
Partial observability in EKF based mobile robot navigation is investigated in this paper to find a
solution that can prevent erroneous estimation. By only considering certain landmarks in an environment,
the computational cost in mobile robot can be reduced but with an increase of uncertainties to the system.
This is known as suboptimal condition of the system. Fuzzy Logic technique is proposed to ensure that the
estimation achieved desired performance even though some of the landmarks were excluded for
references. The Fuzzy Logic is applied to the measurement innovation of Kalman Filter to correct the
positions of both mobile robot and any observed landmarks during observations. The simulation results
shown that the proposed method is capable to secure reliable estimation results even a number of
landmarks being excluded from Kalman Filter update process in both Gaussian and non-Gaussian noise
conditions.
Vehicle Detection using Camera
Vehicle Detection Using Cameras for Self-Driving Cars |
Using machine learning and computer vision I create a pipeline that detects nearby vehicles from a dash-cam.
AN EFFICIENT SYSTEM FOR FORWARD COLLISION AVOIDANCE USING LOW COST CAMERA & E...aciijournal
Forward Collision Avoidance (FCA) systems in automobiles is an essential part of Advanced Driver Assistance System (ADAS) and autonomous vehicles. These devices currently use, radars as the main sensor. The increasing resolution of camera sensors, processing capability of hardware chipsets and advances in image processing algorithms, have been pushing the camera based features recently. Monocular cameras face the challenge of accurate scale estimation which limits it use as a stand-alone sensor for this application. This paper proposes an efficient system which can perform multi scale object
detection which is being patent granted and efficient 3D reconstruction using structure from motion (SFM)
framework. While the algorithms need to be accurate it also needs to operate real time in low cost
embedded hardware. The focus of the paper is to discuss how the proposed algorithms are designed in such
a way that it can be provide real time performance on low cost embedded CPU’s which makes use of only Digital Signal processors (DSP) and vector processing cores.
Road traffic jam becomes a serious issue for highly crowded metropolitan cities. India is that the
second most populated country within the world and may be a fast growing economy. it's facing terrible road
congestion within the cities. consistent with Times of India about 30 percent of deaths are caused thanks to delayed
ambulance to succeed in at hospital. In proposed system we try to scale back the delay for the ambulance. To
smoothen the ambulance movement, we come up with “Auto Traffic Management System”. We try to supply the
green signals for ambulance by switching the signals. We are getting to use the technologies like RFIDs. Whenever
signal detects the ambulance almost signal, then signal switches to green. As this technique is fully automated, it
recognize the ambulance and control traffic signals. this technique controls traffic signal and saves the time in
emergency period. Also we've automated camera which can help in monitoring the traffic jam . Thus it act as a
life saver project.
Monitoring traffic in urban areas is an important task for intelligent transport applications to alleviate the traffic problems like traffic jams and long trip times. The traffic flow in urban areas is more complicated than the traffic flow in highway, due to the slow movement of vehicles and crowded traffic flows in urban areas. In this paper, a vehicle detection and classification system at intersections is proposed. The system consists of three main phases: vehicle detection, vehicle tracking and vehicle classification. In the vehicle detection, the background subtraction is utilized to detect the moving vehicles by employing mixture of Gaussians (MoGs) algorithm, and then the removal shadow algorithm is developed to improve the detection phase and eliminate the undesired detected region (shadows). After the vehicle detection phase, the vehicles are tracked until they reach the classification line. Then the vehicle dimensions are utilized to classify the vehicles into three classes (cars, bikes, and trucks). In this system, there are three counters; one counter for each class. When the vehicle is classified to a specific class, the class counter is incremented by one. The counting results can be used to estimate the traffic density at intersections, and adjust the timing of traffic light for the next light cycle. The system is applied to videos obtained by stationary cameras. The results obtained demonstrate the robustness and accuracy of the proposed system.
A Solution to Partial Observability in Extended Kalman Filter Mobile Robot Na...TELKOMNIKA JOURNAL
Partial observability in EKF based mobile robot navigation is investigated in this paper to find a
solution that can prevent erroneous estimation. By only considering certain landmarks in an environment,
the computational cost in mobile robot can be reduced but with an increase of uncertainties to the system.
This is known as suboptimal condition of the system. Fuzzy Logic technique is proposed to ensure that the
estimation achieved desired performance even though some of the landmarks were excluded for
references. The Fuzzy Logic is applied to the measurement innovation of Kalman Filter to correct the
positions of both mobile robot and any observed landmarks during observations. The simulation results
shown that the proposed method is capable to secure reliable estimation results even a number of
landmarks being excluded from Kalman Filter update process in both Gaussian and non-Gaussian noise
conditions.
The information in this slide is very useful for me to do the assignment regarding the simulation in which we have to report together with the presentation...
Comparative study of optimization algorithms on convolutional network for aut...IJECEIAES
The last 10 years have been the decade of autonomous vehicles. Advances in intelligent sensors and control schemes have shown the possibility of real applications.
Deep learning, and in particular convolutional networks have become a fundamental
tool in the solution of problems related to environment identification, path planning,
vehicle behavior, and motion control. In this paper, we perform a comparative study of
the most used optimization strategies on the convolutional architecture residual neural network (ResNet) for an autonomous driving problem as a previous step to the
development of an intelligent sensor. This sensor, part of our research in reactive
systems for autonomous vehicles, aims to become a system for direct mapping of sensory information to control actions from real-time images of the environment. The
optimization techniques analyzed include stochastic gradient descent (SGD), adaptive gradient (Adagrad), adaptive learning rate (Adadelta), root mean square propagation (RMSProp), Adamax, adaptive moment estimation (Adam), nesterov-accelerated
adaptive moment estimation (Nadam), and follow the regularized leader (Ftrl). The
training of the deep model is evaluated in terms of convergence, accuracy, recall, and
F1-score metrics. Preliminary results show a better performance of the deep network
when using the SGD function as an optimizer, while the Ftrl function presents the
poorest performances.
Help the Genetic Algorithm to Minimize the Urban Traffic on IntersectionsIJORCS
Control of traffic lights at the intersections of the main issues is the optimal traffic. Intersections to regulate traffic flow of vehicles and eliminate conflicting traffic flows are used. Modeling and simulation of traffic are widely used in industry. In fact, the modeling and simulation of an industrial system is studied before creating economically and when it is affordable. The aim of this article is a smart way to control traffic. The first stage of the project with the objective of collecting statistical data (cycle time of each of the intersection of the lights of vehicles is waiting for a red light) steps where the data collection found optimal amounts next it is. Introduced by genetic algorithm optimization of parameters is performed. GA begin with coding step as a binary variable (the range specified by the initial data set is obtained) will start with an initial population and then a new generation of genetic operators mutation and crossover and will Finally, the members of the optimal fitness values are selected as the solution set. The optimal output of Petri nets CPN TOOLS modeling and software have been implemented. The results indicate that the performance improvement project in intersections traffic control systems. It is known that other data collected and enforced intersections of evolutionary methods such as genetic algorithms to reduce the waiting time for traffic lights behind the red lights and to determine the appropriate cycle.
HOMOGENEOUS MULTISTAGE ARCHITECTURE FOR REAL-TIME IMAGE PROCESSINGcscpconf
In this article, we present a new multistage architecture oriented to real-time complex processing applications. Given a set of rules, this proposed architecture allows the using of different communication links (point to point link, hardware router…) to connect unlimited number of parallel computing elements (software processors) to follow the increasing complexity of algorithms. In particular, this work brings out a parallel implementation of multihypothesis approach for road recognition application on the proposed Multiprocessor Systemon-Chip (MP-SoC) architecture. This algorithm is usually the main part of the lane keeping applications. Experimental results using images of a real road scene are presented. Using a low cost FPGA-based System-on-Chip, our hardware architecture is able to detect and recognize the roadsides in a time limit of 60 mSec. Moreover, we demonstrate that our multistage architecture may be used to achieve good speed-up in solving automotive applications.
Task Scheduling using Hybrid Algorithm in Cloud Computing Environmentsiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Integrated tripartite modules for intelligent traffic light systemIJECEIAES
The traffic in urban areas is primarily controlled by traffic lights, contributing to the excessive, if not properly installed, long waiting times for vehicles. The condition is compounded by the increasing number of road accidents involving pedestrians in cities across the world. Thus, this work presents an integrated tripartite module for an intelligent traffic light system. This system has enough ingredients for success that can solve the above challenges. The proposed system has three modules: the intelligent visual monitoring module, intelligent traffic light control module, and the intelligent recommendation module for emergency vehicles. The monitor module is a visual module capable of identifying the conditions of traffic in the streets. The intelligent traffic light control module configures many intersections in a city to improve the flow of vehicles. Finally, the intelligent recommendation module for emergency vehicles offers an optimal path for emergency vehicles. The evaluation of the proposed system has been carried out in Al-Sader city/Bagdad/Iraq. The intelligent recommendation module for the emergency vehicles module shows that the optimization rate average for the optimal path was in range 67.13% to 92%, where the intelligent traffic light control module shows that the optimization ratio was in range 86% to 91.8%.
A collection of mobile nodes is known as ad-hoc network in which wireless communication network is used to connect these mobile nodes. A major requirement on the MANET is to provide unidentifiability and unlinkability for mobile nodes During the last few decades, continuous progresses in wireless communications have opened new research fields in computer networking, goal of extending data networks connectivity to environments where wired solutions are impracticable. Among these, vehicular traffic is attracting a increasing attention from both academic and industry, due to the amount and importance of the related applications, ranging from road safety to traffic control, up to mobile entertainment. Vehicular Ad-hoc Network(VANETs) are self-organized networks built up from moving vehicles, and are part of the broader class of Mobile Ad-hoc Net- works(MANETs). Because of their peculiar characteristics, VANETs require the definition of specific networking techniques, whose feasibility and performance are usually tested by means of simulation. One of the main challenges posed by VANETs simulations is the faithful characterization of vehicular mobility at both macroscopic and microscopic levels, leads to realistic non-uniform distributions of cars and velocity, and unique connectivity dynamics. There are various secure routing protocols have been proposed, but the requirement is not satisfied. The existing protocols are unguarded to the attacks of fake routing packets. Simulation results have demonstrated the effectiveness of the proposed AODV protocol with improved performance as compared to the existing protocols.
cuSTINGER: Supporting Dynamic Graph Aigorithms for GPUs : NOTESSubhajit Sahu
Highlighted notes on cuSTINGER: Supporting Dynamic Graph Aigorithms for GPUs (compressed).
While doing research work under Prof. Kishore Kothapalli.
These people wrote the first data structure for maintaining dynamic graphs with NVIDIA CUDA GPUs. Unlike STINGER which uses a block linked-list and GT-STINGER which uses Array of Structures (AoS), here they instead used Structure of Arrays (SoA) which is not only more suitable to GPU memory access, but also allows smaller allocations modes (memory is a premium in GPU).
They use a custom memory manager which speeds up memory management (instead of using system memory manager). The data structure used is the standard adjacency list (CSR) and pointers are updated when edge list has to grow. It could handle
upto 10 million updates per second (large batch sizes), and ran a static graph algorithm (triangle counting) 1-10% slower. This shows that cuSTINGER can also be used with static graph algorithms. Dynamic graph algorithms should run much faster.
Similar to HARDWARE ACCELERATION OF THE GIPPS MODEL FOR REAL-TIME TRAFFIC SIMULATION (20)
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
PIP-MPU: FORMAL VERIFICATION OF AN MPUBASED SEPARATION KERNEL FOR CONSTRAINED...ijesajournal
Pip-MPU is a minimalist separation kernel for constrained devices (scarce memory and power resources).
In this work, we demonstrate high-assurance of Pip-MPU’s isolation property through formal verification.
Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit
(MPU). Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained
environment and targets equivalent security properties. The proofs verify that the memory blocks loaded in
the MPU adhere to the global partition tree model. We provide the basis of the MPU formalisation and the
demonstration of the formal verification strategy on two representative kernel services. The publicly
released proofs have been implemented and checked using the Coq Proof Assistant for three kernel
services, representing around 10000 lines of proof. To our knowledge, this is the first formal verification of
an MPU based separation kernel. The verification process helped discover a critical isolation-related bug.
International Journal of Embedded Systems and Applications (IJESA)ijesajournal
International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.
Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Embedded Systems & applications.
Pip-MPU: Formal Verification of an MPU-Based Separationkernel for Constrained...ijesajournal
Pip-MPU is a minimalist separation kernel for constrained devices (scarce memory and power resources). In this work, we demonstrate high-assurance of Pip-MPU’s isolation property through formal verification. Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit (MPU). Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained environment and targets equivalent security properties. The proofs verify that the memory blocks loaded in the MPU adhere to the global partition tree model. We provide the basis of the MPU formalisation and the demonstration of the formal verification strategy on two representative kernel services. The publicly released proofs have been implemented and checked using the Coq Proof Assistant for three kernel services, representing around 10000 lines of proof. To our knowledge, this is the first formal verification of an MPU based separation kernel. The verification process helped discover a critical isolation-related bug.
International Journal of Embedded Systems and Applications (IJESA)ijesajournal
International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.
Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Embedded Systems & applications.
Call for papers -15th International Conference on Wireless & Mobile Network (...ijesajournal
15th International Conference on Wireless & Mobile Network (WiMo 2023) is dedicated to addressing the challenges in the areas of wireless & mobile networks. The Conference looks for significant contributions to the Wireless and Mobile computing in theoretical and practical aspects. The Wireless and Mobile computing domain emerges from the integration among personal computing, networks, communication technologies, cellular technology, and the Internet Technology. The modern applications are emerging in the area of mobile ad hoc networks and sensor networks. This Conference is intended to cover contributions in both the design and analysis in the context of mobile, wireless, ad-hoc, and sensor networks. The goal of this Conference is to bring together researchers and practitioners from academia and industry to focus on advanced wireless and Mobile computing concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to.
Call for Papers -International Conference on NLP & Signal (NLPSIG 2023)ijesajournal
Scope & Topics
International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP).
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to:
Topics of interest include, but are not limited to, the following
Chunking/Shallow Parsing
Dialogue and Interactive Systems
Deep learning and NLP
Discourseand Pragmatics
Information Extraction, Retrieval, Text Mining
Interpretability and Analysis of Models for NLP
Language Grounding to Vision, Robotics and Beyond
Lexical Semantics
Linguistic Resources
Machine Learning for NLP
Machine Translation
NLP and Signal Processing
NLP Applications
Ontology
Paraphrasing/Entailment/Generation
Parsing/Grammatical Formalisms
Phonology, Morphology
POS tagging
Question Answering
Resources and Evaluation
Semantic Processing
Sentiment Analysis, Stylistic Analysis, and Argument Mining
Speech and Multimodality
Speech Recognition and Synthesis
Spoken Language Processing
Statistical and Knowledge based methods
Summarization
Theory and Formalism in NLP
Signal Processing & NLP
Computer Vision, Image Processing& NLP
NLP, AI & Signal
Paper Submission
Authors are invited to submit papers through the conference Submission System by May 06, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by International Journal on Cybernetics & Informatics (IJCI) (Confirmed).
Selected papers from NLPSIG 2023, after further revisions, will be published in the special issue of the following journals.
International Journal on Natural Language Computing (IJNLC)
International Journal of Ubiquitous Computing (IJU)
International Journal of Data Mining & Knowledge Management Process (IJDKP)
Signal & Image Processing : An International Journal (SIPIJ)
International Journal of Ambient Systems and Applications (IJASA)
International Journal of Grid Computing & Applications (IJGCA)
Important Dates
Submission Deadline : May 06, 2023
Authors Notification : May 25, 2023
Final Manuscript Due : June 08, 2023
International Conference on NLP & Signal (NLPSIG 2023)ijesajournal
International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP).
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to:
11th International Conference on Software Engineering & Trends (SE 2023)ijesajournal
11th International Conference on Software Engineering & Trends (SE 2023)
May 27 ~ 28, 2023, Vancouver, Canada
https://acsit2023.org/se/index
Scope & Topics
11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following.
Topics of interest include, but are not limited to, the following
The Software Process
Software Engineering Practice
Web Engineering
Quality Management
Managing Software Projects
Advanced Topics in Software Engineering
Multimedia and Visual Software Engineering
Software Maintenance and Testing
Languages and Formal Methods
Web-based Education Systems and Learning Applications
Software Engineering Decision Making
Knowledge-based Systems and Formal Methods
Search Engines and Information Retrieval
Paper Submission
Authors are invited to submit papers through the conference Submission System by April 08, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings (H index 35) in Computer Science & Information Technology (CS & IT) series (Confirmed).
Selected papers from SE 2023, after further revisions, will be published in the special issue of the following journals.
The International Journal of Software Engineering & Applications (IJSEA) -ERA indexed
International Journal of Computer Science, Engineering and Applications (IJCSEA)
Important Dates
Submission Deadline : April 08, 2023
Authors Notification : April 29, 2023
Final Manuscript Due : May 06, 2023
11th International Conference on Software Engineering & Trends (SE 2023)ijesajournal
11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following.
PERFORMING AN EXPERIMENTAL PLATFORM TO OPTIMIZE DATA MULTIPLEXINGijesajournal
This article is based on preliminary work on the OSI model management layers to optimized industrial
wired data transfer on low data rate wireless technology. Our previous contribution deal with the
development of a demonstrator providing CAN bus transfer frames (1Mbps) on a low rate wireless channel
provided by Zigbee technology. In order to be compatible with all the other industrial protocols, we
describe in this paper our contribution to design an innovative Wireless Device (WD) and a software tool,
which will aim to determine the best architecture (hardware/software) and wireless technology to be used
taking in account of the wired protocol requirements. To validate the proper functioning of this WD, we
will develop an experimental platform to test different strategies provided by our software tool. We can
consequently prove which is the best configuration (hardware/software) compared to the others by the
inclusion (inputs) of the required parameters of the wired protocol (load, binary rate, acknowledge
timeout) and the analysis of the WD architecture characteristics proposed (outputs) as the delay introduced
by system, buffer size needed, CPU speed, power consumption, meeting the input requirement. It will be
important to know whether gain comes from a hardware strategy with hardware accelerator e.g or a
software strategy with a more perf
GENERIC SOPC PLATFORM FOR VIDEO INTERACTIVE SYSTEM WITH MPMC CONTROLLERijesajournal
Today, a significant number of embedded systems focus on multimedia applications with almost insatiable demand for low-cost, high performance, and low power hardware cosumption. In this paper, we present a re-configurable and generic hardware platform for image and video processing. The proposed platform uses the benefits offered by the Field Programmable Gate Array (FPGA) to attain this goal. In this context,
a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processors, embedded memory, DDR, interface technologies, Digital Clock Managers (DCM) and MPMC.
The MPMC is an essential component for design performance tuning and real time video processing. We demonstrate the importance role of this interface in multi video applications. In fact, to successful the
deployment of DRAM it is mandatory to use a flexible and scalable interface. Our system introduces diverse modules, such as cut video detection, video zoom-in and out. This provides the utility of using this architecture as a universal video processing platform according to different application requirements. This platform facilitates the development of video and image processing applications.
This paper presents an inverting buck-boost DCDC converter design. A negative supply voltage is needed
in a variety of applications, but only a few DCDC converters are available on the market. OLED, a new
display type especially suited for small digital camera or mobile phone displays. Design challenges that
came up when negative voltages have to be handled on chip will be discussed, such as
continuous/discontinuous mode transition problems, negative voltage feedback and negative over-voltage
protection. Both devices operate in a fixed frequency PWM mode or alternatively in PFM mode. The single
inductor topology is called inverting buck-boost converter or simply inverter. The proposed converter has
been implemented with a TSMC 0.13-um 2P4M CMOS process, and the chip area is 325 x 300 um2.
A Case Study: Task Scheduling Methodologies for High Speed Computing Systems ijesajournal
High Speed computing meets ever increasing real-time computational demands through the leveraging of
flexibility and parallelism. The flexibility is achieved when computing platform designed with
heterogeneous resources to support multifarious tasks of an application where as task scheduling brings
parallel processing. The efficient task scheduling is critical to obtain optimized performance in
heterogeneous computing Systems (HCS). In this paper, we brought a review of various application
scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In
this paper, we made a review of various scheduling methodologies targeted to high speed computing
systems and also prepared summary chart. The comparative study of scheduling methodologies for high
speed computing systems has been carried out based on the attributes of platform & application as well.
The attributes are execution time, nature of task, task handling capability, type of host & computing
platform. Finally a summary chart has been prepared and it demonstrates that the need of developing
scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an
emerging high speed computing platform for real time applications.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
Payment industry is largely aligned in their desire to create embedded payment systems ready for the
modern digital age. The trend to embed payments into a software platform is often regarded as first step
towards a broader trend of embedded finance based on digital representation of fiat currencies. Since it
became clear to our research team that there are no technologies and protocols that are protected against
attacks of quantum computing, and that enable automatic embedded payments, online or offline with no
fear of counterfeit, P2P or device-to-device to be made in real time without intermediaries, in any
denomination, even continuous payments per time or service, while preserving the privacy of all parties,
without enabling illicit activities, we decided to utilize the Generic Innovation Engine [1] that is based on
the Artificial Intelligence Assistance Innovation acceleration methodologies and tools in order to boost the
progress of innovation of the necessary solutions. These methodologies accelerate innovation across the
board. It proposes a framework for natural and artificial intelligence collaboration in pursuit of an
innovative (R&D) objective The outcome of deploying these Artificial Innovation Assistant (AIA)
methodologies was tens of patents that yield solutions, that a few of them are described in this paper. We
argue that a promising avenue for automated embedded payment systems to fulfil people’s desire for
privacy when conducting payments, and national security agencies demand for quantum-safe security,
could be based on DeFi and digital currencies platforms that does not suffer from flaws of DLT-based
solutions, while introducing real advantages, in all aspects, including being quantum-resilient, enabling
users to decide with whom, if at all, to share information, identity, transactions details, etc., all without
trade-offs, complying with AML measures, and accommodating the potential for high transaction volumes.
It is not legacy bank accounts, and it is not peer-dependent, nor a self-organizing network.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
2 nd International Conference on Computing and Information Technology ijesajournal
2
nd International Conference on Computing and Information Technology Trends
(CCITT 2023) will provide an excellent international forum for sharing knowledge and
results in theory, methodology and applications of Computing and Information Technology
Trends. The Conference looks for significant contributions to all major fields of the
Computer Science, Compute Engineering, Information Technology and Trends in theoretical
and practical aspects.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
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Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
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Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
While the dev and ops silo continues to crumble….many organizations still relegate monitoring & observability as the purview of ops, infra and SRE teams. This is a mistake - achieving a highly observable system requires collaboration up and down the stack.
I, a former op, would like to extend an invitation to all application developers to join the observability party will share these foundational concepts to build on:
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Discover how Changi Airport Group (CAG) leverages graph technologies and generative AI to revolutionize their search capabilities. This session delves into the unique search needs of CAG’s diverse passengers and customers, showcasing how graph data structures enhance the accuracy and relevance of AI-generated search results, mitigating the risk of “hallucinations” and improving the overall customer journey.
UiPath Test Automation using UiPath Test Suite series, part 6DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 6. In this session, we will cover Test Automation with generative AI and Open AI.
UiPath Test Automation with generative AI and Open AI webinar offers an in-depth exploration of leveraging cutting-edge technologies for test automation within the UiPath platform. Attendees will delve into the integration of generative AI, a test automation solution, with Open AI advanced natural language processing capabilities.
Throughout the session, participants will discover how this synergy empowers testers to automate repetitive tasks, enhance testing accuracy, and expedite the software testing life cycle. Topics covered include the seamless integration process, practical use cases, and the benefits of harnessing AI-driven automation for UiPath testing initiatives. By attending this webinar, testers, and automation professionals can gain valuable insights into harnessing the power of AI to optimize their test automation workflows within the UiPath ecosystem, ultimately driving efficiency and quality in software development processes.
What will you get from this session?
1. Insights into integrating generative AI.
2. Understanding how this integration enhances test automation within the UiPath platform
3. Practical demonstrations
4. Exploration of real-world use cases illustrating the benefits of AI-driven test automation for UiPath
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What is generative AI
Test Automation with generative AI and Open AI.
UiPath integration with generative AI
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Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
How to Get CNIC Information System with Paksim Ga.pptxdanishmna97
Pakdata Cf is a groundbreaking system designed to streamline and facilitate access to CNIC information. This innovative platform leverages advanced technology to provide users with efficient and secure access to their CNIC details.
Alt. GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using ...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
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Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
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GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
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HARDWARE ACCELERATION OF THE GIPPS MODEL FOR REAL-TIME TRAFFIC SIMULATION
1. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.1, March 2013
HARDWARE ACCELERATION OF THE GIPPS MODEL
FOR REAL-TIME TRAFFIC SIMULATION
Salim Farah1 and Magdy Bayoumi2
The Center for Advanced Computer Studies, University of Louisiana at Lafayette, USA
1 2
snf3346@cacs.louisiana.edu, mab@cacs.louisiana.edu
ABSTRACT
Traffic simulation software is becoming increasingly popular as more cities worldwide use it to better
manage their crowded traffic networks. An important requirement for such software is the ability to
produce accurate results in real time, requiring great computation resources. This work proposes an ASIC-
based hardware accelerated approach for the AIMSUN traffic simulator, taking advantage of repetitive
tasks in the algorithm. Different system configurations using this accelerator are also discussed. Compared
with the traditional software simulator, it has been found to improve the performance by as much as 9x
when using a single processing element approach, or more depending on the chosen hardware
configuration.
KEYWORDS
Traffic Simulation, Gipps Model, AIMSUN, ASIC
1. INTRODUCTION
The steady improvement in computation power has allowed for many applications previously
limited only to super-computers and data centers. Traffic simulation is one application that has
begun to gain popularity in recent years, especially in cities with notoriously busy traffic
networks such as Madrid and Singapore. The technology is used in either the design or operation
phase of a transportation network. During design, simulation helps decide upon the most efficient
and reliable configuration, while simulation during traffic operation allows for predicting rush
hours and traffic flow, as well as effective rerouting in case of road closures.
1.1 Traffic Simulators Overview
Traffic simulators are handed the system data from road traffic sensors, and already have the
information about the road network and its layout. Simulating traffic flow can be performed in
three methods. In the macroscopic method, the traffic system is modeled at no lower than the road
level and the density at the given road stretches. From there the flow development is carried out
[1]. On the other hand, the microscopic method simulates at the car level, following each car's
movement. Combining all the individual car behaviors, the overall traffic flow can be obtained.
In the middle sits the mesoscopic method which is a trade-off between the two. The microscopic
method offers the greatest accuracy at the expense of computation time, while the macroscopic
approach will produce a less accurate result in a more timely fashion.
A number of traffic simulators exist, some of which are commercially sold and widely used in a
variety of fields. These simulators have been evolving for a while, and it's safe to say they've
reached a mature state where they can perform at a reasonable speed and produce trusted results.
AIMSUN and VISSIM [2] are two popular commercial traffic simulators used by a number of
traffic engineering firms and transportation planning agencies. AIMSUN is allegedly capable of
DOI : 10.5121/ijesa.2013.3103 33
2. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.1, March 2013
microscopic simulation of traffic in a big-sized city with a speed 60x faster than that of real time,
or in other words simulates 1 hour in 1 minute.
1.2 Related Work
The previously discussed simulators are purely software-based, as are most implementations.
However, there have been a few proposed FPGA-based implementations. One work combines
microprocessors with FPGAs in a low-bandwidth, high-latency interconnect, dividing the tasks
between software and hardware to balance the workloads [3]. It claims to reduce the number of
needed FPGAs and to achieve a speedup of 12.8x over an AMD processor. Another FPGA design
centers around modeling the route system as a collection of interconnected cells, each cell
representing a short segment of a roadway and can be either empty or containing a single car [4].
The authors claim to be able to effectively model various geometric configurations of a traffic
system by hierarchically combining the cells.
1.3 Performance Requirements
A timely response is the obvious prime requirement of real-time simulation systems. Delays
cannot be tolerated in a traffic environment. Once a traffic congestion has been formed, it is hard
to reverse it due to the unidirectional nature of vehicle movement, and on busy highways
congestions can form in a matter of seconds in a major incident. Reacting as quickly as possible is
therefore a must, and this entails a very efficient simulation of any decision the system might
decide to take.
An important thing to note is that upon deciding on a response strategy, a potentially large
number of possible actions are simulated. Having a computing infrastructure capable of parallel
processing is therefore desirable. Still, some of the simulations may be related to each other and
depend on each other's results, and parallelizing them may not be possible. Simulation runs will in
this case add up in time and a 1 minute run would add up to 15 minutes if performed in 15
different instances.
2. PROPOSED HARDWARE ACCELERATION
2.1. Choice of Simulation Model
Traffic simulators usually make use of two important models: the car-following model and the
lane-switching model. This work is only concerned with the car-following model, although it
could be extended to the lane-switching model if desired. The car-following model itself is
modeled differently in different simulators. VISSIM and AIMSUN are two of the most widely
used traffic simulators, and they employ different car-following models. The AIMSUN model
was ultimately chosen for the hardware acceleration, for the two following reasons.
Firstly, the AIMSUN simulator uses the Gipps car-following model, a model represented
mathematically through an algebraic equation, as opposed to the model used in VISSIM, which is
based on a psychological model that tries to mimic the behavior of the driver [5]. Mapping a
mathematical equation to hardware is more straightforward than trying to accelerate a complex
psychological model that relies on statistical decisions and specialized algorithms. The
mathematical nature of the Gipps model in AIMSUN allows the use of common hardware units
such as dividers and multipliers, and the reuse of such items in case the hardware unit is to be
used to accelerate other tasks as well.
The second reason for choosing AIMSUN is simply its superior accuracy, as was concluded in
[5]. Accuracy is not to be underestimated in traffic simulators as errors would accumulate
34
3. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.1, March 2013
considering cars are all affected by each others' movements. AIMSUN was found to produce
fewer errors when taking real life situations as a reference.
The following is the primary equation representing the Gipps car-following model:
, (1)
where
V(n, t) is the speed of vehicle n at time t,
V∗(n) is the desired speed of vehicle n,
a(n) is the maximum acceleration for vehicle n,
T is the reaction time (this is equal to simulation step).
The actual model is a little more complicated than this, it uses an additional equation for
calculating the velocity value and then chooses the lower of the two values from the two
equations. However only the above equation will be accelerated here, but the same concept can be
applied to that second equation. This work hopes to show the potential of accelerating the Gipps
model, more so than performing a full-fledged acceleration. This is the reason why only part of
the model was accelerated.
2.2 Assumed System Organization
It was assumed that only the equation above was moved to hardware while the rest of the
software constituting the simulator is still unchanged. That is the code in the simulator
responsible for carrying out the calculation above is now replaced by one instruction that
performs this task. This instruction requires 4 operands: acceleration, time step, desired velocity,
and current velocity. These can be stored in special memory registers or locations prior to
executing the instruction.
Figure 1. Illustration of how an array of accelerators can concurrently simulate different cars
The hardware accelerator module can be either added to the internals of the general purpose CPU,
or installed as an add-on via some fast connection protocol like PCI Express. In the latter solution
the module would occupy the whole chip, therefore giving it a much larger area and power
budget. This in turn allows for the use of multiple modules on a single chip, performing parallel
calculations that correspond to modeling several cars simultaneously. The simulation would thus
35
4. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.1, March 2013
be accelerated by several orders of magnitude, even when accounting for the communication
overhead due the bus CPU connection.
2.3 Hardware Architecture
As is evident in the equation discussed above, the hardware units that will be needed are an adder,
a multiplier, and a divider. Given these units, it's still required to perform the square root
operation. The multiplier and divider units shall be discussed first, and subsequently the square
root implementation shall be dealt with. But before that, it's worth discussing the word width that
is being assumed. Given that the maximum speed anyone is likely to achieve is below 256 km/h,
8 bits should be assigned to represent both the speed and the acceleration. However, given that
the equation also deals with decimal points, 6 more bits were assigned as fixed decimal point bits.
These allow for an accuracy of 0.0156, i.e. an error of ± 0.008, which should be acceptable for the
given application. In all, 14 bits were used to represent the numbers in use.
Figure 2. The high level organization of the hardware accelerator
For the multiplier, an entirely combinational approach was chosen, since the main target of this
work is speed and performance. With a 14-bit word, the multiplier had to use 14 14-bit adders,
adding up to 196 full adder cells. The same goes for the divider, which uses 14 14-bit subtracters,
which are essentially adders with an added inverter on one of the inputs. Obviously, significant
area is being occupied by just the multiplier and the divider. But these two units take the vast
majority of the design and everything else takes insignificant area in comparison. For instance the
square root unit already makes use of the available divider, adding only little hardware to that,
and the control unit for the design is also small in comparison. Moreover, it should be kept in
mind that we're mainly assuming the accelerator will be on a chip by itself.
The Babylonian method was used for the computation of the square root. Initially a rough
estimation based on the number of bits to the right of the first '1' in the number is done, giving a
starting point close to the solution so that the unit would converge much faster. Subsequently, the
following operation is conducted multiple times until it converges to a constant number:
, (2)
36
5. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.1, March 2013
where S is the number the square root of which is being sought. It was observed that it only took
two clock cycles (or iterations) at most for the operation to converge to a constant value, due
mainly to a relatively accurate estimation done beforehand.
Figure 3. Area distribution of the accelerator. Total area was 7016 μm2.
3. RESULTS
The Verilog code for the accelerator was synthesized with a 45 nm standard cell library
(FreePDK45). The operating frequency was set to be 250 MHz, which is about the highest the
design could reach without timing violations. Although this may seem like too low for such an
advanced technology, the entire computation only takes 4 clock cycles, or 16 ns. If desired,
however, the clock frequency may be significantly increased if instead of entirely combinational
dividers and multipliers, hybrid ones were used that take a few clock cycles to complete one
division or multiplication operation. That would also dercease the area of these units due to the
reuse of the adders/subtracters. When considering packing several of these accelerators on one
chip, this becomes especially important. The implemented design occupies an area of 7016 μm2
with an estimated power consumption of 2.3 mW.
This result was compared with an estimation of the time required to complete the computation of
the Gipps model equation on a general purpose processor. A short program that performs the
same computation was written in C, and was run on an Intel Core i3-350M processor, which is a
mid-range dual core processor with 3 MB of cache, and 2 threads per core, making a total of 4
virtual cores. The computer was running a Linux 64-bit OS, and has a total of 4 GB of RAM.
Code profiling functions were added to the C program to measure the execution time, and the
computation was run for 100 iterations in order to average out any inaccuracies in the profiling
measurement. The average execution time was 144 ns, which is 9x slower than the hardware
accelerator. When using multiple processing elements of the accelerator, this speedup would be
multiplied by the number of PEs in use.
4. CONCLUSION
The use of hardware accelerators for improving the performance of the AIMSUN traffic simulator
has been shown to be significantly effective. The hardware accelerator uses high performance
multiplication and division units, and is able to perform an accurate square root operation in only
two clock cycles. By comparison, the software code written in C and performing the same
computation was 9x slower. The obtained speedup would in fact be multiplied when the
37
6. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.1, March 2013
accelerator includes several computation units working in parallel, which is feasible when the
accelerator is implemented off-chip. Future work could concentrate on finding an efficient way
for using and placing an array of acceleration modules working concurrently on a single chip.
REFERENCES
[1] Magne L., S. Rabut, and J. F. Gabard, (2000) “Towards an Hybrid Macro Micro Traffic Flow
Simulation Model”, INFORMS Spring 2000 Meeting, Salt Lake City, Utah, U.S.A.
[2] H. Xiao, R. Ambadipudi, et al, (2005) “Methodology for Selecting Microscopic Simulators:
Comparative Evaluation of AIMSUN and VISSIM”, Technical Report CTS 05-05, Department of
Civil Engineering, Univ. of Minnesota.
[3] Ttipp , J. L., Mortveit , H. S., Hansson , A. A., Gokhale , M, (2005) “Metropolitan Road Traffic
Simulation on FPGAs”, Proceedings of the IEEE Symposium on Field-Programmable Custom
Computing Machines.
[4] Gordon Russell, Paul Shaw, John McInnes, Neil Ferguson, and George Milne, (1995) “The Rapid
Simulation of Urban Traffic Using Field-Programmable Gate Arrays”, Proceedings of the
International Conference on the Application of New Technologies to Transport Systems,
Australasian Road Research Board Ltd.
[5] S. Panwai, H. Dia, (2005) "Comparative Evaluation of Microscopic Car-Following Behavior",
IEEE Transactions on Intelligent Transportation Systems, Volume 6, Issue 3 Pp. 314--325.
38