Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
Task scheduling methodologies for high speed computing systemsijesajournal
High Speed computing meets ever increasing real-time computational demands through the leveraging of
flexibility and parallelism. The flexibility is achieved when computing platform designed with
heterogeneous resources to support multifarious tasks of an application where as task scheduling brings
parallel processing. The efficient task scheduling is critical to obtain optimized performance in
heterogeneous computing Systems (HCS). In this paper, we brought a review of various application
scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In
this paper, we made a review of various scheduling methodologies targeted to high speed computing
systems and also prepared summary chart. The comparative study of scheduling methodologies for high
speed computing systems has been carried out based on the attributes of platform & application as well.
The attributes are execution time, nature of task, task handling capability, type of host & computing
platform. Finally a summary chart has been prepared and it demonstrates that the need of developing
scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an
emerging high speed computing platform for real time applications.
A Case Study: Task Scheduling Methodologies for High Speed Computing Systems ijesajournal
High Speed computing meets ever increasing real-time computational demands through the leveraging of
flexibility and parallelism. The flexibility is achieved when computing platform designed with
heterogeneous resources to support multifarious tasks of an application where as task scheduling brings
parallel processing. The efficient task scheduling is critical to obtain optimized performance in
heterogeneous computing Systems (HCS). In this paper, we brought a review of various application
scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In
this paper, we made a review of various scheduling methodologies targeted to high speed computing
systems and also prepared summary chart. The comparative study of scheduling methodologies for high
speed computing systems has been carried out based on the attributes of platform & application as well.
The attributes are execution time, nature of task, task handling capability, type of host & computing
platform. Finally a summary chart has been prepared and it demonstrates that the need of developing
scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an
emerging high speed computing platform for real time applications.
Reconfiguration Strategies for Online Hardware Multitasking in Embedded SystemsCSEIJJournal
An intensive use of reconfigurable hardware is expected in future embedded systems. This means that the
system has to decide which tasks are more suitable for hardware execution. In order to make an efficient
use of the FPGA it is convenient to choose one that allows hardware multitasking, which is implemented by
using partial dynamic reconfiguration. One of the challenges for hardware multitasking in embedded
systems is the online management of the only reconfiguration port of present FPGA devices. This paper
presents different online reconfiguration scheduling strategies which assign the reconfiguration interface
resource using different criteria: workload distribution or task’ deadline. The online scheduling strategies
presented take efficient and fast decisions based on the information available at each moment. Experiments
have been made in order to analyze the performance and convenience of these reconfiguration strategies.
Sharing of cluster resources among multiple Workflow Applicationsijcsit
Many computational solutions can be expressed as workflows. A Cluster of processors is a shared
resource among several users and hence the need for a scheduler which deals with multi-user jobs
presented as workflows. The scheduler must find the number of processors to be allotted for each workflow
and schedule tasks on allotted processors. In this work, a new method to find optimal and maximum
number of processors that can be allotted for a workflow is proposed. Regression analysis is used to find
the best possible way to share available processors, among suitable number of submitted workflows. An
instance of a scheduler is created for each workflow, which schedules tasks on the allotted processors.
Towards this end, a new framework to receive online submission of workflows, to allot processors to each
workflow and schedule tasks, is proposed and experimented using a discrete-event based simulator. This
space-sharing of processors among multiple workflows shows better performance than the other methods
found in literature. Because of space-sharing, an instance of a scheduler must be used for each workflow
within the allotted processors. Since the number of processors for each workflow is known only during
runtime, a static schedule can not be used. Hence a hybrid scheduler which tries to combine the advantages
of static and dynamic scheduler is proposed. Thus the proposed framework is a promising solution to
multiple workflows scheduling on cluster.
RSDC (Reliable Scheduling Distributed in Cloud Computing)IJCSEA Journal
In this paper we will present a reliable scheduling algorithm in cloud computing environment. In this algorithm we create a new algorithm by means of a new technique and with classification and considering request and acknowledge time of jobs in a qualification function. By evaluating the previous algorithms, we understand that the scheduling jobs have been performed by parameters that are associated with a failure rate. Therefore in the roposed algorithm, in addition to previous parameters, some other important parameters are used so we can gain the jobs with different scheduling based on these parameters. This work is associated with a mechanism. The major job is divided to sub jobs. In order to balance the jobs we should calculate the request and acknowledge time separately. Then we create the scheduling of each job by calculating the request and acknowledge time in the form of a shared job. Finally efficiency of the system is increased. So the real time of this algorithm will be improved in comparison with the other algorithms. Finally by the mechanism presented, the total time of processing in cloud computing is improved in comparison with the other algorithms.
Reinforcement learning based multi core scheduling (RLBMCS) for real time sys...IJECEIAES
Embedded systems with multi core processors are increasingly popular because of the diversity of applications that can be run on it. In this work, a reinforcement learning based scheduling method is proposed to handle the real time tasks in multi core systems with effective CPU usage and lower response time. The priority of the tasks is varied dynamically to ensure fairness with reinforcement learning based priority assignment and Multi Core MultiLevel Feedback queue (MCMLFQ) to manage the task execution in multi core system
Task scheduling methodologies for high speed computing systemsijesajournal
High Speed computing meets ever increasing real-time computational demands through the leveraging of
flexibility and parallelism. The flexibility is achieved when computing platform designed with
heterogeneous resources to support multifarious tasks of an application where as task scheduling brings
parallel processing. The efficient task scheduling is critical to obtain optimized performance in
heterogeneous computing Systems (HCS). In this paper, we brought a review of various application
scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In
this paper, we made a review of various scheduling methodologies targeted to high speed computing
systems and also prepared summary chart. The comparative study of scheduling methodologies for high
speed computing systems has been carried out based on the attributes of platform & application as well.
The attributes are execution time, nature of task, task handling capability, type of host & computing
platform. Finally a summary chart has been prepared and it demonstrates that the need of developing
scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an
emerging high speed computing platform for real time applications.
A Case Study: Task Scheduling Methodologies for High Speed Computing Systems ijesajournal
High Speed computing meets ever increasing real-time computational demands through the leveraging of
flexibility and parallelism. The flexibility is achieved when computing platform designed with
heterogeneous resources to support multifarious tasks of an application where as task scheduling brings
parallel processing. The efficient task scheduling is critical to obtain optimized performance in
heterogeneous computing Systems (HCS). In this paper, we brought a review of various application
scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In
this paper, we made a review of various scheduling methodologies targeted to high speed computing
systems and also prepared summary chart. The comparative study of scheduling methodologies for high
speed computing systems has been carried out based on the attributes of platform & application as well.
The attributes are execution time, nature of task, task handling capability, type of host & computing
platform. Finally a summary chart has been prepared and it demonstrates that the need of developing
scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an
emerging high speed computing platform for real time applications.
Reconfiguration Strategies for Online Hardware Multitasking in Embedded SystemsCSEIJJournal
An intensive use of reconfigurable hardware is expected in future embedded systems. This means that the
system has to decide which tasks are more suitable for hardware execution. In order to make an efficient
use of the FPGA it is convenient to choose one that allows hardware multitasking, which is implemented by
using partial dynamic reconfiguration. One of the challenges for hardware multitasking in embedded
systems is the online management of the only reconfiguration port of present FPGA devices. This paper
presents different online reconfiguration scheduling strategies which assign the reconfiguration interface
resource using different criteria: workload distribution or task’ deadline. The online scheduling strategies
presented take efficient and fast decisions based on the information available at each moment. Experiments
have been made in order to analyze the performance and convenience of these reconfiguration strategies.
Sharing of cluster resources among multiple Workflow Applicationsijcsit
Many computational solutions can be expressed as workflows. A Cluster of processors is a shared
resource among several users and hence the need for a scheduler which deals with multi-user jobs
presented as workflows. The scheduler must find the number of processors to be allotted for each workflow
and schedule tasks on allotted processors. In this work, a new method to find optimal and maximum
number of processors that can be allotted for a workflow is proposed. Regression analysis is used to find
the best possible way to share available processors, among suitable number of submitted workflows. An
instance of a scheduler is created for each workflow, which schedules tasks on the allotted processors.
Towards this end, a new framework to receive online submission of workflows, to allot processors to each
workflow and schedule tasks, is proposed and experimented using a discrete-event based simulator. This
space-sharing of processors among multiple workflows shows better performance than the other methods
found in literature. Because of space-sharing, an instance of a scheduler must be used for each workflow
within the allotted processors. Since the number of processors for each workflow is known only during
runtime, a static schedule can not be used. Hence a hybrid scheduler which tries to combine the advantages
of static and dynamic scheduler is proposed. Thus the proposed framework is a promising solution to
multiple workflows scheduling on cluster.
RSDC (Reliable Scheduling Distributed in Cloud Computing)IJCSEA Journal
In this paper we will present a reliable scheduling algorithm in cloud computing environment. In this algorithm we create a new algorithm by means of a new technique and with classification and considering request and acknowledge time of jobs in a qualification function. By evaluating the previous algorithms, we understand that the scheduling jobs have been performed by parameters that are associated with a failure rate. Therefore in the roposed algorithm, in addition to previous parameters, some other important parameters are used so we can gain the jobs with different scheduling based on these parameters. This work is associated with a mechanism. The major job is divided to sub jobs. In order to balance the jobs we should calculate the request and acknowledge time separately. Then we create the scheduling of each job by calculating the request and acknowledge time in the form of a shared job. Finally efficiency of the system is increased. So the real time of this algorithm will be improved in comparison with the other algorithms. Finally by the mechanism presented, the total time of processing in cloud computing is improved in comparison with the other algorithms.
Reinforcement learning based multi core scheduling (RLBMCS) for real time sys...IJECEIAES
Embedded systems with multi core processors are increasingly popular because of the diversity of applications that can be run on it. In this work, a reinforcement learning based scheduling method is proposed to handle the real time tasks in multi core systems with effective CPU usage and lower response time. The priority of the tasks is varied dynamically to ensure fairness with reinforcement learning based priority assignment and Multi Core MultiLevel Feedback queue (MCMLFQ) to manage the task execution in multi core system
SURVEY ON SCHEDULING AND ALLOCATION IN HIGH LEVEL SYNTHESIScscpconf
This paper presents the detailed survey of scheduling and allocation techniques in the High Level Synthesis (HLS) presented in the research literature. It also presents the methodologies and techniques to improve the Speed, (silicon) Area and Power in High Level Synthesis, which are presented in the research literature.
Many computational solutions can be expressed as Di
rected Acyclic Graph (DAG), in which
nodes represent tasks to be executed and edges repr
esent precedence constraints among tasks.
A Cluster of processors is a shared resource among
several users and hence the need for a
scheduler which deals with multi-user jobs presente
d as DAGs. The scheduler must find the
number of processors to be allotted for each DAG an
d schedule tasks on allotted processors. In
this work, a new method to find optimal and maximum
number of processors that can be allotted
for a DAG is proposed. Regression analysis is used
to find the best possible way to share
available processors, among suitable number of subm
itted DAGs. An instance of a scheduler
for each DAG, schedules tasks on the allotted proce
ssors. Towards this end, a new framework
to receive online submission of DAGs, allot process
ors to each DAG and schedule tasks, is
proposed and experimented using a simulator. This s
pace-sharing of processors among multiple
DAGs shows better performance than the other method
s found in literature. Because of space-
sharing, an online scheduler can be used for each D
AG within the allotted processors. The use
of online scheduler overcomes the drawbacks of stat
ic scheduling which relies on inaccurate
estimated computation and communication costs. Thus
the proposed framework is a promising
solution to perform online scheduling of tasks usin
g static information of DAG, a kind of hybrid
scheduling
.
MULTIPLE DAG APPLICATIONS SCHEDULING ON A CLUSTER OF PROCESSORScscpconf
Many computational solutions can be expressed as Directed Acyclic Graph (DAG), in which
nodes represent tasks to be executed and edges represent precedence constraints among tasks.
A Cluster of processors is a shared resource among several users and hence the need for a
scheduler which deals with multi-user jobs presented as DAGs. The scheduler must find the
number of processors to be allotted for each DAG and schedule tasks on allotted processors. In
this work, a new method to find optimal and maximum number of processors that can be allotted
for a DAG is proposed. Regression analysis is used to find the best possible way to share
available processors, among suitable number of submitted DAGs. An instance of a scheduler
for each DAG, schedules tasks on the allotted processors. Towards this end, a new framework
to receive online submission of DAGs, allot processors to each DAG and schedule tasks, is
proposed and experimented using a simulator. This space-sharing of processors among multiple
DAGs shows better performance than the other methods found in literature. Because of spacesharing,
an online scheduler can be used for each DAG within the allotted processors. The use
of online scheduler overcomes the drawbacks of static scheduling which relies on inaccurate
estimated computation and communication costs. Thus the proposed framework is a promising
solution to perform online scheduling of tasks using static information of DAG, a kind of hybrid
scheduling.
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTINGcscpconf
Parallel computing systems compose task partitioning strategies in a true multiprocessing
manner. Such systems share the algorithm and processing unit as computing resources which
leads to highly inter process communications capabilities. The main part of the proposed
algorithm is resource management unit which performs task partitioning and co-scheduling .In
this paper, we present a technique for integrated task partitioning and co-scheduling on the
privately owned network. We focus on real-time and non preemptive systems. A large variety of
experiments have been conducted on the proposed algorithm using synthetic and real tasks.
Goal of computation model is to provide a realistic representation of the costs of programming
The results show the benefit of the task partitioning. The main characteristics of our method are
optimal scheduling and strong link between partitioning, scheduling and communication. Some
important models for task partitioning are also discussed in the paper. We target the algorithm
for task partitioning which improve the inter process communication between the tasks and use
the recourses of the system in the efficient manner. The proposed algorithm contributes the
inter-process communication cost minimization amongst the executing processes.
Cost-Efficient Task Scheduling with Ant Colony Algorithm for Executing Large ...Editor IJCATR
The aim of cloud computing is to share a large number of resources and pieces of equipment to compute and store knowledge and information for great scientific sources. Therefore, the scheduling algorithm is regarded as one of the most important challenges and problems in the cloud. To solve the task scheduling problem in this study, the ant colony optimization (ACO) algorithm was adapted from social theories with a fair and accurate resource allocation approach based on machine performance and capacity. This study was intended to decrease the runtime and executive costs. It was also meant to optimize the use of machines and reduce their idle time. Finally, the proposed method was compared with Berger and greedy algorithms. The simulation results indicate that the proposed algorithm reduced the makespan and executive cost when tasks were added. It also increased fairness and load balancing. Moreover, it made the optimal use of machines possible and increased user satisfaction. According to evaluations, the proposed algorithm improved the makespan by 80%.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Cloud computing is an emerging technology. It process huge amount of data so scheduling mechanism
works as a vital role in the cloud computing. Thus my protocol is designed to minimize the switching time,
improve the resource utilization and also improve the server performance and throughput. This method or
protocol is based on scheduling the jobs in the cloud and to solve the drawbacks in the existing protocols.
Here we assign the priority to the job which gives better performance to the computer and try my best to
minimize the waiting time and switching time. Best effort has been made to manage the scheduling of jobs
for solving drawbacks of existing protocols and also improvise the efficiency and throughput of the server.
GROUPING BASED JOB SCHEDULING ALGORITHM USING PRIORITY QUEUE AND HYBRID ALGOR...ijgca
Grid computing enlarge with computing platform which is collection of heterogeneous computing resources connected by a network across dynamic and geographically dispersed organization to form a distributed high performance computing infrastructure. Grid computing solves the complex computing
problems amongst multiple machines. Grid computing solves the large scale computational demands in a high performance computing environment. The main emphasis in the grid computing is given to the resource management and the job scheduler .The goal of the job scheduler is to maximize the resource utilization and minimize the processing time of the jobs. Existing approaches of Grid scheduling doesn’t give much emphasis on the performance of a Grid scheduler in processing time parameter. Schedulers allocate resources to the jobs to be executed using the First come First serve algorithm. In this paper, we have provided an optimize algorithm to queue of the scheduler using various scheduling methods like Shortest Job First, First in First out, Round robin. The job scheduling system is responsible to select best suitable machines in a grid for user jobs. The management and scheduling system generates job schedules for each machine in the grid by taking static restrictions and dynamic parameters of jobs and machines
into consideration. The main purpose of this paper is to develop an efficient job scheduling algorithm to maximize the resource utilization and minimize processing time of the jobs. Queues can be optimized by using various scheduling algorithms depending upon the performance criteria to be improved e.g. response
time, throughput. The work has been done in MATLAB using the parallel computing toolbox.
GROUPING BASED JOB SCHEDULING ALGORITHM USING PRIORITY QUEUE AND HYBRID ALGOR...ijgca
Grid computing enlarge with computing platform which is collection of heterogeneous computing resources connected by a network across dynamic and geographically dispersed organization to form a distributed high performance computing infrastructure. Grid computing solves the complex computing problems amongst multiple machines. Grid computing solves the large scale computational demands in a high performance computing environment. The main emphasis in the grid computing is given to the resource management and the job scheduler .The goal of the job scheduler is to maximize the resource utilization and minimize the processing time of the jobs. Existing approaches of Grid scheduling doesn’t give much emphasis on the performance of a Grid scheduler in processing time parameter. Schedulers allocate resources to the jobs to be executed using the First come First serve algorithm. In this paper, we have provided an optimize algorithm to queue of the scheduler using various scheduling methods like Shortest Job First, First in First out, Round robin. The job scheduling system is responsible to select best suitable machines in a grid for user jobs. The management and scheduling system generates job schedules for each machine in the grid by taking static restrictions and dynamic parameters of jobs and machines into consideration. The main purpose of this paper is to develop an efficient job scheduling algorithm to maximize the resource utilization and minimize processing time of the jobs. Queues can be optimized by using various scheduling algorithms depending upon the performance criteria to be improved e.g. response time, throughput. The work has been done in MATLAB using the parallel computing toolbox.
EFFICIENT SCHEDULING STRATEGY USING COMMUNICATION AWARE SCHEDULING FOR PARALL...ijdpsjournal
In the area of Computer Science, Parallel job scheduling is an important field of research. Finding a best
suitable processor on the high performance or cluster computing for user submitted jobs plays an
important role in measuring system performance. A new scheduling technique called communication aware
scheduling is devised and is capable of handling serial jobs, parallel jobs, mixed jobs and dynamic jobs.
This work focuses the comparison of communication aware scheduling with the available parallel job
scheduling techniques and the experimental results show that communication aware scheduling performs
better when compared to the available parallel job scheduling techniques.
A hybrid approach for scheduling applications in cloud computing environment IJECEIAES
Cloud computing plays an important role in our daily life. It has direct and positive impact on share and update data, knowledge, storage and scientific resources between various regions. Cloud computing performance heavily based on job scheduling algorithms that are utilized for queue waiting in modern scientific applications. The researchers are considered cloud computing a popular platform for new enforcements. These scheduling algorithms help in design efficient queue lists in cloud as well as they play vital role in reducing waiting for processing time in cloud computing. A novel job scheduling is proposed in this paper to enhance performance of cloud computing and reduce delay time in queue waiting for jobs. The proposed algorithm tries to avoid some significant challenges that throttle from developing applications of cloud computing. However, a smart scheduling technique is proposed in our paper to improve performance processing in cloud applications. Our experimental result of the proposed job scheduling algorithm shows that the proposed schemes possess outstanding enhancing rates with a reduction in waiting time for jobs in queue list.
NETWORK-AWARE DATA PREFETCHING OPTIMIZATION OF COMPUTATIONS IN A HETEROGENEOU...IJCNCJournal
Rapid development of diverse computer architectures and hardware accelerators caused that designing parallel systems faces new problems resulting from their heterogeneity. Our implementation of a parallel
system called KernelHive allows to efficiently run applications in a heterogeneous environment consisting
of multiple collections of nodes with different types of computing devices. The execution engine of the
system is open for optimizer implementations, focusing on various criteria. In this paper, we propose a new
optimizer for KernelHive, that utilizes distributed databases and performs data prefetching to optimize the
execution time of applications, which process large input data. Employing a versatile data management
scheme, which allows combining various distributed data providers, we propose using NoSQL databases
for our purposes. We support our solution with results of experiments with real executions of our OpenCL
implementation of a regular expression matching application in various hardware configurations.
Additionally, we propose a network-aware scheduling scheme for selecting hardware for the proposed
optimizer and present simulations that demonstrate its advantages.
Comparative Analysis of Various Grid Based Scheduling Algorithmsiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Recently, lot of interest have been put forth by researchers to improve workload scheduling in cloud platform. However, execution of scientific workflow on cloud platform is time consuming and expensive. As users are charged based on hour of usage, lot of research work have been emphasized in minimizing processing time for reduction of cost. However, the processing cost can be reduced by minimizing energy consumption especially when resources are heterogeneous in nature; very limited work have been done considering optimizing cost with energy and processing time parameters together in meeting task quality of service (QoS) requirement. This paper presents cost and performance aware workload scheduling (CPA-WS) technique under heterogeneous cloud platform. This paper presents a cost optimization model through minimization of processing time and energy dissipation for execution of task. Experiments are conducted using two widely used workflow such as Inspiral and CyberShake. The outcome shows the CPA-WS significantly reduces energy, time, and cost in comparison with standard workload scheduling model.
DYNAMIC TASK SCHEDULING BASED ON BURST TIME REQUIREMENT FOR CLOUD ENVIRONMENTIJCNCJournal
Cloud computing has an indispensable role in the modern digital scenario. The fundamental challenge of cloud systems is to accommodate user requirements which keep on varying. This dynamic cloud environment demands the necessity of complex algorithms to resolve the trouble of task allotment. The overall performance of cloud systems is rooted in the efficiency of task scheduling algorithms. The dynamic property of cloud systems makes it challenging to find an optimal solution satisfying all the evaluation metrics. The new approach is formulated on the Round Robin and the Shortest Job First algorithms. The Round Robin method reduces starvation, and the Shortest Job First decreases the average waiting time. In this work, the advantages of both algorithms are incorporated to improve the makespan of user tasks.
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
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SURVEY ON SCHEDULING AND ALLOCATION IN HIGH LEVEL SYNTHESIScscpconf
This paper presents the detailed survey of scheduling and allocation techniques in the High Level Synthesis (HLS) presented in the research literature. It also presents the methodologies and techniques to improve the Speed, (silicon) Area and Power in High Level Synthesis, which are presented in the research literature.
Many computational solutions can be expressed as Di
rected Acyclic Graph (DAG), in which
nodes represent tasks to be executed and edges repr
esent precedence constraints among tasks.
A Cluster of processors is a shared resource among
several users and hence the need for a
scheduler which deals with multi-user jobs presente
d as DAGs. The scheduler must find the
number of processors to be allotted for each DAG an
d schedule tasks on allotted processors. In
this work, a new method to find optimal and maximum
number of processors that can be allotted
for a DAG is proposed. Regression analysis is used
to find the best possible way to share
available processors, among suitable number of subm
itted DAGs. An instance of a scheduler
for each DAG, schedules tasks on the allotted proce
ssors. Towards this end, a new framework
to receive online submission of DAGs, allot process
ors to each DAG and schedule tasks, is
proposed and experimented using a simulator. This s
pace-sharing of processors among multiple
DAGs shows better performance than the other method
s found in literature. Because of space-
sharing, an online scheduler can be used for each D
AG within the allotted processors. The use
of online scheduler overcomes the drawbacks of stat
ic scheduling which relies on inaccurate
estimated computation and communication costs. Thus
the proposed framework is a promising
solution to perform online scheduling of tasks usin
g static information of DAG, a kind of hybrid
scheduling
.
MULTIPLE DAG APPLICATIONS SCHEDULING ON A CLUSTER OF PROCESSORScscpconf
Many computational solutions can be expressed as Directed Acyclic Graph (DAG), in which
nodes represent tasks to be executed and edges represent precedence constraints among tasks.
A Cluster of processors is a shared resource among several users and hence the need for a
scheduler which deals with multi-user jobs presented as DAGs. The scheduler must find the
number of processors to be allotted for each DAG and schedule tasks on allotted processors. In
this work, a new method to find optimal and maximum number of processors that can be allotted
for a DAG is proposed. Regression analysis is used to find the best possible way to share
available processors, among suitable number of submitted DAGs. An instance of a scheduler
for each DAG, schedules tasks on the allotted processors. Towards this end, a new framework
to receive online submission of DAGs, allot processors to each DAG and schedule tasks, is
proposed and experimented using a simulator. This space-sharing of processors among multiple
DAGs shows better performance than the other methods found in literature. Because of spacesharing,
an online scheduler can be used for each DAG within the allotted processors. The use
of online scheduler overcomes the drawbacks of static scheduling which relies on inaccurate
estimated computation and communication costs. Thus the proposed framework is a promising
solution to perform online scheduling of tasks using static information of DAG, a kind of hybrid
scheduling.
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTINGcscpconf
Parallel computing systems compose task partitioning strategies in a true multiprocessing
manner. Such systems share the algorithm and processing unit as computing resources which
leads to highly inter process communications capabilities. The main part of the proposed
algorithm is resource management unit which performs task partitioning and co-scheduling .In
this paper, we present a technique for integrated task partitioning and co-scheduling on the
privately owned network. We focus on real-time and non preemptive systems. A large variety of
experiments have been conducted on the proposed algorithm using synthetic and real tasks.
Goal of computation model is to provide a realistic representation of the costs of programming
The results show the benefit of the task partitioning. The main characteristics of our method are
optimal scheduling and strong link between partitioning, scheduling and communication. Some
important models for task partitioning are also discussed in the paper. We target the algorithm
for task partitioning which improve the inter process communication between the tasks and use
the recourses of the system in the efficient manner. The proposed algorithm contributes the
inter-process communication cost minimization amongst the executing processes.
Cost-Efficient Task Scheduling with Ant Colony Algorithm for Executing Large ...Editor IJCATR
The aim of cloud computing is to share a large number of resources and pieces of equipment to compute and store knowledge and information for great scientific sources. Therefore, the scheduling algorithm is regarded as one of the most important challenges and problems in the cloud. To solve the task scheduling problem in this study, the ant colony optimization (ACO) algorithm was adapted from social theories with a fair and accurate resource allocation approach based on machine performance and capacity. This study was intended to decrease the runtime and executive costs. It was also meant to optimize the use of machines and reduce their idle time. Finally, the proposed method was compared with Berger and greedy algorithms. The simulation results indicate that the proposed algorithm reduced the makespan and executive cost when tasks were added. It also increased fairness and load balancing. Moreover, it made the optimal use of machines possible and increased user satisfaction. According to evaluations, the proposed algorithm improved the makespan by 80%.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Cloud computing is an emerging technology. It process huge amount of data so scheduling mechanism
works as a vital role in the cloud computing. Thus my protocol is designed to minimize the switching time,
improve the resource utilization and also improve the server performance and throughput. This method or
protocol is based on scheduling the jobs in the cloud and to solve the drawbacks in the existing protocols.
Here we assign the priority to the job which gives better performance to the computer and try my best to
minimize the waiting time and switching time. Best effort has been made to manage the scheduling of jobs
for solving drawbacks of existing protocols and also improvise the efficiency and throughput of the server.
GROUPING BASED JOB SCHEDULING ALGORITHM USING PRIORITY QUEUE AND HYBRID ALGOR...ijgca
Grid computing enlarge with computing platform which is collection of heterogeneous computing resources connected by a network across dynamic and geographically dispersed organization to form a distributed high performance computing infrastructure. Grid computing solves the complex computing
problems amongst multiple machines. Grid computing solves the large scale computational demands in a high performance computing environment. The main emphasis in the grid computing is given to the resource management and the job scheduler .The goal of the job scheduler is to maximize the resource utilization and minimize the processing time of the jobs. Existing approaches of Grid scheduling doesn’t give much emphasis on the performance of a Grid scheduler in processing time parameter. Schedulers allocate resources to the jobs to be executed using the First come First serve algorithm. In this paper, we have provided an optimize algorithm to queue of the scheduler using various scheduling methods like Shortest Job First, First in First out, Round robin. The job scheduling system is responsible to select best suitable machines in a grid for user jobs. The management and scheduling system generates job schedules for each machine in the grid by taking static restrictions and dynamic parameters of jobs and machines
into consideration. The main purpose of this paper is to develop an efficient job scheduling algorithm to maximize the resource utilization and minimize processing time of the jobs. Queues can be optimized by using various scheduling algorithms depending upon the performance criteria to be improved e.g. response
time, throughput. The work has been done in MATLAB using the parallel computing toolbox.
GROUPING BASED JOB SCHEDULING ALGORITHM USING PRIORITY QUEUE AND HYBRID ALGOR...ijgca
Grid computing enlarge with computing platform which is collection of heterogeneous computing resources connected by a network across dynamic and geographically dispersed organization to form a distributed high performance computing infrastructure. Grid computing solves the complex computing problems amongst multiple machines. Grid computing solves the large scale computational demands in a high performance computing environment. The main emphasis in the grid computing is given to the resource management and the job scheduler .The goal of the job scheduler is to maximize the resource utilization and minimize the processing time of the jobs. Existing approaches of Grid scheduling doesn’t give much emphasis on the performance of a Grid scheduler in processing time parameter. Schedulers allocate resources to the jobs to be executed using the First come First serve algorithm. In this paper, we have provided an optimize algorithm to queue of the scheduler using various scheduling methods like Shortest Job First, First in First out, Round robin. The job scheduling system is responsible to select best suitable machines in a grid for user jobs. The management and scheduling system generates job schedules for each machine in the grid by taking static restrictions and dynamic parameters of jobs and machines into consideration. The main purpose of this paper is to develop an efficient job scheduling algorithm to maximize the resource utilization and minimize processing time of the jobs. Queues can be optimized by using various scheduling algorithms depending upon the performance criteria to be improved e.g. response time, throughput. The work has been done in MATLAB using the parallel computing toolbox.
EFFICIENT SCHEDULING STRATEGY USING COMMUNICATION AWARE SCHEDULING FOR PARALL...ijdpsjournal
In the area of Computer Science, Parallel job scheduling is an important field of research. Finding a best
suitable processor on the high performance or cluster computing for user submitted jobs plays an
important role in measuring system performance. A new scheduling technique called communication aware
scheduling is devised and is capable of handling serial jobs, parallel jobs, mixed jobs and dynamic jobs.
This work focuses the comparison of communication aware scheduling with the available parallel job
scheduling techniques and the experimental results show that communication aware scheduling performs
better when compared to the available parallel job scheduling techniques.
A hybrid approach for scheduling applications in cloud computing environment IJECEIAES
Cloud computing plays an important role in our daily life. It has direct and positive impact on share and update data, knowledge, storage and scientific resources between various regions. Cloud computing performance heavily based on job scheduling algorithms that are utilized for queue waiting in modern scientific applications. The researchers are considered cloud computing a popular platform for new enforcements. These scheduling algorithms help in design efficient queue lists in cloud as well as they play vital role in reducing waiting for processing time in cloud computing. A novel job scheduling is proposed in this paper to enhance performance of cloud computing and reduce delay time in queue waiting for jobs. The proposed algorithm tries to avoid some significant challenges that throttle from developing applications of cloud computing. However, a smart scheduling technique is proposed in our paper to improve performance processing in cloud applications. Our experimental result of the proposed job scheduling algorithm shows that the proposed schemes possess outstanding enhancing rates with a reduction in waiting time for jobs in queue list.
NETWORK-AWARE DATA PREFETCHING OPTIMIZATION OF COMPUTATIONS IN A HETEROGENEOU...IJCNCJournal
Rapid development of diverse computer architectures and hardware accelerators caused that designing parallel systems faces new problems resulting from their heterogeneity. Our implementation of a parallel
system called KernelHive allows to efficiently run applications in a heterogeneous environment consisting
of multiple collections of nodes with different types of computing devices. The execution engine of the
system is open for optimizer implementations, focusing on various criteria. In this paper, we propose a new
optimizer for KernelHive, that utilizes distributed databases and performs data prefetching to optimize the
execution time of applications, which process large input data. Employing a versatile data management
scheme, which allows combining various distributed data providers, we propose using NoSQL databases
for our purposes. We support our solution with results of experiments with real executions of our OpenCL
implementation of a regular expression matching application in various hardware configurations.
Additionally, we propose a network-aware scheduling scheme for selecting hardware for the proposed
optimizer and present simulations that demonstrate its advantages.
Comparative Analysis of Various Grid Based Scheduling Algorithmsiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Recently, lot of interest have been put forth by researchers to improve workload scheduling in cloud platform. However, execution of scientific workflow on cloud platform is time consuming and expensive. As users are charged based on hour of usage, lot of research work have been emphasized in minimizing processing time for reduction of cost. However, the processing cost can be reduced by minimizing energy consumption especially when resources are heterogeneous in nature; very limited work have been done considering optimizing cost with energy and processing time parameters together in meeting task quality of service (QoS) requirement. This paper presents cost and performance aware workload scheduling (CPA-WS) technique under heterogeneous cloud platform. This paper presents a cost optimization model through minimization of processing time and energy dissipation for execution of task. Experiments are conducted using two widely used workflow such as Inspiral and CyberShake. The outcome shows the CPA-WS significantly reduces energy, time, and cost in comparison with standard workload scheduling model.
DYNAMIC TASK SCHEDULING BASED ON BURST TIME REQUIREMENT FOR CLOUD ENVIRONMENTIJCNCJournal
Cloud computing has an indispensable role in the modern digital scenario. The fundamental challenge of cloud systems is to accommodate user requirements which keep on varying. This dynamic cloud environment demands the necessity of complex algorithms to resolve the trouble of task allotment. The overall performance of cloud systems is rooted in the efficiency of task scheduling algorithms. The dynamic property of cloud systems makes it challenging to find an optimal solution satisfying all the evaluation metrics. The new approach is formulated on the Round Robin and the Shortest Job First algorithms. The Round Robin method reduces starvation, and the Shortest Job First decreases the average waiting time. In this work, the advantages of both algorithms are incorporated to improve the makespan of user tasks.
Similar to A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COMPUTING SYSTEM (20)
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
PIP-MPU: FORMAL VERIFICATION OF AN MPUBASED SEPARATION KERNEL FOR CONSTRAINED...ijesajournal
Pip-MPU is a minimalist separation kernel for constrained devices (scarce memory and power resources).
In this work, we demonstrate high-assurance of Pip-MPU’s isolation property through formal verification.
Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit
(MPU). Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained
environment and targets equivalent security properties. The proofs verify that the memory blocks loaded in
the MPU adhere to the global partition tree model. We provide the basis of the MPU formalisation and the
demonstration of the formal verification strategy on two representative kernel services. The publicly
released proofs have been implemented and checked using the Coq Proof Assistant for three kernel
services, representing around 10000 lines of proof. To our knowledge, this is the first formal verification of
an MPU based separation kernel. The verification process helped discover a critical isolation-related bug.
International Journal of Embedded Systems and Applications (IJESA)ijesajournal
International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.
Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Embedded Systems & applications.
Pip-MPU: Formal Verification of an MPU-Based Separationkernel for Constrained...ijesajournal
Pip-MPU is a minimalist separation kernel for constrained devices (scarce memory and power resources). In this work, we demonstrate high-assurance of Pip-MPU’s isolation property through formal verification. Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit (MPU). Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained environment and targets equivalent security properties. The proofs verify that the memory blocks loaded in the MPU adhere to the global partition tree model. We provide the basis of the MPU formalisation and the demonstration of the formal verification strategy on two representative kernel services. The publicly released proofs have been implemented and checked using the Coq Proof Assistant for three kernel services, representing around 10000 lines of proof. To our knowledge, this is the first formal verification of an MPU based separation kernel. The verification process helped discover a critical isolation-related bug.
International Journal of Embedded Systems and Applications (IJESA)ijesajournal
International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.
Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Embedded Systems & applications.
Call for papers -15th International Conference on Wireless & Mobile Network (...ijesajournal
15th International Conference on Wireless & Mobile Network (WiMo 2023) is dedicated to addressing the challenges in the areas of wireless & mobile networks. The Conference looks for significant contributions to the Wireless and Mobile computing in theoretical and practical aspects. The Wireless and Mobile computing domain emerges from the integration among personal computing, networks, communication technologies, cellular technology, and the Internet Technology. The modern applications are emerging in the area of mobile ad hoc networks and sensor networks. This Conference is intended to cover contributions in both the design and analysis in the context of mobile, wireless, ad-hoc, and sensor networks. The goal of this Conference is to bring together researchers and practitioners from academia and industry to focus on advanced wireless and Mobile computing concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to.
Call for Papers -International Conference on NLP & Signal (NLPSIG 2023)ijesajournal
Scope & Topics
International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP).
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to:
Topics of interest include, but are not limited to, the following
Chunking/Shallow Parsing
Dialogue and Interactive Systems
Deep learning and NLP
Discourseand Pragmatics
Information Extraction, Retrieval, Text Mining
Interpretability and Analysis of Models for NLP
Language Grounding to Vision, Robotics and Beyond
Lexical Semantics
Linguistic Resources
Machine Learning for NLP
Machine Translation
NLP and Signal Processing
NLP Applications
Ontology
Paraphrasing/Entailment/Generation
Parsing/Grammatical Formalisms
Phonology, Morphology
POS tagging
Question Answering
Resources and Evaluation
Semantic Processing
Sentiment Analysis, Stylistic Analysis, and Argument Mining
Speech and Multimodality
Speech Recognition and Synthesis
Spoken Language Processing
Statistical and Knowledge based methods
Summarization
Theory and Formalism in NLP
Signal Processing & NLP
Computer Vision, Image Processing& NLP
NLP, AI & Signal
Paper Submission
Authors are invited to submit papers through the conference Submission System by May 06, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by International Journal on Cybernetics & Informatics (IJCI) (Confirmed).
Selected papers from NLPSIG 2023, after further revisions, will be published in the special issue of the following journals.
International Journal on Natural Language Computing (IJNLC)
International Journal of Ubiquitous Computing (IJU)
International Journal of Data Mining & Knowledge Management Process (IJDKP)
Signal & Image Processing : An International Journal (SIPIJ)
International Journal of Ambient Systems and Applications (IJASA)
International Journal of Grid Computing & Applications (IJGCA)
Important Dates
Submission Deadline : May 06, 2023
Authors Notification : May 25, 2023
Final Manuscript Due : June 08, 2023
International Conference on NLP & Signal (NLPSIG 2023)ijesajournal
International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP).
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to:
11th International Conference on Software Engineering & Trends (SE 2023)ijesajournal
11th International Conference on Software Engineering & Trends (SE 2023)
May 27 ~ 28, 2023, Vancouver, Canada
https://acsit2023.org/se/index
Scope & Topics
11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following.
Topics of interest include, but are not limited to, the following
The Software Process
Software Engineering Practice
Web Engineering
Quality Management
Managing Software Projects
Advanced Topics in Software Engineering
Multimedia and Visual Software Engineering
Software Maintenance and Testing
Languages and Formal Methods
Web-based Education Systems and Learning Applications
Software Engineering Decision Making
Knowledge-based Systems and Formal Methods
Search Engines and Information Retrieval
Paper Submission
Authors are invited to submit papers through the conference Submission System by April 08, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings (H index 35) in Computer Science & Information Technology (CS & IT) series (Confirmed).
Selected papers from SE 2023, after further revisions, will be published in the special issue of the following journals.
The International Journal of Software Engineering & Applications (IJSEA) -ERA indexed
International Journal of Computer Science, Engineering and Applications (IJCSEA)
Important Dates
Submission Deadline : April 08, 2023
Authors Notification : April 29, 2023
Final Manuscript Due : May 06, 2023
11th International Conference on Software Engineering & Trends (SE 2023)ijesajournal
11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following.
PERFORMING AN EXPERIMENTAL PLATFORM TO OPTIMIZE DATA MULTIPLEXINGijesajournal
This article is based on preliminary work on the OSI model management layers to optimized industrial
wired data transfer on low data rate wireless technology. Our previous contribution deal with the
development of a demonstrator providing CAN bus transfer frames (1Mbps) on a low rate wireless channel
provided by Zigbee technology. In order to be compatible with all the other industrial protocols, we
describe in this paper our contribution to design an innovative Wireless Device (WD) and a software tool,
which will aim to determine the best architecture (hardware/software) and wireless technology to be used
taking in account of the wired protocol requirements. To validate the proper functioning of this WD, we
will develop an experimental platform to test different strategies provided by our software tool. We can
consequently prove which is the best configuration (hardware/software) compared to the others by the
inclusion (inputs) of the required parameters of the wired protocol (load, binary rate, acknowledge
timeout) and the analysis of the WD architecture characteristics proposed (outputs) as the delay introduced
by system, buffer size needed, CPU speed, power consumption, meeting the input requirement. It will be
important to know whether gain comes from a hardware strategy with hardware accelerator e.g or a
software strategy with a more perf
GENERIC SOPC PLATFORM FOR VIDEO INTERACTIVE SYSTEM WITH MPMC CONTROLLERijesajournal
Today, a significant number of embedded systems focus on multimedia applications with almost insatiable demand for low-cost, high performance, and low power hardware cosumption. In this paper, we present a re-configurable and generic hardware platform for image and video processing. The proposed platform uses the benefits offered by the Field Programmable Gate Array (FPGA) to attain this goal. In this context,
a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processors, embedded memory, DDR, interface technologies, Digital Clock Managers (DCM) and MPMC.
The MPMC is an essential component for design performance tuning and real time video processing. We demonstrate the importance role of this interface in multi video applications. In fact, to successful the
deployment of DRAM it is mandatory to use a flexible and scalable interface. Our system introduces diverse modules, such as cut video detection, video zoom-in and out. This provides the utility of using this architecture as a universal video processing platform according to different application requirements. This platform facilitates the development of video and image processing applications.
This paper presents an inverting buck-boost DCDC converter design. A negative supply voltage is needed
in a variety of applications, but only a few DCDC converters are available on the market. OLED, a new
display type especially suited for small digital camera or mobile phone displays. Design challenges that
came up when negative voltages have to be handled on chip will be discussed, such as
continuous/discontinuous mode transition problems, negative voltage feedback and negative over-voltage
protection. Both devices operate in a fixed frequency PWM mode or alternatively in PFM mode. The single
inductor topology is called inverting buck-boost converter or simply inverter. The proposed converter has
been implemented with a TSMC 0.13-um 2P4M CMOS process, and the chip area is 325 x 300 um2.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
Payment industry is largely aligned in their desire to create embedded payment systems ready for the
modern digital age. The trend to embed payments into a software platform is often regarded as first step
towards a broader trend of embedded finance based on digital representation of fiat currencies. Since it
became clear to our research team that there are no technologies and protocols that are protected against
attacks of quantum computing, and that enable automatic embedded payments, online or offline with no
fear of counterfeit, P2P or device-to-device to be made in real time without intermediaries, in any
denomination, even continuous payments per time or service, while preserving the privacy of all parties,
without enabling illicit activities, we decided to utilize the Generic Innovation Engine [1] that is based on
the Artificial Intelligence Assistance Innovation acceleration methodologies and tools in order to boost the
progress of innovation of the necessary solutions. These methodologies accelerate innovation across the
board. It proposes a framework for natural and artificial intelligence collaboration in pursuit of an
innovative (R&D) objective The outcome of deploying these Artificial Innovation Assistant (AIA)
methodologies was tens of patents that yield solutions, that a few of them are described in this paper. We
argue that a promising avenue for automated embedded payment systems to fulfil people’s desire for
privacy when conducting payments, and national security agencies demand for quantum-safe security,
could be based on DeFi and digital currencies platforms that does not suffer from flaws of DLT-based
solutions, while introducing real advantages, in all aspects, including being quantum-resilient, enabling
users to decide with whom, if at all, to share information, identity, transactions details, etc., all without
trade-offs, complying with AML measures, and accommodating the potential for high transaction volumes.
It is not legacy bank accounts, and it is not peer-dependent, nor a self-organizing network.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
2 nd International Conference on Computing and Information Technology ijesajournal
2
nd International Conference on Computing and Information Technology Trends
(CCITT 2023) will provide an excellent international forum for sharing knowledge and
results in theory, methodology and applications of Computing and Information Technology
Trends. The Conference looks for significant contributions to all major fields of the
Computer Science, Compute Engineering, Information Technology and Trends in theoretical
and practical aspects.
TIME CRITICAL MULTITASKING FOR MULTICORE MICROCONTROLLER USING XMOS® KITijesajournal
This paper presents the research work on multicore microcontrollers using parallel, and time critical
programming for the embedded systems. Due to the high complexity and limitations, it is very hard to work
on the application development phase on such architectures. The experimental results mentioned in the
paper are based on xCORE multicore microcontroller form XMOS®
. The paper also imitates multi-tasking
and parallel programming for the same platform. The tasks assigned to multiple cores are executed
simultaneously, which saves the time and energy. The relative study for multicore processor and multicore
controller concludes that micro architecture based controller having multiple cores illustrates better
performance in time critical multi-tasking environment. The research work mentioned here not only
illustrates the functionality of multicore microcontroller, but also express the novel technique of
programming, profiling and optimization on such platforms in real time environments.
4 th International Conference on Signal Processing and Machine Learning (SIGM...ijesajournal
4
th International Conference on Signal Processing and Machine Learning (SIGML
2023) will provide an excellent international forum for sharing knowledge and results in
theory, methodology and applications of on Signal Processing and Machine Learning.
The aim of the conference is to provide a platform to the researchers and practitioners
from both academia as well as industry to meet and share cutting-edge development in
the field.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Let's dive deeper into the world of ODC! Ricardo Alves (OutSystems) will join us to tell all about the new Data Fabric. After that, Sezen de Bruijn (OutSystems) will get into the details on how to best design a sturdy architecture within ODC.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
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Transcript: Selling digital books in 2024: Insights from industry leaders - T...
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COMPUTING SYSTEM
1. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
DOI : 10.5121/ijesa.2015.5102 19
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION
IN HETEROGENEOUS RECONFIGURABLE COMPUTING
SYSTEM
Mahendra Vucha1
and Arvind Rajawat2
1,2
Department of Electronics & Communication Engineering, MANIT, Bhopal, India.
1
Department of Electronics & Communication Engineering, Christ University,
Bangalore, India.
ABSTRACT
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
KEYWORDS
Heterogeneous Reconfigurable Computing Systems, FPGA, parallel processing, concurrency, Directed
Acyclic Graph.
1. INTRODUCTION
Modern embedded systems are used for highly integrated handheld devices such as mobile
phones, digital cameras, and multimedia devices. Hardware Software Co-design supports mixed
hardware and software implementation to satisfy the given timing and cost constraints. Co-
design is a flexible solution for the applications when hardware realization satisfies the timing but
not the cost constraints whereas software solution is not fast enough. So, the hardware software
co-design provides intensive solution for the modern embedded systems which are modeled with
flexible computing platform like Field Programmable Gate Arrays (FPGA). The FPGA is flexible
hardware that offers cost effective solution through reuse and also accelerate many multimedia
applications by adopting their hardware at runtime. In real time, the tasks of parallel application
must share the resources of FPGA effectively in order to enhance application execution speed and
it can be achieved through effective scheduling mechanism. The aim of this paper is to introduce
2. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
20
a disciplined approach to utilize the resources of embedded system, which are having reusable
architectures, and also that meets the requirements of variety real time applications. Diverse set of
resources like Reconfigurable Logic Units (RLUs) and soft core processors are interconnected
together, with a high speed communication network, on a single chip FPGA that describes a new
computing platform called Heterogeneous Reconfigurable Computing Systems (HRCS). The
HRCS requires an efficient application scheduling methodology to share their resources in order
to achieve high performance and also utilize the resources effectively. There are many researchers
[3] [6] [7] [9] presented techniques for mapping multiple tasks to High Speed Computing
Systems [26] with the aim of “minimizing execution time of an application” and also “efficient
utilization of resources”. In this paper, first we would describe review of the various existing task
distribution methodologies for platforms like HRCS and proposed a novel task distribution
methodology. In general, task distribution i.e. scheduling models are two types called static and
dynamic. Static Scheduling: All information needed for scheduling such as the structure of the
parallel application, execution time of individual tasks and communication cost between the tasks
must be known in advance and they are described in [10] [11] [12] [13] [14]. Dynamic
scheduling: The scheduling decisions made at runtime are demonstrated in [8] [20] [22] [24] [26]
and their aim is not only enhancing the execution time and also minimize the communication
overheads. The static and dynamic scheduling heuristic approaches, proposed by various
researches, are classified into four categories: List scheduling algorithms [20], clustering
algorithms [11], Duplication Algorithms [22], and genetic algorithms. The list scheduling
algorithms [20] provides good quality of task distribution and their performance would be
compatible with all real time categories. So, in this paper we have been motivated to develop list
scheduling algorithm and generally it has three steps: task selection, processor selection and
status update. In this paper, we have developed a list based task distribution model which is based
on the attributes of the tasks of an application and computing platform. The remaining paper is
organized as the literature review in chapter 2, problem formulation in chapter 3, task distribution
methodology in chapter 4, implementation scheme in chapter 5, and results discussion in chapter
6 and finally paper is concluded in chapter 7.
2. LITERATURE REVIEW
The task distribution problems for CPU as well as for reconfigurable hardware have been
addressed by many researchers in academic and industry. However, research in this paper is
targeted to CPU – FPGA environment. The articles discussed in this session describe various task
scheduling methodologies for heterogeneous computing systems. A computing platform called
MOLEN Polymorphic processor described in [26] which is incorporated with both general
purpose and custom computing processing elements. The MOLEN processor is designed with
arbitrary number of programmable units to support both hardware and software tasks. An
efficient multi task scheduler in [9] proposed for runtime reconfigurable systems and also it has
introduced a new parameter called Time-Improvement as cost function for compiler assisted
scheduling models. The Time-Improvement parameter described based on reduction-in-task-
execution time and distance-to-next-call of the tasks in an application. The scheduling system in
[9], targeted to MOLEN Polymorphic processor [26] and in which the scheduler assigns control
of tasks and less computing intensive tasks to General Purpose Processor (GPP) whereas
computing intensive tasks are assigned to FPGA. The task scheduler in [9] outperforms previous
existing algorithms and accelerates task execution 4% to 20%. In [6], an online scheduling is
demonstrated for CPU-FPGA platform where tasks are described into three categories such as
3. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
21
Software Tasks executes only on CPU, Hardware Tasks executes only on FPGA and Hybrid
Tasks executes on both CPU & FPGA. The scheduling model [6] is integration of task allocation,
placement and task migration modules and considers the reserved time of tasks as cost function to
schedule the tasks of an application. An On-line HW/SW partitioning and co-scheduling
algorithm [3] proposed for GPP and Reconfigurable Processing Unit (RPU) environment in
which Hardware Earliest Finish Time (HEFT) and Software Earliest Finish Time (SEFT) are
estimated for tasks of an application. The difference between HEFT and SEFT imply to partition
the tasks and EFT used to define scheduled tasks list for GPP and RPU as well. An overview of
tasks co-scheduling [7] [31] is described to µP and FPGA environment and it have been defined
from different research communities like Embedded Computing (EC), Heterogeneous Computing
(HC) and Reconfigurable Hardware (RH). The Reconfigurable Computing Co-scheduler (ReCoS)
[7] integrates the strengths of HC and RH scheduling policies in order to effectively handle the
RC system constraints such as the number of FFs, LUTs, Multiplexers, CLBs, communication
overheads, reconfiguration overheads, throughputs and power constraints. The ReCoS, as
compared with EC, RC and RH scheduling algorithms, shows improvement in optimal schedule
search time and execution time of an application. Hardware supported task scheduling is
proposed in [15] for Dynamically Reconfigurable SoC (RSoC) to utilize the resources effectively
for execution of multi task applications. The RSoC architecture comprises a general purpose
embedded processor along with two L1 data and instruction cache and number of reconfigurable
logic units on a single chip. In [15], task systems are represented as Modified Directed Acyclic
Graph (MDAG) and the MDAG defined as tuple G = (V, Ed
, Ec
, P), where V is set of nodes, Ed
and Ec
are the set of directed data edges and control edges respectively and P represents the set of
probabilities associated with Ec
. The conclusion of the paper [15] states that Dynamic Scheduling
(DS) does not degrade as the complexity of the problem increase whereas the performance of
Static Scheduling (SS) decline. Finally, the DS outperforms the SS when both task system
complexity and degree of dynamism increases. Compiler assisted runtime scheduler [16] is
designed for MOLEN architecture where the run time application is described as Configuration
Call Graph (CCG). The CCG assigns two parameters called the distance to the next call and
frequency of calls in future to the tasks in an application and these parameters acts as cost
function to schedule the tasks. Communication aware online task scheduling for partially
reconfigurable systems [17] distributes the tasks of an application to 2D area of computing
architecture and where communication time of tasks acts as cost function to schedule the tasks.
The scheduler in [17] describes the tasks expected end time as = + + +
+ , where is completion time of already scheduled task, is task
configuration time, is data/memory read time, is task execution time and is
data/memory write time and it could run on host processor. HW/SW co-design techniques [18]
are described for dynamically reconfigurable architectures with the aim of deciding execution
order of the event at run time based on their EDF. Here they have demonstrated a HW/SW
partitioning algorithm, a co-design methodology with dynamic scheduling for discrete event
systems along with a dynamic reconfigurable computing multi-context scheduling algorithm.
These three co-design techniques [18] minimize the application execution time by paralleling
events execution and it could be controlled by host processor for both shared memory and local
memory based Dynamic Reconfigurable Logic (DRL) architectures. When number of DRL cells
is equal or more than three, the techniques in [18] brings better optimization for shared memory
architecture compared to the local memory architectures. A HW/SW partitioning algorithm
presented in [30] to partition the tasks as software tasks and hardware tasks based on their waiting
time. A layer model in [20] provides systematic use of dynamically reconfigurable hardware and
4. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
22
also reduces the error-proneness of the system components. A methodology in [34] presented for
building real time reconfigurable systems and they ensure that all the constraints of the
applications are met. In [34, the Compulsory-Reuse (CR) tasks in an application are found and
they are used to calculate the Loading-Back factor that support the reuse of resources. The
various research articles addressed in this section describes task distribution of non real time
systems in order to achieve optimized performance and throughput but they may miss deadlines
in real time. In this article, we also focused on non real time systems with the objective to meet
dead line requirements at runtime.
3. TASK DISTRIBUTION PROBLEM
Generally, a task distribution methodology consists of an application, targeted architecture and
criteria to task distribution. So this chapter is intended to brief about task graph of an application,
targeted architecture, performance criteria, motivation to the research and some necessary
assumption.
3.1 Targeted architecture
Heterogeneous reconfigurable hardware is an emerging technology [1] [26] [32] [33] due to their
high performance, flexibility, area reuse and also provides faster time-to-market solutions [1] [33]
for real time applications compared to ASIC solutions. In this research, a computing platform is
modeled on a single chip FPGA which consists of a soft core processor (i.e. microprocessor is
configured on core of FPGA) and multiple Reconfigurable Logic Unit (RLU) as processing
elements shown in figure 1. The soft core processor is static core in nature and it would execute
software version of tasks in an application. The reconfigurable units RLU1, RLU2, RLU3, RLU4
and RLU5 support dynamic reconfiguration at runtime for hardware tasks of an application. The
Cache memory is dedicated for soft core processor to store the instructions and input/output data
while task execution. The shared memory stores the task executables and input/output data for
both soft core and hard core (i.e. RLU computing elements) processing elements.
Figure 1. Target heterogeneous architecture
The soft core and hard core Processing Elements (PEs) in the targeted architecture are wrapped
with communication interface so that provides interface between memory and PEs for data
interchange. The hardware reconfiguration and tasks execution is managed by a task distribution
model which would be the objective of this research and it can be demonstrated in coming
FPGA
Soft core
Processor
Cache
Memory
Shared
Memory
RLU 1 RLU 2
RLU 4 RLU 5
RLU 3
Communication Interface
5. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
23
chapters. The RLUs independently execute the tasks and communicate with each other. The
targeted platform can be implemented on Xilinx Virtex-5 and Virtex-6 or Altera FPGA devices.
The FPGA Vendors provide specific design tools to develop custom computing platforms where
as the Xilinx EDK development tool is used to develop a processor based reconfigurable system
called Heterogeneous Reconfigurable Systems.
3.2 Application as Task Graph
An application is represented by a waited Directed Acyclic Graph (DAG) G = (V, E), where V
represents set of tasks = {, , … } and E represents set of edges E = {e11, e12 …., e21
,e22, .…., eMN} between the tasks. Each edge represents precedence constraint such that
task should complete its execution before . In a DAG, task without any predecessor is an
entry task and task without successor is an exit task. Generally, the tasks execution of an
application is non – preemptive but in this research we have considered that the tasks behavior
would be either preemptive or non-preemptive. In this research, the tasks of an application, i.e.
DAG, are waited with their attributes (stated as parameters in rest of the paper) like task arrival
time, ! task deadline, task area in terms of number of bit slices required, #$ task
reconfiguration time, ℎ task execution time on FPGA and task execution time on soft core
processor, where i = 1, 2, 3 . . . . N and N is equal to number of tasks in DAG. Task arrival
time is the starting time of task execution and task deadline ! would be maximum time
allowed to complete the task. The tasks area is described as the number of logic gates required
for task execution on FPGA. The task configuration time #$ is the time taken by FPGA to adopt
their hardware to execute the task. In this paper, we have assumed that the configuration time is
fixed for all tasks, since all RLUs configuration time is fixed in FPGA. The task execution time is
the time taken by task to complete their execution either on µP called or FPGA called ℎ .
3.3 Performance Criteria
In this research, we intended to represent parallel applications as DAG and also they carry task
parameters. The one or more task parameters may acts as cost function to distribute applications
to the resources of computing architecture. Initially, the tasks of parallel applications have been
executed on soft core processor as well on hard core FPGA in order to acquire their parameters.
The acquired parameters like area (number of slices on FPGA), execution time are maintained in
the form of cost matrix'()×. The order of the execution time cost matrix is N×2, since there are
N tasks assumed in an application and each task is executed on 2 processing elements i.e. soft
core processor and FPGA. The cost matrixes of an application plays crucial role while
distributing the tasks to the targeted architecture. In practical, the execution time of an application
depends on Finish Time (FT) of the exit task and called as scheduled length of an application. In
this research, the objective of task distribution model is to minimize the scheduled length of an
application and also efficient utilization of Heterogeneous architecture resources. The FT of task
depends on nature of resources used for computation and also on tasks arrival time. The FT of the
task, FT ( ) = + , where is an execution time of a task ti on soft core processor or FPGA
i.e. ∈ '()×. The arrival time of task is depends on finish time of the task 0 i.e.
( ) = FT( 0) and so on.
3.4 Motivational Example
6. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
24
The task graph shown in figure 2 is an example taken form [20] [35] and it is targeted to a
heterogeneous reconfigurable platform having one CPU and three RLUs as computing elements.
Figure 2 Task graph and its attribute table on soft core processor and FPGA
Generally, execution time of task graph depends on the processing elements on which their tasks
are executed. In this research, the reconfiguration latency is assumed as constant and equal to
zero. The task graph, in figure 2, is executed on different configurations of targeted platform as
shown in figure 3. In the figure 3, along the x-axis represents execution time in millisecond and
the y-axis represents platform configurations used for task graph execution. An application,
shown in figure 2, is scheduled to single microprocessor and FPGA with single RLU and the
execution time in the both cases are shown in figure 3(a) and 3(b) respectively. The application
ideal schedulable length on CPU, figure 3(a), is 127 µsec. and it would be 101 µsec., when the
application is mapped to FPGA with single RLU, figure 3(b). So, schedulable length of an
application can be minimized when and only RLU acts as computing element. Since FPGA
support partial reconfiguration, we could cluster the FPGA into multiple RLUs to support parallel
task execution and it further reduces the schedulable length of an application. Application
scheduled to multiple RLUs platform where tasks found the required area and the execution time
is 65µs as shown in figure 3(c).
Task
(Node)
Area on
FPGA
Execution Time in
µsec
Soft core
processor
FPGA
T1 200 14 12
T2 180 13 10
T3 120 11 9
T4 180 13 10
T5 150 12 9
T6 170 13 11
T7 90 7 5
T8 70 5 3
T9 250 18 15
T10 300 21 17
T9
T8
T7
T10
T1
T6
T5
T4
T3
T2
7. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
25
Figure 3. Scheduled length of task graph on heterogeneous Reconfigurable Computing Systems
In real time, tasks may require hardware area which could not available on FPGA and they can be
called as critical tasks. The critical tasks may leads to infinite schedulable length (i.e. application
could not fully executed) and such critical tasks can be executed on microprocessor due to
microprocessor flexibility for software tasks. In this article, tasks which do not find the required
area on FPGA can be treated as critical tasks. For example, when we consider RLUs area on
FPGA is less than 200 then the tasks T1, T9 and T10 in task graph (Figure 2) becomes critical
tasks and the application could not execute on RLUs of FPGA. The scenario of scheduling critical
tasks to the platform where tasks do not find required area and its execution time is infinite as
shown in figure 3(d). The execution time infinite indicates that the application is partially
executed (i.e. tasks 9 and 10 are not completely executed) due to lack of resources and it can be
(a) Task schedule for Microprocessor
(b) Task schedule for
(c) Task schedule for FPGA with three partially reconfigurable RLU
(d) Task schedule with critical tasks for FPGA with three partially
(e) Task schedule with critical tasks for Heterogeneous Reconfigurable
(f) Dynamic task schedule for FPGA with three partially reconfigurable RLU
(g) Dynamic task schedule for Heterogeneous Reconfigurable Computing
Systems
T7
CPU T1 T2 T3 T4 T5 T6 T8 T9 T10
FPGA T1 T2 T3 T4 T5 T6 T7 T9 T9
T3
T6 T7
T8
T10
CPU
T1 T2
T4
T5
T9
T3
T6 T7
CPU T1
T8
T10
T2
T4
T5
T9
0 20 40 60 80 100 120
T3
T6 T7
T8
T10
CPU
T1 T2
T4
T5
T9
T3
T7
T1 T6
T8
T10
CPU
T2
T4
T5
T9
T8
T5
T2 T6
CPU T1
T4
T9
T3
T7
T10
Task execution on CPU
Task execution on FPGA
No Task execution on CPU
No Task execution on FPGA
Non schedulable tasks on FPGA
Task execution time difference
between CPU FPGA
Task execution time difference
between SS DS
8. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
26
addressed effectively by introducing a soft core processor along with FPGA, where as the
processor acts as a flexible computing element for critical tasks. The task schedule for such
HRCS platform is shown in figure 3(e) and the execution time is 74 µs which is more than 3(c)
but application is executed successfully. The dynamic task schedule of the application to the
platform with multiple RLUs only is shown in figure 3(f) and its execution time is 63µs.
Similarly, the dynamic task schedule of the application to the platform HRCS is shown in 3(g)
and its execution time is 71 µs. From the figures 3 (c), (e), (f), (g), it is clear that the dynamic
schedule enhances the application execution speed compared to static schedule. The idle time of
RLUs and processors is used for execution of task of parallel applications. In this paper, we are
intended to address dynamic scheduling techniques for real time applications.
3.5 problem statement and assumptions
An overview of different steps in scheduling of real time application to HRCS platform is
described in figure 4. An application would be represented as weighted DAG and it is passed to
task prioritization and HW/SW partitioning modules. The prioritization modules assigns priorities
to the tasks of DAG based on their attributes and then the partitioning module partition the tasks
into hardware and software tasks.
Figure 4. Flow chart of task distribution methodology
Task prioritization assigns priority to each task in such a way that meets the deadlines of an
application. The HW/SW partitioner partition the tasks based on the resources availability and
nature of task and the scheduler prepares the scheduled task list to either CPU or FPGA based on
task parameters stated in section 3.2. These three sequential steps plays major role in distribution
of tasks to HRCS i.e. the task graphs are distributed sequentially not concurrently. In this
Input DAG and its
parameters
HW/SW Partitioner
Application scheduler
Task schedule to
CPU
Task Schedule to
FPGA
Scheduled task
list for HRCS
Task Prioritization
9. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
27
research, tasks would be scheduled to CPU and FPGA concurrently i.e. task graphs are executed
concurrently based on availability of the HRCS resources. Each processing element in HRCS
intended to run only one task at a time and each task may be loaded to either CPU or FPGA. In
HRCS, data among the tasks can be exchanged by shared memory and the tasks nature is
assumed as either preemption or non preemption. Let’s assume that the set of tasks 1 =
{, , … … , } of an application are represented as weighted DAG and task arrival time would
be stochastic in nature. The tasks set T in DAG would be partitioned into three types called
software tasks (ST), hardware tasks (HT) and hybrid tasks (HST) based on their area (i.e.
resources width in terms of number of bit slices) and preemption nature, as stated below.
1. The set of tasks, which are preempted in nature and could not find required area on RC of
HRCS, can be treated as software task set (ST). 21 = { , , … … , }, ∈
ST, (1 ≤ 5 ≤ 6), having the parameters , ! and and run only on µP.
2. The set of tasks, which are non-preempted in nature and could find required area on RC of
HRCS, can be treated as hardware task set (HT). 71 = {ℎ , ℎ, … … , ℎ }, ℎ ∈
7T,(1 ≤ 5 ≤ 8), having parameters , ! , , $ and ℎ and run only run on FPGA.
3. The set of tasks, which are preempted in nature and could find required area on RC of
HRCS, can be treated as hybrid task set (HST). 721 = 9ℎ, ℎ, … … , ℎ:;, ℎ ∈
72T (1 ≤ 5 ≤ ), having parameters , ! , , $ , and ℎ and run either on µP or
FPGA.
In this research, the task parameters are estimated to the platform HRCS statically by different
techniques. Task area width is estimated with the help of synthesis tools like XILINX ISE,
Synopsys Design Compiler. Task hardware configuration parameters like $ , ℎ are estimated by
configuring them to hard core processor i.e. FPGA, whereas software execution time is
estimated by executing the task on soft core processor i.e. µP. The partitioned tasks are prioritized
based on the level of tasks and then scheduled them to either to soft core processor or hard core
processor. In this article, we made decision to direct software tasks to µP and hardware tasks to
FPGA permanently but the hybrid tasks are directed to either µP or FPGA based on resources
availability at that instant of time.
4.PROPOSED METHODOLOGY FOR TASK DISTRIBUTION TO
HETEROGENEOUS COMPUTING SYSTEMS
The execution time of real time applications always depends on targeted platform and its
computing elements. Distribution of the tasks of real time applications becomes complex when
there are multiple heterogeneous computing elements present in computing platform and it has
been addressed by many researchers for various computing platforms. In this article, we intended
to describe a task distribution methodology to the platform where CPU and FPGA would be
computing elements. Usually task distribution takes place in three steps task prioritization,
HW/SW partition and application schedule as shown in figure 4. In our research, the task
prioritization generates the priorities for the tasks based on their level in task graph. Task
partitioner partition the tasks into software tasks, hardware tasks and hybrid tasks based on the
resources required and availability. The scheduler prepares task distribution list to the hard core
processor and soft core processor based on tasks dead line. The behavior and Pseudocode for
these three steps are described in the following sub sections.
10. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
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4.1 Task prioritization
Initially task graph is represented as adjacency matrix which shows dependency of tasks in a task
graph. The adjacency matrix is used to find Level of individual tasks in the task graph. The Level
of tasks in task graph acts as cost function for task prioritization. In any task graph, source task
gets highest priority and sink task gets lowest priority in order to maintain dependency between
tasks. The Pseudocode for task prioritization is described in algorithm 1.
Algorithm 1: Pseudocode for Task prioritization
1 for each task_graph, no_tasks, no_next_task do
2 Compute adjacent Matrix
3 Compute Level of task
4 while ((Level)i 0)
5 Assign_Priority (task, Level);
6 Sort (priority_list)
7 end
8 end
Tasks may have equal priority since more than one task may exist at same level in a task graph.
The tasks T2, T3, T4, T5 and T6 in task graph, shown in figure 2, are at same level and they have
equal priority according to algorithm 1. In the task graph (figure 2), task T1 has first priority,
tasks T2, T3, T4, T5 and T6 assigned with second priority, tasks T7, T8 and T9 assigned with
third priority and finally task T10 assigned with forth priority. The prioritized tasks are sorted
according to their priority increasing order and then moved for HW/SW partition module.
4.2 Task Partition
The prioritized tasks are partitioned into software task, hardware tasks and hybrid tasks based on
resources available and preemption nature of the task. The pseudocode for task partition is
described in algorithm 2.
Algorithm 2: Pseudocode for Task Partition
1 for initial prioritized task_graph, no_tasks do
2 HT_queue = 0; HST_queue = 0; ST_Queue = 0;
3 if ( ( area (Ti ) available_RLU) preemption_nature = false) then
4 HT_queue = Ti
5 else if ( ( area (Ti ) available_RLU) preemption_nature = true) then
6 HST_queue = Ti
7 else
8 ST_Queue = Ti
9 end
10 end
11. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
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The initial prioritized tasks of task graph would be accepted by the task partition module as input.
The ST_Queue, HT_Queue and HST_Queues are used to store software tasks, hardware tasks and
hybrid tasks respectively. Initially these queues would be empty and intended to store partitioned
tasks in their priority increasing order. The tasks which are non-preempted in nature and could
find reconfigurable area on HRCS are sent to HT_Queue, tasks which are preempted in nature
and could find reconfigurable area on HRCS are sent to HST_Queue, and tasks which are
preempted in nature and could not find reconfigurable area on HRCS are sent ST_Queue. Finally,
these partitioned tasks are available in their respective queues and they could be distributed to
computing platform HRCS by tasks scheduling module.
4.3 Task Scheduling
The pseudocode in section 4.1 and 4.2 depict the behavior of prioritization and partition
methodologies. These methodologies receive task graphs as well as their attributes as input and
prepares initial schedule portioned task list. In this section, the dynamic task scheduling policy is
demonstrated as combination of prioritization and resource management. The initial scheduled
tasks in algorithm 1 2 are further prioritized based on the cost function called Minimum Laxity
First (MLF) and availability of the resources. The pseudocode of task scheduling model is
described in algorithm 3.
Algorithm 3: Pseudo code for Task scheduling
1 while (no_task graphs 0)
2 for initial scheduled and partitioned task graph, no_tasks do
3 Compute MLF of individual tasks in task graph
4 Assign_Priority (task, MLF)
5 Sort (priority_list)
6 end
7 RLU_Impementation_Queue = 0; CPU_Impementation_Queue = 0;
8 for prioritized tasks, no_tasks do
9 if ( Ti HT_Queue) then
10 Ti - RLU_Implementation Queue
11 else if ((Ti HST_Queue) (RLU_available ) then
12 Ti - RLU_Implentation Queue
13 else
14 Ti - CPU_Implementation Queue
15 end
16 end
17 while (RLU_Implementation_Queue != empty)
18 Wait for RLU
19 Assign task to available RLU
20 end
21 while (CPU_Implementation_Queue != empty)
22 Wait for CPU
23 Assign task to CPU
24 end
25 end
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30
The task scheduler accepts the partitioned tasks as input and computes a parameter called
Minimum Laxity First (MLF) for all the individual tasks which are in same level of the task
graph. The expression for MLF is =?@ = AB − DB − EB. The MLF acts as cost function to
prioritize parallel tasks and then prioritized tasks are scheduled as their priority increasing order.
The RLU_Implementation Queue and CPU_impementation Queue are used to store the task for
execution on hard core processor and soft core processor respectively. The RLU_Implementation
Queue stores the tasks which could execute on hardcore processor (RLUs) and the
CPU_Implementation queue stores the tasks which could execute on softcore processor (CPU).
Tasks in HT_Queue and also tasks in HST_Queue for which reconfigurable area available are
sent to RLU_Implementation Queue. Similarly tasks in ST_Queue and tasks in HST_Queue for
which reconfigurable area is not available are sent to CPU_Implementation Queue. Finally, tasks
in RLU_Implementation Queue and CPU_Implementation Queue are executed on hard core
processor (RLU) and soft core processor (microprocessor) respectively.
5. IMPLEMENTATION SCHEME
In this section, we describe the computing environment, real time application and methods
followed for application execution. The reconfigurable computing brings flexibility for execution
of wide range of application and also enhances the execution speed. So, in this research we have
described a heterogeneous computing environment on a single chip FPGA called Heterogeneous
Reconfigurable Computing System (HRCS). The HRCS contains a soft core processor and
multiple hard core processors i.e. Reconfigurable Logic Units (RLUs) as processing elements.
The soft core processor executes application in traditional method like fetch, decode and execute
whereas the hard core processor reconfigures its architecture according to the behavior of an
application task. The described HRCS platform is realized on Virtex 5 FPGA with a MicroBlaze
as soft core processor and partially reconfigurable RLUs as hard core processing elements. In the
realized heterogeneous reconfigurable platform, the MicroBlaze is equipped with a BRAM,
Instruction and Data Cache memories for storing program as well data while executing an
application. BRAM also acts as shared memory for RLUs to store input and output data. These
functional blocks MicroBlaze, RLUs (custom hardware for application tasks), BRAM, Cache and
general purpose I/O devices are interconnected through communication protocols like Processor
Local Bus (PLB) and First In First Out (FIFO) as shown in figure 5.
MicroBlaze
(Soft core)
Data Cache
Instruction
Cache
BRAM
(Shared
Memory)
Input
Devices
Output
Devices
RLU1
(Custom Hardware)
RLU2
(Custom Hardware)
RLU3
(Custom Hardware)
FPGA
PLB bus FIFO bus
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Figure 5. On-chip Heterogeneous Reconfigurable Computing System
We have selected set of task graphs extracted from multimedia applications and executed on hard
core and soft core processing elements which are constructed on Virtex 5 FPGA platform. The
task graph of JPEG is shown in figure 6(a) and it can be used as input to task distributing model.
Figure 6 (a) Tasks and their dependency in JPEG (b) Task and their dependency in DCT (c) Task and
their dependency in Encoder
The JPEG task graph has five levels where task T1 for RGB_to_ YCbCr at level 1, task graph has
three tasksT2, T3, T4 shown in figure 6(b) for Discrete Cosine Transform (DCT) at level 2, task
T5 for quantization at level 3, task graph has three tasks T6, T7, T8 shown in figure 6(c) for
Encoder at level 4 and task T9 for Stream_writing at level 5. In the figure 6(b), the task T6 for
matrix wrapping – 1 and T7 for matrix transpose are in the same level they could be executed
concurrently. The figure 6(c) shows encoder where pipeline is introduced while hardware
implementation of the task graph which increases the throughput of the task graph. The tasks in
encoder can be executed sequentially. The dataflow diagram of the procedure which is followed
to design HRCS and implement the real time application on HRCS is describe in figure 7.
Matrix
Transpose
Matrix
Wrapping - 1
Matrix
Wrapping -2
Image Matrix DCT Matrix
DCT Image Matrix
Encoder
RGB 2 YCbCr
DCT
Quantization
Stream writing
Zigzag
Scanning
RLE
Huffman
Encoding
Task/Task Graph
Pipeline
Source or sink
(a) (b) (c)
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Figure 7 Xilinx Tool flow to design HRCS and task graph execution on HRCS
The Embedded Development Kit (EDK) demonstrates board support package design. So, in this
research, we have been using the Xilinx EDK to realize the HRCS platform on Virtex 5 FPGA
where MicroBlaze soft core is configured in part of the reconfigurable area of FPGA and the rest
reconfigurable area is divided into multiple hard core processing elements. Standard embedded
SW development flow supports execution of the applications on soft core processor where as the
standard FPGA HW development flow supports execution of the application on hard core
processor.
6. RESULTS DISCUSSION
This section is intended to describe FPGA device utilization for configuring HRCS, evaluate the
performance of the task distribution methodology described for HRCS and finally HRCS
resources utilization while executing for real time applications.
6.1 Device Utilization for Heterogeneous Reconfigurable Computing System
The Virtex 5 FPGA (XC5VLX110T) device consists of 17,280 slices, 64 DSP slices and 5,328Kb
of RAM memory blocks to design high performance embedded systems. Each slice contains 4
LUT, 4 FF, arithmetic logic gates, multiplexers and fast look ahead carry chain. The Virtex 5
device used to configure the resources of HRCS such as soft core processor, RLUs and Memory
with the necessary communication ports. The device utilization for configuration of various
modules in HRCS summarized in table 2
.
Table 2. Virtex 5 FPGA (XC5VLX110T) Device utilization chart
Resource Module No. slices
Soft core (MicroBlaze) MicroBlaze 1599
Hard core
(Reconfigurable Logic Unit)
RLU1 500
RLU2 500
RLU3 500
Memory
DDR2_SDRAM
(256MB)
1687
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dlmb_cntlr (8KB) 7
Ilmb_cntlr (8KB) 4
Communication Interfaces
(Bus controllers)
dlmb 1
ilmb 1
Mb_plb 96
Debug Module Mdm (64KB) 97
Timing and reset circuits proc_sys_reset 30
xps_timer (64KB) 187
I/O interfaces RS232_uart (64KB) 97
DIP_Switches_8bit
(64KB)
67
LEDs_8bit (64KB) 71
Heterogeneous Reconfigurable Computing System 5,444
The table 2 depicts the number of slices used for each module in HRCS and the HRCS consumed
5,444 slices on virtex 5 FPGA. In coming sections we will demonstrate the tasks distribution to
targeted HRCS architecture and their performance.
6.2 Performance Estimation of application targeted to HRCS
Initially, the real time application JPEG is taken as input to analyze the effectiveness of the task
distribution methodology. So, the JPEG is represented as task graph and their dependencies are
shown in figure 8.
Figure 8. Task graph of JPEG
As stated in figure 7, the behavior of the tasks in JPEG is described in C++ and also in HDL in
order to execute them on soft core and hard core processing elements. The C++ code of the task is
cross compiled to the soft core processor MicroBlaze and that generates executable file. The
executables of the tasks are stored in program memory and then executed on MicroBlaze in order
to acquire attributes, i.e. ececution time, of the tasks on MicroBlaze. Similarly, HDL code of the
tasks is synthesized for the device Xilinx Virtex 5 to generate gate level netlist and that produces
configuration files required for task execution on FPGA. These configuration files are stored in
memory and configured them to FPGA and then executed in order to acquire the attributes, like
area required and execution time, of the tasks on FPGA. The acquired attributes of JPEG task
graph (shown in figure 6) is shown in table 3 where the task in a task graph in first column, level
of the tasks in second column, area required on FPGA in third column, tasks execution time on
FPGA in forth column and the execution time of tasks on soft core processors, i.e. core 2 duo and
MicroBlaze, in column 5 and 6. Finally, the column 7 represents the enhancement in
computational complexity of MicroBlaze compared to GPP i.e Core 2 duo Processor.
T5 T6 T7
T4
T3
T2
T1
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Table 3: Attributes of JPEG Task graph on HRCS
The table 3 shows execution time of the application JPEG on soft core processor and hardcore
processor. From the table, it is clear that the performance of the JPEG task graph is effective on
FPGA reconfigurable area compared to soft core processor. The computation time of the
application is more on MicroBlaze compared to Core 2 Duo processor. The computation time
(number of CPU clock cycles) of an application is equal to multiplication of clock speed of the
processor and execution time of that application on the processor. So, the custom soft core
MicroBlaze takes more computation time compared to general purpose Core 2 duo soft core
processor. The comparisons between the soft cores in terms of computation time and number of
clock cycles are shown in figure 9.
Figure 9 (a) No. of clock cycles consumed for execution of JPEG (b) Computation time of the application
JPEG on MicroBlaze and Core 2 duo processor
The figure 9 depicts that the JPEG execution is effective on Core 2 Duo compared to MicroBlaze
but the MicroBlaze provides cost effective solution in terms of power and area. Since, the core 2
duo runs at 1.2Ghz, whereas MicroBlaze runs at 125MHz, the core 2 duo dissipates more power
and also consumes more area. So, the MicroBlaze would be the soft core processor to design low
power computing platform for real time applications.
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The task distribution methodologies distribute the tasks of an application statically as well as
dynamically to the resources of computing platform. As we have stated, the both task distribution
methodologies are implemented and verified for the represented task graphs. In this research, the
dynamic task distribution methodology follows the MLF algorithm for task distribution. Initially,
hypothetical task graph shown in figure 2 is distributed statically as well dynamically to the
platform HRCS which is configured on FPGA and then the JPEG task graph is distributed for
execution. The execution time, in both static and dynamic scheduled policies, of hypothetical task
graph and JPEG task graphs on the platform HRCS is shown in figure 10.
(a) (b)
Figure 10 (a) Execution time of hypothetical task graph on HRCS (b) Execution time of JPEG task graph
on HRCS
From the figure 10, it is clear that the execution time of the task graphs is less in dynamic
scheduling policy compared to static scheduling policy. So the task distribution with dynamic
scheduling enhances the application execution and also utilizes the resources of computing
platform HRS effectively. The real time application JPEG alone is small enough to effectively
utilize the HRCS resources. So, an advanced application OFDM also considered along with JPEG
and distributed to HRCS in order to utilize the resources effectively. The task graph of OFDM
transmitter consists of 6 tasks as shown in figure 11. The tasks in OFDM transmitter are source
generator (T1), serial to parallel (S/P) converter (T2), Quadrature Amplitude Modulation (QAM)
a constellation mapper (T3) , IFFT (T4), parallel to serial (P/S) converter (T5) and cyclic prefix
insertion blocks (T6).
Figure 11. OFDM Transmitter Task graph
The task 3 is QAM and it could perform 16 QAM operations to generate 16 symbols which are
further transmitted to 16 bit IFFT. The tasks, in OFDM transmitter, are executed individual on
T1 T2 T4 T5 T6
T3i
T3i
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36
MicroBlaze as well on FPGA and captured their attributes. The attributes of OFDM transmitter
task graph are listed in table 4. Form the table 4, it is clear that the hardware realization enhances
the OFDM transmitter execution. The execution speed of OFDM transmitter on MicroBlaze
processor is slower than the general purpose processor and DSP processors. The core 2 duo and
DSP processors dissipates more power since they run at 1.2GHz and 225 MHz speed and also
bulky due to their heat sink. But, the MicroBlaze is available on the same chip FPGA where RLU
resides and hence it would be effective soft core processor for many power sensitive real time
applications.
Table 4. Attributes of OFDM Transmitter
So the tasks, in OFDM transmitter task graph, are distributed to HRCS platform statically as well
dynamically. The execution time of the OFDM transmitter on the platform HRCS is shown in
figure 12. Finally both JPEG and OFDM transmitter task graphs together distributed to the HRCS
platform and the execution time in both static scheduling and dynamic scheduling policy is shown
in figure 13.
The figure 12 shows that the execution time of OFDM transmitter and it is same in both Static
and Dynamic scheduling policies because there are no parallel tasks in the task graph of OFDM
transmitter. The figure 13 shows the execution time when both JPEG OFDM transmitter task
graphs together distributed to the HRCS platform. From the figures 10, 12 and 13, the dynamic
19. International Journal of Embedded systems and Applications(IJESA) Vol.5, No.1, March 2015
37
task distribution policy with MLF algorithm enhances the execution time compared to static task
distribution policy in [15] [20]. The application execution time difference between dynamic
scheduling policy and static scheduling policy depends on the task parallelism in the task graph
and execution time of the parallel tasks. The resource utilization of HRCS in both task
distribution scenarios would be demonstrated in coming section.
6.3 Resources utilization
The resources utilization of the platform HRCS is estimated based on the tasks allocated to
individual resources of the platform and time spent in executing the tasks. The expression used to
calculate the resources utilization is as follows. FDGHIJKD I=LBME=BHN =
∑ N ×D=
P×QR
, where n =
number of resources active in a time slot et, et = task execution time slot, N = Total number of
resources in computing platform, ET = Total execution time of an application. The resource
utilization is calculated for both JPEG and OFDM transmitter task graphs targeted to the platform
HRCS. The JPEG utilized 26.7% of HRCS resources when tasks are distributed statically
whereas it is 28.9% when they are distributed dynamically. Similarly, the OFDM utilize 25% of
the resources in both task distribution policies due to lake of parallelism in OFDM transmitter
task graph. The resource utilization is 25% in the case of both JPEG and OFDM transmitter task
graphs together distributed to the platform.
7. CONCLUSION
In this paper, we have proposed a novel dynamic task distribution methodology named as MLF
algorithm for on chip heterogeneous computing platform. An on chip Heterogeneous
Reconfigurable Computing System (HRCS) is constructed on Virtex 5 FPGA device for
application execution. The HRCS contains MicroBlaze as soft core processor and multiple RLUs
configured on FPGA as hardcore processor. The real time applications JPEG and OFDM
transmitter task graphs design parameters are obtained by executing them on the resources of
HRCS. The obtained attributes of task graphs acts as cost functions in MLF algorithm and the
task graphs are distributed statically as well as dynamically to the resources of HRCS. From the
result, it is concluded that the application execution is effective on HRCS when parallel tasks are
targeted. The MLF dynamic task distribution methodology enhanced the execution speed of the
JPEG applications by 9.6% over static task distribution. On the other side, the execution of the
task graphs takes less time on GPP and DSP processors compared to the On-chip soft core
processor MicroBlaze but GPP and DSP processors dissipates more power due to their high clock
speeds. So the MicroBlaze can acts as soft core processes in design of low power computing
platforms for real time applications.
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AUTHORS
Mahendra Vucha received his B. Tech degree in Electronics Comm. Engineering
from JNTU, Hyderabad, India in 2007 and M. Tech degree in VLSI and Embedded
System Design from MANIT, Bhopal, India in 2009. He is currently working for his
PhD degree at MANIT, Bhopal, India and also working as Asst. Professor in Christ
University, Dept. of Electronics and Communication Engineering, Bangalore (K.A),
India. His areas of interest are Hardware Software Co-Design, Analog Circuit
design, Digital System Design and Embedded System Design.
Arvind Rajawat received his B.E degree in Electronics Communication
Engineering from Govt. Engineering College, Ujjain, India in 1989, M. Tech
degree in Computer Science Engineering from SGSITS, Indore, India in 1991 and
Ph. D degree from MANIT, Bhopal, India. He is currently working as Professor in
Dept. Electronics and Communication, MANIT, Bhopal (M.P), India. His areas of
interest are Hardware Software Co-Design, Embedded System Design and Digital
VLSI Design.