This article is based on preliminary work on the OSI model management layers to optimized industrial
wired data transfer on low data rate wireless technology. Our previous contribution deal with the
development of a demonstrator providing CAN bus transfer frames (1Mbps) on a low rate wireless channel
provided by Zigbee technology. In order to be compatible with all the other industrial protocols, we
describe in this paper our contribution to design an innovative Wireless Device (WD) and a software tool,
which will aim to determine the best architecture (hardware/software) and wireless technology to be used
taking in account of the wired protocol requirements. To validate the proper functioning of this WD, we
will develop an experimental platform to test different strategies provided by our software tool. We can
consequently prove which is the best configuration (hardware/software) compared to the others by the
inclusion (inputs) of the required parameters of the wired protocol (load, binary rate, acknowledge
timeout) and the analysis of the WD architecture characteristics proposed (outputs) as the delay introduced
by system, buffer size needed, CPU speed, power consumption, meeting the input requirement. It will be
important to know whether gain comes from a hardware strategy with hardware accelerator e.g or a
software strategy with a more perf
Optimization of Latency of Temporal Key Integrity Protocol (TKIP) Using Graph...ijcseit
Temporal Key Integrity Protocol (TKIP) [1] encapsulation consists of multiple-hardware and software
block which can be implemented either software or hardware block or combination of both. This papers
aims to design the TKIP technique using graph theory and hardware software co-design for minimizing the
latency. Simulation results show the effectiveness of the presented technique over Hardware software codesign.
In this paper we design the High-level Data Link Control to permit synchronous, code
transparent data transmission. The control information is always in the same position and specific bit
patterns which used for control differ dramatically from those representing data that reduces the errors
chances. The transmission rate and data stream are controlled by the network node. This eliminates
additional synchronization and buffering of the data at the network interface. Some common
applications include terminal-to-terminal, terminal to CPU, satellite communication, packet switching
and other high-speed data links. In system, which require expensive cabling, and interconnection
hardware. So this core can be used to simplify interfacing by going serially, thereby reducing
interconnects hardware cost. The HDLC Controller MEGACELL is a high performance module for the
bit oriented, switched, non-switched packet transmission module. It supports half duplex and full duplex
communication lines, point-to-point and multipoint channels.
Optimization of Latency of Temporal Key Integrity Protocol (TKIP) Using Graph...ijcseit
Temporal Key Integrity Protocol (TKIP) [1] encapsulation consists of multiple-hardware and software
block which can be implemented either software or hardware block or combination of both. This papers
aims to design the TKIP technique using graph theory and hardware software co-design for minimizing the
latency. Simulation results show the effectiveness of the presented technique over Hardware software codesign.
In this paper we design the High-level Data Link Control to permit synchronous, code
transparent data transmission. The control information is always in the same position and specific bit
patterns which used for control differ dramatically from those representing data that reduces the errors
chances. The transmission rate and data stream are controlled by the network node. This eliminates
additional synchronization and buffering of the data at the network interface. Some common
applications include terminal-to-terminal, terminal to CPU, satellite communication, packet switching
and other high-speed data links. In system, which require expensive cabling, and interconnection
hardware. So this core can be used to simplify interfacing by going serially, thereby reducing
interconnects hardware cost. The HDLC Controller MEGACELL is a high performance module for the
bit oriented, switched, non-switched packet transmission module. It supports half duplex and full duplex
communication lines, point-to-point and multipoint channels.
As the urgency in the need for standards in differ ent computer networks was more,International Standard Organization (ISO) created a new subcommit tee for �Open System Interconnection� in 1977. The first priority of subcommittee was to de velop architecture for Open System Interconnection which could serve as a frame work f or the definition of standard protocols. In July 1979 the specifications of this architecture,established. That was passed under the name of �OSI Reference Model� to Technical committee .These recommendations were adopted at the end of 1979 as the basis for the following developm ent of standards for Open System Interconnection within ISO. This paper explains the OSI reference Model,which comprises of seven different layers & their own responsibilities .
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
The pattern and realization of zigbee wi-fi wireless pathwayeSAT Journals
Abstract
The application of WSN/ZigBee is having enormous growth and how to connect WSN/ZigBee to the present standard network
seamlessly is an issue what is worth studying. In this paper, it patters and realizes a ZigBee—Wi-Fi wireless pathway based on
STM32W108 RF chip and embedded Wi-Fi module. In ZigBee network, wireless pathway as a sink, it receives information from
sensor nodes and interacts with them. In WLAN, wireless pathway communicates with PC or network servers by means of AP. Both
the hardware scheme and software scheme of the wireless gateway are introduced. Then the performance of the wireless pathway is
tested, and the result shows that it can be used for general purposes and the performance is stable. The wireless pathway can realize
communication effectively between ZigBee network and WLAN.
Index Terms: STM32W108, ZigBee, WI-Fi, Wireless gateway
Running Head THE SEVEN LAYER MODEL OF OSIKao 1THE SEVEN LAYE.docxtodd521
Running Head: THE SEVEN LAYER MODEL OF OSIKao 1
THE SEVEN LAYER MODEL OF OSIKao 2
The Seven Layer Model of OSI
Kao Badi Prudence
CMIT 265
Professor: Ryan Thomas
Date: 06/25/2020
The Seven Layer Model of OSIComment by Prof Thomas: Paper format changes between sections. Review format
The Open System Interconnect (OSI) is a very important concept in networking when considering the creation of a a networking system for the university. “It was created by the international organization of standards 1978 and its main purpose is to help describe the architecture of a network so as make it possible for computers to send and receive data from other computers”. Although the model is conceptual, appreciating its purpose and function will help the university in understanding how the protocol suits and network architecture work on an application basis. The OSI model is usually built from bottom to top in this order; physical, data link, network, transport, session, presentation and lastly application. Every layer of the OSI model has its own special function. The following sections describe the function of each layer.
The layers of the OSI model
Physical Layer (Layer 1)
The OSI model layer identifies the networks’ physical characteristics and specifications. This is the type of media used on the network for example type of connector, cables, and pinout format cables.
Topology
The topography is defined by the physical layer. This layer shows the type of topology to be applied in the network. Additional characteristics in this layer define voltage used on a given frequency and medium at which the signals that carrying the data operates. They dictate speed and bandwidth of a given medium and the maximum distance over which a specific media type can be applied
Data link Layer (Layer 2)
The layer is a designed protocol that operates in a program involved in data movement into and out of a physical link in a network. Layer 2 of the OSI model is responsible for receiving data for layer 1. It is then sent to layer 3 and the data from layer 3 is sent to layer 1. This layer also detects and corrects errors. The word ‘frame’ is usually used to refer to the logical data grouping at this layer. It has two distinctive sub-layers:
· Access control (MAC) - MAC address is the physical/hardware address burnt into each network interface card (NIC). It accesses specific areas that are found within the interior of buildings. Provides access that is faster to the people authorized and restricts access of people not authorized.
· Link control (LLC) – “this controls the error and flows control mechanism of the data link layer [2].” It plays the role of managing the transmissions of data to ensure that there is integrity. For NLC, it has a role of providing data link layers.
· Network Layer (Layer 3).
The primary faction of layer 3 is to giving access to the ways by which information can disseminate to and from different network systems. It does not specify.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Adhoc mobile wireless network enhancement based on cisco devicesIJCNCJournal
Adhoc wireless networks become one of the most researchable areas in the studying of routing protocols depending on the Open System Interconnection (OSI Model). This paper use Cisco devices as a reference to enhance the performance of the network. This enhancement will be due to high processing, reliability, average cost, power consumption and accessibility. The aim of this research not only to get the cost down, it also to choose a time to time device to process the data as rapid as it can. Using NAT, Access List and DHCP protocols defined in Cisco (Graphical Unit Interface) GUI of the (Command Line Interface) CLI, the task can be made.
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
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As the urgency in the need for standards in differ ent computer networks was more,International Standard Organization (ISO) created a new subcommit tee for �Open System Interconnection� in 1977. The first priority of subcommittee was to de velop architecture for Open System Interconnection which could serve as a frame work f or the definition of standard protocols. In July 1979 the specifications of this architecture,established. That was passed under the name of �OSI Reference Model� to Technical committee .These recommendations were adopted at the end of 1979 as the basis for the following developm ent of standards for Open System Interconnection within ISO. This paper explains the OSI reference Model,which comprises of seven different layers & their own responsibilities .
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
The pattern and realization of zigbee wi-fi wireless pathwayeSAT Journals
Abstract
The application of WSN/ZigBee is having enormous growth and how to connect WSN/ZigBee to the present standard network
seamlessly is an issue what is worth studying. In this paper, it patters and realizes a ZigBee—Wi-Fi wireless pathway based on
STM32W108 RF chip and embedded Wi-Fi module. In ZigBee network, wireless pathway as a sink, it receives information from
sensor nodes and interacts with them. In WLAN, wireless pathway communicates with PC or network servers by means of AP. Both
the hardware scheme and software scheme of the wireless gateway are introduced. Then the performance of the wireless pathway is
tested, and the result shows that it can be used for general purposes and the performance is stable. The wireless pathway can realize
communication effectively between ZigBee network and WLAN.
Index Terms: STM32W108, ZigBee, WI-Fi, Wireless gateway
Running Head THE SEVEN LAYER MODEL OF OSIKao 1THE SEVEN LAYE.docxtodd521
Running Head: THE SEVEN LAYER MODEL OF OSIKao 1
THE SEVEN LAYER MODEL OF OSIKao 2
The Seven Layer Model of OSI
Kao Badi Prudence
CMIT 265
Professor: Ryan Thomas
Date: 06/25/2020
The Seven Layer Model of OSIComment by Prof Thomas: Paper format changes between sections. Review format
The Open System Interconnect (OSI) is a very important concept in networking when considering the creation of a a networking system for the university. “It was created by the international organization of standards 1978 and its main purpose is to help describe the architecture of a network so as make it possible for computers to send and receive data from other computers”. Although the model is conceptual, appreciating its purpose and function will help the university in understanding how the protocol suits and network architecture work on an application basis. The OSI model is usually built from bottom to top in this order; physical, data link, network, transport, session, presentation and lastly application. Every layer of the OSI model has its own special function. The following sections describe the function of each layer.
The layers of the OSI model
Physical Layer (Layer 1)
The OSI model layer identifies the networks’ physical characteristics and specifications. This is the type of media used on the network for example type of connector, cables, and pinout format cables.
Topology
The topography is defined by the physical layer. This layer shows the type of topology to be applied in the network. Additional characteristics in this layer define voltage used on a given frequency and medium at which the signals that carrying the data operates. They dictate speed and bandwidth of a given medium and the maximum distance over which a specific media type can be applied
Data link Layer (Layer 2)
The layer is a designed protocol that operates in a program involved in data movement into and out of a physical link in a network. Layer 2 of the OSI model is responsible for receiving data for layer 1. It is then sent to layer 3 and the data from layer 3 is sent to layer 1. This layer also detects and corrects errors. The word ‘frame’ is usually used to refer to the logical data grouping at this layer. It has two distinctive sub-layers:
· Access control (MAC) - MAC address is the physical/hardware address burnt into each network interface card (NIC). It accesses specific areas that are found within the interior of buildings. Provides access that is faster to the people authorized and restricts access of people not authorized.
· Link control (LLC) – “this controls the error and flows control mechanism of the data link layer [2].” It plays the role of managing the transmissions of data to ensure that there is integrity. For NLC, it has a role of providing data link layers.
· Network Layer (Layer 3).
The primary faction of layer 3 is to giving access to the ways by which information can disseminate to and from different network systems. It does not specify.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Adhoc mobile wireless network enhancement based on cisco devicesIJCNCJournal
Adhoc wireless networks become one of the most researchable areas in the studying of routing protocols depending on the Open System Interconnection (OSI Model). This paper use Cisco devices as a reference to enhance the performance of the network. This enhancement will be due to high processing, reliability, average cost, power consumption and accessibility. The aim of this research not only to get the cost down, it also to choose a time to time device to process the data as rapid as it can. Using NAT, Access List and DHCP protocols defined in Cisco (Graphical Unit Interface) GUI of the (Command Line Interface) CLI, the task can be made.
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DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
DESIGN OF AN EMBEDDED SYSTEM: BEDSIDE PATIENT MONITORijesajournal
Embedded systems in the range of from a tiny microcontroller-based sensor device to mobile smart phones
have vast variety of applications. However, in the literature there is no up to date system-level design of
embedded hardware and software, instead academic publications are mainly focused on the improvement
of specific features of embedded software/hardware and the embedded system designs for specific
applications. Moreover, commercially available embedded systems are not disclosed for the view of
researchers in the literature. Therefore, in this paper we first present how to design a state of art embedded
system including emerged hardware and software technologies. Bedside Patient monitor devices used in
intensive cares units of hospitals are also classified as embedded systems and run sophisticated software
and algorithms for better diagnosis of diseases. We reveal the architecture of our, commercially available,
bedside patient monitor to provide a design example of embedded systemsrelating to emerged technologies.
PIP-MPU: FORMAL VERIFICATION OF AN MPUBASED SEPARATION KERNEL FOR CONSTRAINED...ijesajournal
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Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit
(MPU). Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained
environment and targets equivalent security properties. The proofs verify that the memory blocks loaded in
the MPU adhere to the global partition tree model. We provide the basis of the MPU formalisation and the
demonstration of the formal verification strategy on two representative kernel services. The publicly
released proofs have been implemented and checked using the Coq Proof Assistant for three kernel
services, representing around 10000 lines of proof. To our knowledge, this is the first formal verification of
an MPU based separation kernel. The verification process helped discover a critical isolation-related bug.
International Journal of Embedded Systems and Applications (IJESA)ijesajournal
International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.
Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Embedded Systems & applications.
Pip-MPU: Formal Verification of an MPU-Based Separationkernel for Constrained...ijesajournal
Pip-MPU is a minimalist separation kernel for constrained devices (scarce memory and power resources). In this work, we demonstrate high-assurance of Pip-MPU’s isolation property through formal verification. Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit (MPU). Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained environment and targets equivalent security properties. The proofs verify that the memory blocks loaded in the MPU adhere to the global partition tree model. We provide the basis of the MPU formalisation and the demonstration of the formal verification strategy on two representative kernel services. The publicly released proofs have been implemented and checked using the Coq Proof Assistant for three kernel services, representing around 10000 lines of proof. To our knowledge, this is the first formal verification of an MPU based separation kernel. The verification process helped discover a critical isolation-related bug.
International Journal of Embedded Systems and Applications (IJESA)ijesajournal
International Journal of Embedded Systems and Applications (IJESA) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Embedded Systems and applications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on understanding Embedded Systems and establishing new collaborations in these areas.
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Scope & Topics
International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP).
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to:
Topics of interest include, but are not limited to, the following
Chunking/Shallow Parsing
Dialogue and Interactive Systems
Deep learning and NLP
Discourseand Pragmatics
Information Extraction, Retrieval, Text Mining
Interpretability and Analysis of Models for NLP
Language Grounding to Vision, Robotics and Beyond
Lexical Semantics
Linguistic Resources
Machine Learning for NLP
Machine Translation
NLP and Signal Processing
NLP Applications
Ontology
Paraphrasing/Entailment/Generation
Parsing/Grammatical Formalisms
Phonology, Morphology
POS tagging
Question Answering
Resources and Evaluation
Semantic Processing
Sentiment Analysis, Stylistic Analysis, and Argument Mining
Speech and Multimodality
Speech Recognition and Synthesis
Spoken Language Processing
Statistical and Knowledge based methods
Summarization
Theory and Formalism in NLP
Signal Processing & NLP
Computer Vision, Image Processing& NLP
NLP, AI & Signal
Paper Submission
Authors are invited to submit papers through the conference Submission System by May 06, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by International Journal on Cybernetics & Informatics (IJCI) (Confirmed).
Selected papers from NLPSIG 2023, after further revisions, will be published in the special issue of the following journals.
International Journal on Natural Language Computing (IJNLC)
International Journal of Ubiquitous Computing (IJU)
International Journal of Data Mining & Knowledge Management Process (IJDKP)
Signal & Image Processing : An International Journal (SIPIJ)
International Journal of Ambient Systems and Applications (IJASA)
International Journal of Grid Computing & Applications (IJGCA)
Important Dates
Submission Deadline : May 06, 2023
Authors Notification : May 25, 2023
Final Manuscript Due : June 08, 2023
International Conference on NLP & Signal (NLPSIG 2023)ijesajournal
International Conference on NLP & Signal (NLPSIG 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Signal and Natural Language Processing (NLP).
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to:
11th International Conference on Software Engineering & Trends (SE 2023)ijesajournal
11th International Conference on Software Engineering & Trends (SE 2023)
May 27 ~ 28, 2023, Vancouver, Canada
https://acsit2023.org/se/index
Scope & Topics
11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following.
Topics of interest include, but are not limited to, the following
The Software Process
Software Engineering Practice
Web Engineering
Quality Management
Managing Software Projects
Advanced Topics in Software Engineering
Multimedia and Visual Software Engineering
Software Maintenance and Testing
Languages and Formal Methods
Web-based Education Systems and Learning Applications
Software Engineering Decision Making
Knowledge-based Systems and Formal Methods
Search Engines and Information Retrieval
Paper Submission
Authors are invited to submit papers through the conference Submission System by April 08, 2023. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings (H index 35) in Computer Science & Information Technology (CS & IT) series (Confirmed).
Selected papers from SE 2023, after further revisions, will be published in the special issue of the following journals.
The International Journal of Software Engineering & Applications (IJSEA) -ERA indexed
International Journal of Computer Science, Engineering and Applications (IJCSEA)
Important Dates
Submission Deadline : April 08, 2023
Authors Notification : April 29, 2023
Final Manuscript Due : May 06, 2023
11th International Conference on Software Engineering & Trends (SE 2023)ijesajournal
11th International Conference on Software Engineering & Trends (SE 2023) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of Software Engineering. The goal of this conference is to bring together researchers and practitioners from academia and industry to focus on understanding Modern software engineering concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of software engineering & applications. Topics of interest include, but are not limited to, the following.
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a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processors, embedded memory, DDR, interface technologies, Digital Clock Managers (DCM) and MPMC.
The MPMC is an essential component for design performance tuning and real time video processing. We demonstrate the importance role of this interface in multi video applications. In fact, to successful the
deployment of DRAM it is mandatory to use a flexible and scalable interface. Our system introduces diverse modules, such as cut video detection, video zoom-in and out. This provides the utility of using this architecture as a universal video processing platform according to different application requirements. This platform facilitates the development of video and image processing applications.
This paper presents an inverting buck-boost DCDC converter design. A negative supply voltage is needed
in a variety of applications, but only a few DCDC converters are available on the market. OLED, a new
display type especially suited for small digital camera or mobile phone displays. Design challenges that
came up when negative voltages have to be handled on chip will be discussed, such as
continuous/discontinuous mode transition problems, negative voltage feedback and negative over-voltage
protection. Both devices operate in a fixed frequency PWM mode or alternatively in PFM mode. The single
inductor topology is called inverting buck-boost converter or simply inverter. The proposed converter has
been implemented with a TSMC 0.13-um 2P4M CMOS process, and the chip area is 325 x 300 um2.
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flexibility and parallelism. The flexibility is achieved when computing platform designed with
heterogeneous resources to support multifarious tasks of an application where as task scheduling brings
parallel processing. The efficient task scheduling is critical to obtain optimized performance in
heterogeneous computing Systems (HCS). In this paper, we brought a review of various application
scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In
this paper, we made a review of various scheduling methodologies targeted to high speed computing
systems and also prepared summary chart. The comparative study of scheduling methodologies for high
speed computing systems has been carried out based on the attributes of platform & application as well.
The attributes are execution time, nature of task, task handling capability, type of host & computing
platform. Finally a summary chart has been prepared and it demonstrates that the need of developing
scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an
emerging high speed computing platform for real time applications.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
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based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
Payment industry is largely aligned in their desire to create embedded payment systems ready for the
modern digital age. The trend to embed payments into a software platform is often regarded as first step
towards a broader trend of embedded finance based on digital representation of fiat currencies. Since it
became clear to our research team that there are no technologies and protocols that are protected against
attacks of quantum computing, and that enable automatic embedded payments, online or offline with no
fear of counterfeit, P2P or device-to-device to be made in real time without intermediaries, in any
denomination, even continuous payments per time or service, while preserving the privacy of all parties,
without enabling illicit activities, we decided to utilize the Generic Innovation Engine [1] that is based on
the Artificial Intelligence Assistance Innovation acceleration methodologies and tools in order to boost the
progress of innovation of the necessary solutions. These methodologies accelerate innovation across the
board. It proposes a framework for natural and artificial intelligence collaboration in pursuit of an
innovative (R&D) objective The outcome of deploying these Artificial Innovation Assistant (AIA)
methodologies was tens of patents that yield solutions, that a few of them are described in this paper. We
argue that a promising avenue for automated embedded payment systems to fulfil people’s desire for
privacy when conducting payments, and national security agencies demand for quantum-safe security,
could be based on DeFi and digital currencies platforms that does not suffer from flaws of DLT-based
solutions, while introducing real advantages, in all aspects, including being quantum-resilient, enabling
users to decide with whom, if at all, to share information, identity, transactions details, etc., all without
trade-offs, complying with AML measures, and accommodating the potential for high transaction volumes.
It is not legacy bank accounts, and it is not peer-dependent, nor a self-organizing network.
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processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
2 nd International Conference on Computing and Information Technology ijesajournal
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(CCITT 2023) will provide an excellent international forum for sharing knowledge and
results in theory, methodology and applications of Computing and Information Technology
Trends. The Conference looks for significant contributions to all major fields of the
Computer Science, Compute Engineering, Information Technology and Trends in theoretical
and practical aspects.
A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COM...ijesajournal
Modern embedded systems are being modeled as Heterogeneous Reconfigurable Computing Systems
(HRCS) where Reconfigurable Hardware i.e. Field Programmable Gate Array (FPGA) and soft core
processors acts as computing elements. So, an efficient task distribution methodology is essential for
obtaining high performance in modern embedded systems. In this paper, we present a novel methodology
for task distribution called Minimum Laxity First (MLF) algorithm that takes the advantage of runtime
reconfiguration of FPGA in order to effectively utilize the available resources. The MLF algorithm is a list
based dynamic scheduling algorithm that uses attributes of tasks as well computing resources as cost
function to distribute the tasks of an application to HRCS. In this paper, an on chip HRCS computing
platform is configured on Virtex 5 FPGA using Xilinx EDK. The real time applications JPEG, OFDM
transmitters are represented as task graph and then the task are distributed, statically as well dynamically,
to the platform HRCS in order to evaluate the performance of the designed task distribution model. Finally,
the performance of MLF algorithm is compared with existing static scheduling algorithms. The comparison
shows that the MLF algorithm outperforms in terms of efficient utilization of resources on chip and also
speedup an application execution.
TIME CRITICAL MULTITASKING FOR MULTICORE MICROCONTROLLER USING XMOS® KITijesajournal
This paper presents the research work on multicore microcontrollers using parallel, and time critical
programming for the embedded systems. Due to the high complexity and limitations, it is very hard to work
on the application development phase on such architectures. The experimental results mentioned in the
paper are based on xCORE multicore microcontroller form XMOS®
. The paper also imitates multi-tasking
and parallel programming for the same platform. The tasks assigned to multiple cores are executed
simultaneously, which saves the time and energy. The relative study for multicore processor and multicore
controller concludes that micro architecture based controller having multiple cores illustrates better
performance in time critical multi-tasking environment. The research work mentioned here not only
illustrates the functionality of multicore microcontroller, but also express the novel technique of
programming, profiling and optimization on such platforms in real time environments.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
A review on techniques and modelling methodologies used for checking electrom...nooriasukmaningtyas
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
PROJECT FORMAT FOR EVS AMITY UNIVERSITY GWALIOR.ppt
PERFORMING AN EXPERIMENTAL PLATFORM TO OPTIMIZE DATA MULTIPLEXING
1. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
DOI : 10.5121/ijesa.2013.3401 1
PERFORMING AN EXPERIMENTAL PLATFORM TO
OPTIMIZE DATA MULTIPLEXING
Remy Astier1
, Thierry Capitaine1
, Jerome Dubois1
, Valery Bourny1
, Aurelien
Lorthois1
and Jerome Fortin1
1
Laboratoire des Technologies Innovantes (LTI, EA3899), INSSET, Saint-Quentin
ABSTRACT
This article is based on preliminary work on the OSI model management layers to optimized industrial
wired data transfer on low data rate wireless technology. Our previous contribution deal with the
development of a demonstrator providing CAN bus transfer frames (1Mbps) on a low rate wireless channel
provided by Zigbee technology. In order to be compatible with all the other industrial protocols, we
describe in this paper our contribution to design an innovative Wireless Device (WD) and a software tool,
which will aim to determine the best architecture (hardware/software) and wireless technology to be used
taking in account of the wired protocol requirements. To validate the proper functioning of this WD, we
will develop an experimental platform to test different strategies provided by our software tool. We can
consequently prove which is the best configuration (hardware/software) compared to the others by the
inclusion (inputs) of the required parameters of the wired protocol (load, binary rate, acknowledge
timeout) and the analysis of the WD architecture characteristics proposed (outputs) as the delay introduced
by system, buffer size needed, CPU speed, power consumption, meeting the input requirement. It will be
important to know whether gain comes from a hardware strategy with hardware accelerator e.g or a
software strategy with a more performing scheduler. At the end, our experimental platform will be a tool
for characterizing different WD.
KEYWORDS
Embedded system, Multiplexing, Decision Support Tool, Test bench, Networking management systems
1. INTRODUCTION
Our problematic is about a smart data transmission through a multiplexing channel (Figure 1). We
choose to work with a wireless technology because today, wireless technologies are everywhere
and multiplexing of wire data on a wireless channel is a major issue.
Figure 1. Multiplexing system representation
2. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
2
This study is based on previous work [1] on wireless data transmission from 1*CAN Bus High
Speed and 1*serial communication RS232. But due to the number n of possible protocol
(RS232/422/485, CAN Bus, Ethernet) and their parameters (start/stop bit, data field, data rate, ID,
type of frame), it is difficult to make 1 embedded system which integrates at all issues (Figure 2)
which protocols priority? How to send data? It is necessary to consider this information.
Figure 2. Wireless Device representation
In order to process these different protocols, we have defined 2 types of information:
Service Information or SI: allow synchronization and correct transmission of information
between 2 entities (with synchronization bit, control field like CRC, ACK, and upper
layers of OSI Model).
Useful Information or MSG: are useful data like CAN Bus ID, IP, Mac address, type of
frame, field data... They must be sent with WD.
With this representation, we can work with any protocol. To illustrate this, we take Controller
Area Network (CAN Bus) case [2]. Figure 3 shows a 2.0A and 2.0B CAN Bus frame with SI
framed in blue on yellow background and MSG framed in red on grey background.
Figure 3. Highlights of SI and MSG fields
Now, with this generic representation, our WD can manage any I/O protocols as show in the
Figure 4. We must transmit a header, here call “H”, in order to identified source of data. Each
data transmit has a header.
3. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
3
Figure 4. Wireless Device representation with SI and MSG fields
This study builds on preliminary work [1] which has enabled us to identify 4 locks (Figure 5):
L1 in charge of auto-configuration, this means the automatic setting of protocols.
L2 will ensure the extraction of useful messages (going back more or less high in OSI
layers).
L3 will handle data storage decoded from different protocols (multiplexing) their
optimized coding (compression) and encapsulation within a frame that meets the
requirements of the block L4 (Figure 4, “H + Px_MSG”).
L4 is responsible for the transmission of the previous frame in a wireless link. The
wireless transmission channel must meet the following requirements:
o High-speed data rate.
o Real-time and full duplex.
o Compatible with the industrial environment.
Figure 5. Wireless Device locks
It is important to note that lock L1 is necessary for the proper functioning of our system because
we wish to develop a Plug and Play system, that is to say to be able to operate without knowing
protocols parameters. Moreover, in order to process locks L3 and L4, it is necessary to work with
OSI Model [3], [4].
In previous work, we also identified 3 wireless technologies (L4): Zigbee [5], [6], Bluetooth [5],
[7], and UWB for Ultra WideBand [5], [8], [9]. It will also be implemented in our system.
Wireless technologies forces us a bottleneck emphasizing an essential constraint that must be
considered:
WireDataRate <WirelessDataRate
allprotocols
å
4. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
4
The WDs aim being to have n protocols in input, it seems obvious that it is difficult to maintain
this critical constraint. This is why we decided to develop a tool, call Decision Support Tool or
DST, allowing to define hardware and software strategies to optimize operation of WD and thus
minimizing wireless bandwidth. It can, for example, integrate hardware mechanism like DMA
(Direct Memory Access) in order to make faster data transfer between Peripheral to Memory or
Memory to Memory (and vice versa). DST should take into consideration all of 4 locks
previously identified (Figure 5).
The purpose of this paper is to show interest and pertinence of development of an experimental
platform. This platform will enable us to set up an experimental plan to test our various strategies
developed in our WD. They will be qualified and quantified in terms of performance according to
various indicators such as workload, data rate, protocols. Platform is divided into 3 parts that will
represent 3 parts of 4 main sections of this article.
Figure 6. Experimental platform representation
In chapter 2 we will present DST with these hardware and software strategies, for our different
architecture, in such a way as to be optimized and generic. In chapter 3, we will speak about our
experimental platform whose purpose is to test performance of our WD described in chapter 4.
We conclude this paper by presentation of first experimental results (chapter 5) and a conclusion
about perspective.
2. DECISION SUPPORT TOOL
2.1. Aim
The purpose of DST is to solve locks L1, L2, L3, L4 (Figure 5) presented in previous paper [1].
The tool must be able to take into account all constraints in order to response to this problematic
of wireless transfer:
Workload: linked to protocols.
Protocols and their parameters.
Management of OSI Model layer (encapsulation/des-encapsulation).
Multiplexing: we must develop a owner protocol in order to identify transmit data by
wireless technologies because we have n protocols different in input (Figure 4, “H +
Px_MSG”).
System performance.
Delay created by system.
DST will allow us to configure our WD in order to responding to a given problem. The purpose is
to have a generic tool, that is to say capable of taking into account any type of architecture.
5. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
5
2.2. Working approach
The basic principle of our DST is to allow us to set up our WD in the most optimized way.
Therefor, It will generate a Configuration File which will describe hardware and software
strategies to be implement (Figure 7): it should take into account input protocols, as well as their
parameters, priorities levels, buffer size in order to define the best optimization. This corresponds
to the static aspect of our tool.
We also want to implement dynamic aspect, that is to say to be able to come to reconfigure our
WD on detection of one or more particular events due to an integrated electronic device. Various
scenarios can be imagined like increase buffer size, or priority level of protocol in order to adapt
the increase of his workload for example. DST will be connected to wire protocols in order to
able to make these changes.
Figure 7. DST and WD
2.3. Architectures
In order that DST can generate configuration file, it need to be set. As illustrated in Figure 8, DST
composed of several blocks:
Figure 8. DST architecture
Settings: it is an essential part of our DST. Indeed, it is necessary to properly configure
this tool to have the right settings for our system (data rate, priority, ...). The
configuration performs statically, that is to say at system initialization. 3 methods can be
used:
6. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
6
o Manual: we enter information from a GUI: this involves knowing the parameters.
o Automatic: we do not know parameters, we use the "Auto Configuration" method
(L1).
o Manual-Automatic: we use both methods.
Setting in “dynamic”: we can actually speak of a reconfiguration. The aim is to come
regenerate a small part of configuration file in order to come to dynamically reconfigure
our system on arrival of external events generated by the party “Auto Detect” of the
electronics device (increase of workload for example). The interest is to have an
automatic system, able to adapt to increase the use of a protocol, allowing more priority
to its messages, a buffer size larger, so that they are transmitted more quickly.
Electronic Device: includes 3 essential parts to the proper functioning of our DST.
o “Auto Configuration”: needed for automatic configuration in static mode.
o “Auto Detection”: used to detect an event on the protocols and thereby regenerate
a portion of the configuration file so that the system adapts.
o “Test bench”: The objective of this part is to manage the experimental aspects in
order to describe our various hardware and software optimizations.
Optimization: optimizes our system of previously identified locks (L2 and L3). Different
strategies will be implemented to optimize the scheduling (FIFO, FEFO), system
priorities taking into account all constraints identified, buffers size? A model queue will
be also used [10], [11] and meta-heuristic algorithms for optimization [12], [13].
Configuration file: (Figure 9) it is the file describing the strategy which must be
established to configure our WD. It allows defining hardware peripherals and their
parameters including wireless technology (L4). It also describes algorithms to be
implemented with the use or not of optimization brick present in DST.
Figure 9. Configuration file
2.4. In summary
DST is a tool, which allow us to configure any WD so that it can respond to a given problem:
number and type of protocol in entry, defining their parameters, scheduling system, priority level.
It will generate automatically and transparently, a file will be called configuration file that will
determine the hardware and software strategies to implement within our WD.
The advantage of such system is simple: have a generic tool, able to adapt to different
technologies (processor, transceiver, wireless module), with different combinations of protocols,
also having different combinations of parameters, which take into account the constraints of
workload, ACK, response time, encapsulation.
DST has been introduced, I will now present our experimental platform that will allow
experimental validation of our various strategies implemented.
7. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
7
3. EXPERIMENTAL PLATFORM
3.1. Aim
This platform will allow us to validate our different hardware and software strategies
implemented in our wireless device. The benefit of linking our DST in this platform is to
implement an experimental protocol that will allow us to start the same process to a different
hardware and software strategies: it allows us to describe the system in order to determine that
they are the best strategies. It will be necessary to develop a real experimental strategy and to
define relevant indicators.
3.2. Experimental Strategy
In order to know if a hardware and/or software optimization is more interesting than another, it is
necessary to define, in the first instance, indicators to observe the improvement in terms of
processing speed, delay, power consumption ... Here are a few indicators identified:
Delay: integrating a WD to an existing wired system, we will necessarily create a delay
in data transmission. So it is important to measure it in order to define what is most
relevant optimization: it corresponds to the smallest delay.
Buffer size: it is the number of messages that we can be stored. But more we store and
more we are falling behind.
Priority level: defines which protocol will take priority. It can be assumed it must
transmit faster data from a CAN bus protocol as an Ethernet or the RS232 protocol.
Capacity system processing: that is to say delimit the lower boundary and the upper
boundary. This will be in direct line with the different strategies used.
The second point to take into consideration is the experimental protocol. If you wish to know it is
the most appropriate optimization, it is necessary to apply the same experimental protocol that is
to say, the same data sets of events on different WD. You just have to compare the indicator
results in order to determine what is the best strategy to apply.
Our DST will have the objective of reconfigure our WD to resolve this increased protocols
workload. It may for example give more priority to the incoming data to be dealt with more
quickly. It may also increase the buffer size to store more data.
The last point concerns the operation of the experimental phase: the transmitted data are known
and are saved. Thus, DST will be able to compare the data transmitted and data received, so it
will determine the time of transmission, involving the delay caused by the system. For example,
comparing different types of strategies implemented in our WD, we can determine which is the
most efficient and produces the least delay.
3.3. Platform architecture
This platform will allow us to test the hardware and software strategies implemented in different
architectures within our WD. It is composed of our DST (Figure 10.1), electronic board for
transmission (Figure 10.2.a) and receiving (Figure 10.2b) data on wired and our WD (Figure
10.3).
8. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
8
Figure 10. Experimental platform representation
The generator board 2.a will allow the transfer of data communication protocols. It also includes
interfaces to dynamically manage constraints such as workload, speed to constrain more and more
the system. The receiver board 2.b allows to recover the data sent over the wire channels to sure
that the data transmitted by the board 2.a have been received. It is also used to measure various
indicators such as delay caused by the system. Both electronic board have been designated and
completely realized in our laboratory (see Figure 11). It incorporates a PIC24EP512GU810
microcontroller [14] allows us with its available peripherals (2 * CAN Bus, 4 * UART protocols:
2 * RS232 and 2 * RS485, and Ethernet via ENC424J600 component [15]). This microcontroller
integrates PPS (Peripheral Pin Select) functionality, which can easily manage mapping of these
different peripherals.
Figure 11. Simulation board
With the method implemented to the development of the platform, we have only come to connect
a Wireless Device in order to the test.
4. WIRELESS DEVICE ARCHITECTURES
4.1. Aim
To carry out this study, we consider wireless technologies with their standards, speed, resistance
to outside perturbations but also the protocols and their parameters or the different possible
hardware architectures. We chose to develop 3 Wireless Devices (WDA, WDB, WDC)
9. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
9
representative of the hardware and software strategies that we wish to put in place with the DST.
These solutions will fit perfectly on our experimental platform (Figure 12):
Figure 12. Experimental platform with our WDA/B/C
4.2. Our Strategies
We chose to work with 3 Wireless Devices (WDA, WDB, and WDC) in order to show relevance
of our hardware and software optimization approach.
4.2.1. Wireless Device A
The WDA (Figure 13) will be relatively simple architecture to implement with little constraint on
wireless throughput and allow us to work on the timing of the reception and transmission of CAN
Bus architecture.
WireDataRate>WirelessDataRate
The target used is a PIC24EP512GU810 [14], the Zigbee module is an XBee Pro [16] and a BT31
Bluetooth module [17].
Figure 13. WDA demonstrator
10. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
10
4.2.2. Wireless Device B
The purpose of the device WDB (Figure 14) is to show the limits of a microcontroller architecture
compared to the number of peripherals, memory and processing power available. An actual
optimization will be made with the DST.
Figure 14. WDB demonstrator
Furthermore, wireless constraint is more important:
WireDataRate >>WirelessDataRate
4.2.3. Wireless Device C
The last device WDC aims to show dynamic aspect of our DST using an FPGA architecture
allowing dynamic reconfiguration [18], [19]. However, we decided to use InES UWB kit [20] as
wireless solution (not present in the two first devices) to have no constraint on our bandwidth.
WireDataRate <<WirelessDataRate
allprotocols
å
But in the future, we could have :
WireDataRate >>WirelessDataRate
allprotocols
å
because we could have n input protocols.
The aim of WDC is to show the relevance of our dynamic approach between DST and a
configurable and dynamically reprogrammable architecture [18]. To simplify the hardware
implementation, we chose to work with the Industrial Network KIT (INK) [21] in Terasic that
integrates wired protocols and hardware architecture (FPGA Cyclone IV [22]) which we need.
Below is a representation of our dynamic architecture:
11. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
11
Figure 15. WDC dynamic architecture
As illustrated in Figure 15, the green areas correspond to the static phase, that is to say, the
system boots: they come to configure according to these inputs / outputs wired and wireless.
Orange area integrated within the processing unit corresponds to features that can be changed
dynamically: buffer size, priority level, algorithm compression / decompression ... The objective
of this architecture is to have a system capable to deal with different events, with different
mechanisms, allowing it to adapt and overcome them.
4.3. Strategies comparison
This table provides a quick comparison between our different Wireless Device A/B/C:
Table 1. Wireless Device comparison
5. EXPERIMENTAL RESULTS
5.1. Delay Calculation
The delay is the time "lost" due to the integration of WD. This study was conducted with the
WDA (see Section 4.2.1). Through our platform we were able to determine the delay time caused
by the system.
12. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
12
Figure 16. Delay calculation
Here the principle of calculation with:
Tref = wire transmission time.
Twd = TA + (TWDA1 + TW + TWDA2) + TB
Our DST measures the time reference: Tref, and the total transmission time via the wireless
device: Twd, (see Figure 16). Tref allows us to know "normal" time of data transmission. We can
calculate the delay:
Tdelay =Twd -Tref
5.2. Results
This experiment was carried out with Zigbee and Bluetooth technology and CAN Bus 2.0B to
1Mbps with DLC = 2. The experimental protocol used is relatively simple: to illustrate this delay
and relevance of material optimization, we wanted to test two strategies: with and without DMA.
We make a simple test: 10 CAN Bus frames per second during 8 minutes. The aim here is to see
delay transmission and not workload of system.
5.2.1. Bluetooth
In order to compare Zigbee and Bluetooth technologies, we are working with 2 data rate for
Bluetooth technology:
115 kbps.
921 kbps.
Figure 17 shows delay introduce by Bluetooth technology, for both data rate with and without
DMA. We can see average of delay for both graphics. We note that delay introduce by Bluetooth
is very variable.
13. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
13
Figure 17. Bluetooth delay
5.2.2. Zigbee
Figure 18 shows delay introduce by Zigbee technology. We can see that average of Zigbee is
smaller than Bluetooth.
Figure 18. Zigbee delay
5.2.3. Comparison
Aim of this graphic (Figure 19) is to show delay variation introduce by Bluetooth technology
whereas delay introduce by Zigbee is constant. We don’t show DMA or no DMA strategy on this
figure because we focus on delay difference between Zigbee, Bluetooth and wire.
Due to many layer on Bluetooth technology, Figure 19 sees a fluctuation (red and blue plots) in
contrary of Zigbee technology (green plot) where all values are concentrated. We also see purple
plot, corresponding to wire connection: it corresponds to Tref (see section 5.1), that is to say data
transmission without Wireless Device.
14. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
14
Figure 19. Delay comparison depending on connection types
Colours of both Figure (19 and 20) correspond to the same data. Figure 20 is a column diagram
representation of delay average. It is a pertinent figure because we can see difference of delay
transmission between types of transmission (wire and wireless). It is obvious that wire connection
is more efficient (Figure 20, purple plot). However there is Zigbee technology can be a good
wireless solution relative to Bluetooth, despite some values of Bluetooth delay (Figure 19, blue
and red plots) below Zigbee delay (Figure 19, green plot).
Figure 20. Average of delay in function of transmission types
5.3. DMA optimization
We can see the difference with and without DMA is not obvious (Figure 17 and 18). The reason
for this is simple: the management of CAN Bus is already configured with DMA as shown in
Figure 21 below taken from the datasheet of the component [14].
15. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
15
Figure 21. CAN interaction with DMA
Whether the transmission or reception, it is already working with the DMA: data are processed
faster. In this context, our optimizations for the DMA transfer MSG to the wireless channel (and
vice versa) with DMA as shown in the Figure 22.
Figure 22. DMA/Software data transfer
One can speak optimized transfer for a ten byte (header multiplexing MSG + CAN bus): the time
saved is minimal in comparison with software processing. The impact would be more important
on larger architectures in terms of protocols and data traffic. In conclusion, element generating
the largest delay is the Bluetooth component. Additional strategies will be developed to minimize
it.
5.4. DST
Our DST allows us to see delay transmission due to Wireless Device. We have 2 operating
modes:
File reading: we save data on text file. Our simulation board is connecting to computer
with RS232 technology. An example is show with Figure 20.
Real-time data: due to RS232 connection between simulation board and DST, we can see
in real-time delay transmission.
16. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
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Figure 23 is a Graphic User Interface (GUI) develops with QT. We can see that Zigbee delay
(green plot at 115kbps) is smaller that Bluetooth delay (red plot at 921 kbps, blue plot at
115kbps). This tool also allows us to see delay average in real-time.
Figure 23. DST data viewer (read file)
5.5. Prospects
Experiments are going to continue with our other WD. The relevance of the DMA will be more
significant in the WDB and WDC because the volume of data exchanged will be much higher and
that for several reasons:
More protocols (WDB et WDC) in I/O.
Higher MSG (Ethernet, WDC).
6. CONCLUSIONS
The development of this experimental platform allows us to test hardware and software strategies
defined by our DST in order to optimize our WD. We can test wire protocols like
RS232/422/485, CAN Bus and Ethernet with different parameters for different hardware
architectures and wireless technologies. More, we can see in real-time delay introduce by WD
and compare it with another data from saved files.
This first study has allowed to validate our approach but also our tools. Next step will be to test
WDB and to develop our programmable and reconfigurable architecture with RICA (WDC).
The aim of this platform is to test all possible solutions statically but also dynamically
highlighting, through our various indicators, the best solutions and optimizations.
ACKNOWLEDGEMENTS
This study has been carried out thanks to the financial support provided by the Region of
Picardie.
17. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
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REFERENCES
[1] R. Astier, T. Capitaine, V. Bourny, J. Dubois, and J. Fortin, “Technological leap of signal transfer
system: CONTACTLESS,” in IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics
Society, 2012, pp. 3238–3243.
[2] R. B. GmbH, “Can specification,” Version 2.0, Tech. Rep., 1991.
[3] H. Zimmermann, “OSI reference Model–The ISO model of architecture for open systems
interconnection,” IEEE Transactions on Communications, vol. 28, no. 4, pp. 425–432, 1980.
[4] Y. Li, W. Cui, D. Li, and R. Zhang, “Research based on OSI model,” in 2011 IEEE 3rd
International Conference on Communication Software and Networks (ICCSN), 2011, pp. 554–557.
[5] Y.W. S. Jin-Shyan Lee and C.C. Shen, “A comparative study of wireless protocols: Bluetooth, uwb,
zigbee, and wi-fi,” in The 33rd Annual Conference of the IEEE Industrial Electronics Society
(IECON), 2007.
[6] P. Baronti, P. Pillai, V. W. Chook, S. Chessa, A. Gotta, and Y. F. Hu, “Wireless sensor networks: A
survey on the state of the art and the 802.15.4 and zigbee standards,” Computer Communications,
ScienceDirect, p. 1655, 2007.
[7] P. McDermott-Wells, “What is bluetooth?” IEEE Potentials, vol. 23, no. 5, pp. 33–35, 2005.
[8] ECMA-368, “High rate ultra wideband phy and mac standard,” ECMA International, Tech. Rep., 3rd
Edition / December 2008.
[9] ECMA-369, “Mac-phy interface for ecma-368,” ECMA International, Tech. Rep., 3rd Edition /
December 2008.
[10] B. D. Choi, S. H. Choi, B. Kim, and D. K. Sung, “Analysis of priority queueing system based on
thresholds andits application to signaling system no. 7 with congestion control,” ELSEVIER,
Computer Networks 32, 2000.
[11] S.Balsamo, V.D.N.Persone, and P.Inverardi, “Areviewonqueueing network models with finite
capacity queues for software architectures performance prediction,” Perform. Eval., vol. 51, no. 2-4,
pp. 269– 288, Feb. 2003. [Online]. Available: http://dx.doi.org/10.1016/S0166- 5316(02)00099-8
[12] D. Jones, S. Mirrazavi, and M. Tamiz, “Multi-objective meta-heuristics: An overview of the current
state-of-the-art,” European Journal of Operational Research, vol. 137, no. 1, pp. 1 – 9, 2002.
[Online]. Available: http://www.sciencedirect.com/science/article/pii/S0377221701001230
[13] C. Blum and A. Roli, “Metaheuristics in combinatorial optimization: Overview and conceptual
comparison,” ACM Comput. Surv., vol. 35, no. 3, pp. 268–308, Sep. 2003. [Online]. Available:
http://doi.acm.org/10.1145/937503.937505
[14] Pic24ep512gu810. [Online]. Available:
http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en554334
[15] Enc424j600: 10/100 base-t ethernet interface controller. [Online]. Available:
http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en542414
[16] Xbee-pro 802.15.4. [Online]. Available: http://www.digi.com/fr/products/wireless/point-
multipoint/xbee-series1-module
[17] B. module. [Online]. Available: http://ampedrftech.com/modules.htm
[18] S. Khawam, I. Nousias, M. Milward, Y. Yi, M. Muir, and T. Arslan, “The reconfigurable instruction
cell array,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 1, pp.
75–85, 2008.
[19] T. S. Arslan, S. Khawam, J. M. Millward, I. Nousias, and Y. Yi, “Reconfigurable instruction cell
array,” The University Court Of The University Of Edinburgh, Tech. Rep., EP1877927 B1.
18. International Journal of Embedded Systems and Applications (IJESA) Vol.3, No.4, December 2013
18
[20] H. Gelke, “Wireless 480 mbit/s uwb link for embedded system,” InES-Institute of Embedded Systems,
2009.
[21] Industrial networking kit (ink). [Online]. Available: http://www.terasic.com.tw
[22] Cyclone iv fpga family. [Online]. Available: http://www.altera.com/devices/fpga/cyclone-iv/cyiv-
index.jsp
AUTHOR
Remy ASTIER received his Master Degree in Embedded System at INstitue
Supérieur des Sciences et Techniques (INSSET), at Saint-Quentin, in France, in
2009. Since, He is a PhD Student, in the LTI laboratory (EA3899). He is
working on hardware embedded architecture to be able to plug on every
systems which using wires protocols, in order to do smart wireless data transfer.