- A MOS capacitor consists of a metal gate separated from a semiconductor substrate by an insulating layer (oxide). The oxide layer acts as a dielectric, allowing the structure to function as a capacitor. - An nMOS transistor uses an n-type semiconductor substrate and contains an embedded n-channel. A pMOS transistor uses a p-type substrate and contains an embedded p-channel. - In a CMOS structure, both nMOS and pMOS transistors are used together. It uses both p-type and n-type substrates which allows for low power consumption and high noise immunity.

1. Registers

2. PR (PRESET) presets the output to 1 and
CLR (CLEAR) clears the output to 0.

3. Arrow with cross line and a number next
to it is used to represent the vector
notation. Here it shows 4 D-flip flop with
corresponding input D1, D2, D3, and D4.

4. CLK signal will be coming continuously, but it will be provided to the
clock input of the flip-flop only when LOAD = 1, because AND gate will
make the CLK signal 0 when LOAD = 0.

5. When LOAD = 0, Q1 is provided to D.
When LOAD = 1, D1 is provided to D.

7. • If the register is capable of shifting bits either towards right hand side or towards left
hand side is known as shift register. An ‘N’ bit shift register contains ‘N’ flip-flops.
Serial In – Serial Out (SISO) Shift Register
• Input is given serially and for every positive edge triggering of clock signal, the data shifts
from one stage to the next. So, we can receive the bits serially from the output of right
most D flip-flop. Hence, this output is also called as serial output.
Shift Register

8. Serial In – Parallel Out (SIPO) Shift Register
• In this shift register, we can send the bits serially from the input of left most D flip-flop.
Hence, this input is also called as serial input. For every positive edge triggering of clock
signal, the data shifts from one stage to the next. In this case, we can access the outputs
of each D flip-flop in parallel. So, we will get parallel outputs from this shift register.

9. Parallel In – Serial Out (PISO) Shift Register
• In this shift register, we can send the bits serially from the input of left most D flip-flop.
Hence, this input is also called as serial input. For every positive edge triggering of clock
signal, the data shifts from one stage to the next. In this case, we can access the outputs
of each D flip-flop in parallel. So, we will get parallel outputs from this shift register.

10. Parallel In – Serial Out (PISO) Shift Register
• In this shift register, the inputs are parallel and the output is serial. SH input is active high
and it stands for ‘SHIFT’, is active low and it stands for ‘LOAD’ (i.e. loading the input to
the flip-flop). When SH/ = 1 shifting operation will occur, A2 AND gate has one input 0
( is 0), so the B2, B3,.. Bn doesn’t matter, the OR will give output of current flipflop to
input of next flip flop (because SH = 1, so Qn will go to Dn+1).
• When SH/ = 0, loading operation will occur.
• PR (PRESET) presets the output to 1 and CLR (CLEAR) clears the output to 0.

12. *SI stand for Serial Input

14. Q1 Q2 Q3 Q4 = 0000 will remain as it is after the clock edge.

17. Counters
• A sequential circuit that goes through a prescribed sequence of states upon the
application of input pulses is called a counter.
• Counters are used for counting the number of occurrences of an event.
Counters
Synchronous
Ring
counter
Johnson
counter
Asynchronous
Ripple
Up/Down
counter

21. K =4, so it is generating 2K=8 unique patterns or counts.

24. If the T is always 1, Negative edge triggered T flipflop
toggles the output from 0 to 1, whenever there is a
negative edge of clock (i.e., 1 to 0 transition)
Q3 Q2 Q1 Q0

28. *This can be implemented either by connecting Q with CLK of
next positive edge triggered flip flop or by connecting Q’ with
CLK of next negative edge triggered flip flop.

30. 4-bit Synchronous Binary Counter

31. Memory
• Memory is a collection of binary cells together with associated circuits needed to
transfer information to or from any desired location.
• Two primary categories of memory are Random access memory (RAM) and Read only
memory (ROM)
Programmable Logic
• A programmable logic takes input data and performs a predefined logical operation to it.
• Four types of Programmable Logic devices (PLDs)
1. Read-only Memory (ROM)
2. Programmable Logic Array (PLA)
3. Programmable Array Logic (PAL)
4. Field-Programmable Gate Array (FPGA)

32. Random Access Memory (RAM)

33. Random Access Memory (RAM)

34. Types of RAM

35. SRAM vs. DRAM

36. Memory Construction
*BC stands for binary cell

37. Memory Decoding

38. Error Detection and Correction

39. Error Detection and Correction using Hamming Code

40. Error Detection and Correction using Hamming Code

41. Read Only Memory (ROM)

42. Programming the ROM

43. Types of ROM

44. Programmable Logic Devices

45. Basic Configuration of PLDs

46. Inputs
Outputs
Programmable Array Logic (PAL)

47. Inputs
Outputs
Programmable Logic Array (PLA)

48. Transistor

52. BJT Characteristics

53. Assignment
What is MOS capacitor? Explain nMOS, pMOS and CMOS with their working
principle.