2 bit comparator, 4:1 Multiplexer, 1: 4 Demultiplexer, Flip Flops and Registers

1. 2 bit comparator, 4:1 Multiplexer, 1: 4 Demultiplexer, Flip Flops
and Registers
Ms.Mary Jacob, Asst.Professor
Kristu Jayanti College (Autonomous),Bangalore

2. Magnitude Digital Comparator
ØA magnitude digital comparator is a combinational circuit
that compares two digital or binary numbers - 2 n bit
words in order to find out whether one binary number is
equal, less than or greater than the other binary number.
ØCircuit will have two inputs one for A(n bits) and other for
B (n bits) and have three output terminals, for A > B
condition, A = B condition and A < B condition.

3. Magnitude Digital Comparator- Block Diagram

4. 1-Bit Magnitude Comparator
A comparator used to compare two bits is called a single bit comparator.
It consists of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers.
The truth table for a 1-bit comparator is
Logical expressions for each output can be
expressed as :
A > B : AB'
A < B : A'B
A = B : A'B' + AB

5. 1-Bit Magnitude Comparator
Using the Logical expressions the circuit can be drawn as :
A > B : AB'
A < B : A'B
A = B : A'B' + AB

6. 2-Bit Magnitude Comparator
A comparator used to compare two binary numbers each of two bits is called a 2-bit magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to and greater than
between two binary numbers.
The truth table for a 2-bit comparator is :

7. 2-Bit Magnitude Comparator
Logical Expression from the truth table is :
A > B : A1 B1’ + A0 B1’ B0’ + A1 A0 B0’
A = B : A1’ A0’ B1’ B0’ + A1’ A0 B1’ B0 + A1 A0 B1 B0 + A1 A0’ B1 B0’
: A1’ B1’ (A0’ B0’ + A0 B0) + A1 B1 (A0 B0 + A0’ B0’)
: (A0 B0 + A0’ B0’) (A1 B1 + A1’ B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A < B : A1’ B1 + A0’ B1 B0 + A1’ A0’ B0

8. 2-Bit Magnitude Comparator

9. 2-Bit Magnitude Comparator
Applications of Comparators :
1. Comparators are used in central processing units (CPUs) and
microcontrollers (MCUs).
2. These are used in control applications in which the binary numbers
representing physical variables such as temperature, position, etc. are
compared with a reference value.
3. Comparators are also used as process controllers and for Servo motor
control.
4. Used in password verification and biometric applications

10. Multiplexer
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line. One of these data inputs will be
connected to the output based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of
zeros and ones. So, each combination will select only one data input.
Multiplexer is also called as Mux.

11. Multiplexer- 4:1
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0
and one output Y.
One of these 4 inputs will be connected to the output based on the combination
of inputs present at these two selection lines
The block diagram of 4x1 Multiplexer is Truth table of 4x1 Multiplexer is
The logical expression from the truth table is :

12. Multiplexer- 4:1 - Circuit Diagram

13. Demultiplexer
Ø A De-multiplexer is a combinational circuit that has only 1 input line
and 2N output lines.
Ø The multiplexer is a single-input and multi-output combinational circuit.
Ø The information is received from the single input line and directed to
the output line. On the basis of the values of the selection lines, the
input will be connected to one of these outputs.
Ø De-multiplexer is opposite to the multiplexer.
Ø De-multiplexer is also treated as De-mux.

14. Demultiplexer- 1:4
Ø In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2,
and Y3, 2 selection lines, i.e., S0 and S1 and single input, i.e., A.
Ø On the basis of the combination of inputs which are present at the
selection lines S0 and S1, the input be connected to one of the
outputs.
Ø The block diagram and the truth table of the 1×4 multiplexer is:

15. Demultiplexer- 1:4
Ø In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2,
and Y3, 2 selection lines, i.e., S0 and S1 and single input, i.e., A.
Ø On the basis of the combination of inputs which are present at the
selection lines S0 and S1, the input be connected to one of the
outputs.
Ø The block diagram and the truth table of the 1×4 multiplexer is:

16. Demultiplexer- 1:4
Truth Table is :
Logical Expression is:
Y0 = S1' S0' A
y1 = S1' S0 A
y2 = S1 S0' A
y3 = S1 S0 A

17. Demultiplexer- 1:4 - Circuit

18. Unit 5
I BCA E- Ms.Mary Jacob

19. Combinational Circuit Vs Sequential Circuit

20. Sequential Circuits- Types
Asynchronous sequential circuits
The clock signals are not used by the Asynchronous
sequential circuits. The asynchronous circuit is operated
through the pulses. So, the changes in the input can
change the state of the circuit.
Synchronous sequential circuits
Synchronization of the memory element's state is done by
the clock signal. The output is stored in either flip-flops or
latches. The synchronization of the outputs is done with
either only negative edges of the clock signal or only
positive edges.

21. Clock Signal
A clock signal is a periodic signal in which ON time and OFF time need not be
the same. When ON time and OFF time of the clock signal are the same, a
square wave is used to represent the clock signal.

22. Types of Triggering
Level triggering
The logic High and logic Low are the two levels in the clock signal. In level triggering,
when the clock pulse is at a particular level, only then the circuit is activated.
1. Positive level triggering
In a positive level triggering, the signal with Logic High occurs. The circuit is operated
with such type of clock signal.
2. Negative level triggering
In negative level triggering, the signal with Logic Low occurs. The circuit is operated with
such type of clock signal.

23. Edge triggering
In clock signal of edge triggering, two types of transitions occur, i.e., transition
either from Logic Low to Logic High or Logic High to Logic Low.
1.Positive Edge Triggering
If the sequential circuit is operated with the clock signal that is transitioning from
Logic Low to Logic High, then that type of triggering is known as Positive edge
triggering. It is also called as rising edge triggering.
2.Negative edge triggering
If the sequential circuit is operated with the clock signal that is transitioning from
Logic High to Logic Low, then that type of triggering is known as Negative edge
triggering. It is also called as falling edge triggering.
Types of Triggering

24. Latch & Flip Flop
There are two types of memory elements based on the type
of triggering that is suitable to operate it.
• Latches - operate with enable signal, which is level
sensitive
• Flip-flops -They are edge sensitive

25. SR Latch using Nor gate
SR Latch is also called as Set Reset Latch.
This latch affects the outputs as long as the enable, E is maintained at ‘1’.
The circuit diagram of SR Latch is
Truth table of SR latch:
S R Q Q ̅
0 0 Previous state
0 1 0 1
1 0 1 0
1 1 Not used

26. SR Latch using Nand gate
SR latch using NAND gate we will replace NOR gate with the NAND gate. The inputs
are interchanged in SR NOR latch we have reset in the upward gate and set in the
lower gate.
Truth table:SR latch using NAND gate
S R Q Q’
0 0 Not used
0 1 1 0
1 0 0 1
1 1 Previous state

27. SR Flip Flop
In SR flip flop we will use the SR latch using NAND gate and two extra NAND gate
will be used which are G3 and G4.
The input to G3 and G4 will be S and R respectively and clock signal is applied to
both gates which will be train of pulses.

28. SR Flip Flop
SR Flip Flop truth table:

29. D Flip Flop
v The D flip flop is the most important flip flop from other clocked types.
v It ensures that at the same time, both the inputs, i.e., S and R, are never equal to
1 .
v The Delay flip-flop is designed using a gated SR flip-flop with an inverter
connected between the inputs allowing for a single input D(Data).
v This single data input, which is labeled as "D" used in place of the "Set" input and
for the complementary "Reset" input, the inverter is used.
v Thus, the level-sensitive D-type or D flip flop is constructed from a level-sensitive
SR flip flop.

30. D Flip Flop
Truth Table
Circuit Diagram
Block Diagram

31. JK Flip Flop
Block Diagram
Circuit Diagram
Truth Table

32. JK Master Slave Flip flop

33. JK Master Slave Flip flop

34. T Flip flop
The T flip-flop is also called toggle flip-flop. It is a change of the JK flip-flop. The T
flip flop is received by relating both inputs of a JK flip-flop. The T flip-flop is
received by relating the inputs 'J' and 'K'

35. Shift Registers
One flip-flop can store one-bit of information. In order to store multiple bits of information,
we require multiple flip-flops. The group of flip-flops, which are used to hold store the binary
data is known as register.
If the register is capable of shifting bits either towards right hand side or towards left hand
side is known as shift register. An ‘N’ bit shift register contains ‘N’ flip-flops. Four types of
shift registers based on applying inputs and accessing of outputs.
Serial In − Serial Out shift register
Serial In − Parallel Out shift register
Parallel In − Serial Out shift register
Parallel In − Parallel Out shift register

36. Serial-in to Parallel-out Register
Serial-in to Parallel-out (SIPO) – the register is loaded with serial data, one bit at a time,
with the stored data being available at the output in parallel form
SIPO IC’s include the standard 8-bit 74LS164 or the 74LS594

37. Serial-in to Parallel-out Register
Data Movement Through A Shift Register

38. Serial-in to Serial-out Shift Register
Serial-in to Serial-out (SISO) – the data is shifted serially “IN” and “OUT” of the register,
one bit at a time in either a left or right direction under clock control.
IC’s include the 74HC595 8-bit Serial-in to Serial-out Shift Register

39. Parallel-in to Serial-out (PISO)
Parallel-in to Serial-out (PISO) – the parallel data is loaded into the register simultaneously
and is shifted out of the register serially one bit at a time under clock control.
IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

40. Parallel-in to Parallel-out (PIPO)
Parallel-in to Parallel-out (PIPO) – the parallel data is loaded simultaneously into the register,
and transferred together to their respective outputs by the same clock pulse.