ppt

1. A
Final thesis Presentation
on
Study of Low Power Radix-4 Booth Multiplier using PTL
Presented By
RISHAV KUMAR
(Reg. No: 2020VL17)
UNDER THE SUPERVISION OF
Dr. P. Karuppanan
Assistant Professor
Department of Electronics & Communication Engineering
Motilal Nehru National Institute of Technology Allahabad
Prayagraj -211004

2. Contents
 Motivation
 Problem Statement
 Introduction
Radix-4 Booth multiplier
 Existing Topology
 Proposed Design
Conclusion
 References

3. Motivation
• Multiplier is a core part of processor and
embedded system.
• In current time, mobile devices are rapidly
increasing and they do not have dedicated
cooling. This limits the performance of the
devices.
• So, the energy efficiency of the devices is as
important as the performance enhancement.

4. Abstract • Multiplication being a hardware intensive process takes a
lot of hardware and the power dissipation is high. It is one
of the biggest power consuming components in processors.
• It uses a lot of area on the chip as well because of the high
number of adders involve in getting the final product.
• If the inputs are unbalanced there are high amount of
glitches in the circuit which increase the dynamic power
dissipation in the circuit.
• A design of multipliers is required to reduce the power
dissipation and area consumed.

5. Introduction
• The partial product generator(PPG) is an important part of the
multiplier. PPG has various components whose power can be reduced.
• There are glitches in the output of multiplier which cause high
dynamic power dissipation.
• The use of PTL reduces the number of transistors and lowers the
power of the circuit.
• The glitches can be reduced by use of latch like circuit.
• Recent work in multiplier design is implemented in PTL for
comparison.
• A novel design of Radix-4 Booth multiplier is done using PTL to
improve power of the circuit.

6. Radix-4 Booth multiplication
• Booth encoding reduced the number of parital
products to half.
• There is an encoder which takes 3 bits from the
multiplicand and generates encoding signal.
• The encoded signal goes to the decoder for
generating partial product.
• For n-bit multiplication there are n/2 partial
products which means there are n/2 encoders. For
each encoder there are n+1 deocders.
• The partial products generated are added to get the
final product.
B2i+1 B2i B2i-1 Mi Partial product
0 0 0 0 0A
0 0 1 +1 +1A
0 1 0 +1 +1A
0 1 1 +2 +2A
1 0 0 -2 -2A
1 0 1 -1 -1A
1 1 0 -1 -1A
1 1 1 0 0A
Table 1: Partial Products in Radix-4 Booth multiplier

7. Existing Topology 1
• Chang et.al model implements Radix-4
Booth multiplier with an additional pre-
encoder which switches off the encoder
when the partial product is zero.
Advantage
• This circuit saves power by using pre-
encoder in the setup time and switches
off the encoder during run time.
• Reduces hardware by making encoder
less complex.
Disadvantage
• The use of pre-encoder produces glitches
as the output of pre-encoder is
asynchronous to the other inputs to the
encoder which leads to abrupt changes in
the output of encoder whenever the pre-
encoder goes from zero to non-zero state.
Figure 1: Chang et.al model implemented using PTL

8. Existing Topology 2
• Venkatachalam et.al model is an
approximate model which reduces the
complexity of the circuit by ignoring
4/32 use cases.
Advantages
• The delay and power of the circuit is
very less compared to other designs.
Disadvantage
• The output is not always consistent with
the input.
Figure 2: Venkatachalam et.al model implemented using PTL

9. Existing Topology 3
• Ranasinge et.al model gives novel design
of few components in the circuit to
reduce the glitches and power of the
circuit.
Advantages
• The glitches in the circuits are reduced,
which reduces the dynamic power
dissipation.
• This work proposes a novel design for
XOR and XNOR gates.
Disadvantage
• The circuit is very slow compared to its
counterparts.
Figure 3: Ranasinghe et.al model implemented using PTL

10. Proposed Design
• This is a novel design.
• The Proposed design has three major components,
Zero-generator, encoder and decoder.
• Proposed Multiplier design uses PTL to
implement all the components.
• The zero-generator uses a latch like circuit to
reduce the glitches generated when there is
change between zero and non-zero states.
• The circuit includes mitigations to reduce the
side-effects of PTL.
• Disadvantage
• Performance reduces when cascaded
• The output voltage is less than the input voltage.
Figure 4: Proposed zero-generator

11. Proposed Design
Figure 5: Proposed encoder circuit Figure 6: Proposed decoder circuit

12. Parameter Value
Delay 2.6 ns
Power 14.46
uW
Figure 7: Proposed zero-generator transient response

13. Parameter Value
Delay 34.57
ps
Power 7.066u
W
Figure 8: Proposed encoder transient response

14. Parameter Value
Delay 58.67
ps
Power 8.57
uW
Figure 9: Proposed decoder transient response

15. Parameter Value
Delay 231.2
ps
Power 18.63
uW
Figure 10: Proposed PPG transient response

16. Comparative Study FA
Radix-4 Booth
Multiplier
No. of
transistor
Worst Delay
(ps)
Power
(µW)
PDP
(J)
(10−1𝟓
)
Chang et.al Model 172.81ps 23. µW 636 7.989fJ
Venkatachalam et.al model 47.28ps 35.41 µW 588 1.647 fJ
Ranasinghe et.al model 181ps 32.02 µW 652 5.759 fJ
Proposed design 231.2ps 18.63 µW 616 4.307 fJ
Table 2: Comparison of proposed design with existing design

17. Conclusion
• A novel design for PPG of Radix-4 Booth multiplier is implemented using PTL. The design includes
Transmission gates and CMOS inverters to reduce the side-effects of PTL.
• Proposed design has power delay product of 4.307 fJ
• The delay of the proposed design is 231.2 ps which is higher than the designs it is compared to but the
power is 18.63 µW which is less than other designs.
• The glitches in the output are reduced.
• The output of the circuit shows lower voltage(1.51V) than the input(1.8V).

18. References
1. [Y. Chang, Y. Cheng, S. Liao and C. Hsiao, "A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism," in
IEEE Access, vol. 8, pp. 114842-114853, 2020, doi: 10.1109/ACCESS.2020.3003684.
2. A. C. Ranasinghe and S. H. Gerez, "Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers,"
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 2028-2041, Sept. 2020, doi:
10.1109/TVLSI.2020.3009239.
3. R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE J. Solid-State Circuits,
vol. 32, no. 7, pp. 1079–1090, Jul. 1997.
4. Kei-Yong Khoo, Zhan Yu and A. N. Willson, "Improved-Booth encoding for low-power multipliers," 1999 IEEE
International Symposium on Circuits and Systems (ISCAS), 1999, pp. 62-65 vol.1, doi: 10.1109/ISCAS.1999.777806.
5. S. Venkatachalam, E. Adams, H. J. Lee and S. Ko, "Design and Analysis of Area and Power Efficient Approximate Booth
Multipliers," in IEEE Transactions on Computers, vol. 68, no. 11, pp. 1697-1703, 1 Nov. 2019, doi:
10.1109/TC.2019.2926275.
6. H. Waris, C. Wang and W. Liu, "Hybrid Low Radix Encoding-Based Approximate Booth Multipliers," in IEEE Transactions
on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 3367-3371, Dec. 2020, doi: 10.1109/TCSII.2020.2975094.
7. A. D. Booth, “A signed binary multiplication technique,” Quart. J. Mech. Appl. Math., vol. 4, no. 2, pp. 236–240, 1951.
8. C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. Electron. Comput., vol. EC-13, no. 1, pp. 14–17, Feb. 1964.

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