FET Introduction

1. Field effect transistor

2. Field effect transistor introduction
FET is a unipolar Device.
Fet is a voltage controlled Device.
Current conduction is either by holes
or by electrons.
Advantages FET over BJT
1.its operation depends on the flow of
majority charge carriers only.Hence it
is a unipolar device

3. Advantages FET over BJT
2.It has high input impedance.
3.It is less affected by radiation.
4.it has better thermal stability.
It is less noisy compared with JFET.
In IC form it is easy to fabricate rather
than BJT.
Disadvantage : Relatively small gain band
width product.

4. FET

5. FET Family
Field effect transistor ts broadly
divided in to two categories.
They are
1.Junction field Effect transistor
2.Metal oxide Semiconductor field
effect transistor.
Junction field Effect transistor further

6. FET Family
Subdivided into
a. n-channel junction field effect
transistor.
b. p-channel junction field effect
transistor.
MOSFET is further subdivided in
to

7. FET Family
a.Enhancement MOSFET
b.Depletion MOSFET
Enhancement MOSFET is further
subdivided into n channel & p channel
MOSFET.
Depletion MOSFET is further
subdivided into n channel & p channel
MOSFET.

8. JFET CONSTRUCTION

9. JFET CONSTRUCTION(nchannel)
 JFET Consists of four terminals.They are
source ,Drain ,Gate & channel.
 Source : Source is the terminal through which
majority charge carriers enters in to the bar.
 It is analogous to emitter in BJT.
 Drain: Drain is the terminal through which
majority carriers leaves the channel. Drain is
more positive with respect to the channel.
 It is analogous to collector in JFET.

10. JFET CONSTRUCTION(nchannel)
 Gate : Gate is a control electrode.gate is of
opposite polarity with respect to source and
drain.Two heavily doped ‘p’ regions are
diffused in to n channel top and bottom
layers.
 These two p regions together is called as gate.
 Channel : The region of n-type material
between two gate regions is channel through
which majority carriers move from source to
drain.

11. JFET CONSTRUCTION(nchannel)
Bias Voltages
VDD : Drain Junction Must be
always forward Biased.
V gg : Gate Junction Must be
always reverse Biased.

13. JFET Operation(nchannel)
Case- I(When VDD is applied and Vgg is
Zero )
In FET electrons will from source to drain
resulting drain current ID.
Case-II(a) (When VDD is applied and Vgg
is Zero )
Here maximum drain current flowsand it
is equal to IDSS

15. JFET Operation(nchannel)
 Case-II (When VDD and Vgg are applied)
 When Gate Junction is Reverse Biased FET will act
like a two Reverse Biased Diodes Connected Back to
Back.
 And Hence two Depletion Regions will form in the
Channel.Two depletion Regions are widened.
 Constriction is more towards drain terminal rather than
source.
 This Reduces the Channel width hence drain current ID
Decreases.

16. JFET Operation(nchannel)
When gate to source voltage is further
increased a stage is reached at which both
the depletion regions will meet together.
This is called as “pinch off region”. In
this region drain current is zero .

17. JFET Operation(nchannel)
 Here Current Conduction is mainly
depends on the reverse bias gate voltage.
Hence FET is a voltage controlled
Device.
 Current flow is due to the extension with
increasing reverse bias of the field
associated with region of uncovered
charges.
 Hence the name Field effect transistor .

18. JFET symbols
 n Channel JFET  p Channel JFET

19. JFET SYMBOLS