The document describes the design and simulation of an optical cyclic redundancy check (CRC) encoder using lithium niobate waveguides. Key points:
1) A (7,4) CRC encoder is designed using lithium niobate Mach-Zehnder interferometers to perform the encoding optically for faster and more efficient error detection in optical communication.
2) The encoder structure and encoding process are explained mathematically and through simulation show the encoder can accurately detect single bit errors.
3) Beam propagation method is used to simulate the encoder design using lithium niobate waveguides and evaluate its performance in encoding test codewords and detecting errors.
This document presents research on implementing CRC and Viterbi error correction techniques on a DSP processor. CRC-32 and Viterbi decoding algorithms for convolutional codes with rate 1/2 and different generator polynomials are simulated and implemented on a TMS320C5416 DSP chip. Additionally, a concept of serially concatenated CRC-convolutional coding is proposed, using a lookup table at the decoder to potentially reduce computations compared to traditional Viterbi decoding. Simulation results demonstrating CRC-8, CRC-32, and Viterbi decoding with various generator polynomials and error scenarios are shown. The techniques are successfully implemented on the DSP hardware.
Non-binary codes approach on the performance of short-packet full-duplex tran...IJECEIAES
This paper illustrates the enhancement of the performance of short-packet full-duplex (FD) transmission by taking the approach of non-binary low density parity check (NB-LDPC) codes over higher Galois field. For the purpose of reducing the impacts of self-interference (SI), high order of modulation, complexity, and latency decoder, a blind feedback process composed of channels estimation and decoding algorithm is implemented. In particular, this method uses an iterative process to simultaneously suppress SI component of FD transmission, estimate intended channel, and decode messages. The results indicate that the proposed technique provides a better solution than both the NB-LDPC without feedback and the binary LDPC feedback algorithms. Indeed, it can significantly improve the performance of overall system in two important factors, which are bit-error-rate (BER) and mean square error (MSE), especially in high order of modulation. The suggested algorithm also shows a robustness in reliability and power consumption for both short-packet FD transmissions and high order modulation communications.
This document provides an overview of error control coding techniques, specifically cyclic codes and low-density parity-check (LDPC) codes. It begins with an introduction to the need for error correcting codes and definitions of error detection and correction. It then discusses cyclic codes in more detail, covering encoding and decoding techniques like polynomial and shift register methods. LDPC codes are also explained, including their representation via Tanner graphs and decoding algorithms. The document presents examples and applications of both code types. It concludes by discussing areas for future research and summarizing that error codes can effectively protect against random and burst errors in real-time systems.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Data detection with a progressive parallel ici canceller in mimo ofdmeSAT Publishing House
The document describes a progressive parallel interference canceller (PPIC) for use in a MIMO-OFDM system to suppress inter-carrier interference (ICI). PPIC is compared to parallel interference canceller (PIC) and shows lower complexity and better performance. PPIC architecture is simpler than PIC and more suitable for implementation in wireless communication systems requiring high data rates and mobility. Simulation results show that PPIC combined with LDPC coding achieves lower bit error rates than PIC combined with LDPC coding.
This document summarizes an implementation of a data error corrector using VLSI techniques. It describes a convolutional encoder and Viterbi decoder with a constraint length of 9 and code rate of 1/2, realized using Verilog HDL. Convolutional codes are used for forward error correction in digital data transmission by adding redundant bits. The Viterbi algorithm performs maximum likelihood decoding by using a trellis structure to calculate path metrics and select the most probable transmitted sequence. The implemented Viterbi decoder contains branch metric, path metric, and survivor memory units to decode a received bit stream encoded with a convolutional code. It was simulated and synthesized using Xilinx 13.1i tools.
The document discusses a study that implemented low density parity check (LDPC) decoding using a min sum algorithm with reduced complexity compared to existing methods. It used quadrature phase-shift keying (QPSK) modulation to improve bit error rate over previous approaches that used binary phase-shift keying (BPSK) modulation. The proposed method was able to achieve a lower bit error rate than other existing techniques using fewer iterations, improving performance flexibility by varying the code size. It implemented LDPC decoding on an irregular parity check matrix using a split row technique to reduce interconnect complexity and increase parallelism in the row processing stage compared to standard decoding algorithms.
This document presents research on implementing CRC and Viterbi error correction techniques on a DSP processor. CRC-32 and Viterbi decoding algorithms for convolutional codes with rate 1/2 and different generator polynomials are simulated and implemented on a TMS320C5416 DSP chip. Additionally, a concept of serially concatenated CRC-convolutional coding is proposed, using a lookup table at the decoder to potentially reduce computations compared to traditional Viterbi decoding. Simulation results demonstrating CRC-8, CRC-32, and Viterbi decoding with various generator polynomials and error scenarios are shown. The techniques are successfully implemented on the DSP hardware.
Non-binary codes approach on the performance of short-packet full-duplex tran...IJECEIAES
This paper illustrates the enhancement of the performance of short-packet full-duplex (FD) transmission by taking the approach of non-binary low density parity check (NB-LDPC) codes over higher Galois field. For the purpose of reducing the impacts of self-interference (SI), high order of modulation, complexity, and latency decoder, a blind feedback process composed of channels estimation and decoding algorithm is implemented. In particular, this method uses an iterative process to simultaneously suppress SI component of FD transmission, estimate intended channel, and decode messages. The results indicate that the proposed technique provides a better solution than both the NB-LDPC without feedback and the binary LDPC feedback algorithms. Indeed, it can significantly improve the performance of overall system in two important factors, which are bit-error-rate (BER) and mean square error (MSE), especially in high order of modulation. The suggested algorithm also shows a robustness in reliability and power consumption for both short-packet FD transmissions and high order modulation communications.
This document provides an overview of error control coding techniques, specifically cyclic codes and low-density parity-check (LDPC) codes. It begins with an introduction to the need for error correcting codes and definitions of error detection and correction. It then discusses cyclic codes in more detail, covering encoding and decoding techniques like polynomial and shift register methods. LDPC codes are also explained, including their representation via Tanner graphs and decoding algorithms. The document presents examples and applications of both code types. It concludes by discussing areas for future research and summarizing that error codes can effectively protect against random and burst errors in real-time systems.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Data detection with a progressive parallel ici canceller in mimo ofdmeSAT Publishing House
The document describes a progressive parallel interference canceller (PPIC) for use in a MIMO-OFDM system to suppress inter-carrier interference (ICI). PPIC is compared to parallel interference canceller (PIC) and shows lower complexity and better performance. PPIC architecture is simpler than PIC and more suitable for implementation in wireless communication systems requiring high data rates and mobility. Simulation results show that PPIC combined with LDPC coding achieves lower bit error rates than PIC combined with LDPC coding.
This document summarizes an implementation of a data error corrector using VLSI techniques. It describes a convolutional encoder and Viterbi decoder with a constraint length of 9 and code rate of 1/2, realized using Verilog HDL. Convolutional codes are used for forward error correction in digital data transmission by adding redundant bits. The Viterbi algorithm performs maximum likelihood decoding by using a trellis structure to calculate path metrics and select the most probable transmitted sequence. The implemented Viterbi decoder contains branch metric, path metric, and survivor memory units to decode a received bit stream encoded with a convolutional code. It was simulated and synthesized using Xilinx 13.1i tools.
The document discusses a study that implemented low density parity check (LDPC) decoding using a min sum algorithm with reduced complexity compared to existing methods. It used quadrature phase-shift keying (QPSK) modulation to improve bit error rate over previous approaches that used binary phase-shift keying (BPSK) modulation. The proposed method was able to achieve a lower bit error rate than other existing techniques using fewer iterations, improving performance flexibility by varying the code size. It implemented LDPC decoding on an irregular parity check matrix using a split row technique to reduce interconnect complexity and increase parallelism in the row processing stage compared to standard decoding algorithms.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
This document summarizes a research paper that proposes using parallel concatenated turbo codes in wireless sensor networks in an adaptive way. The key points are:
1) Turbo codes can achieve near-Shannon limit performance but decoding is complex, making them difficult to implement on energy-constrained sensor nodes.
2) The proposed approach shifts the complex turbo decoding to the base station while sensor nodes implement encoding and basic error correction.
3) At sensor nodes, a parallel concatenated convolutional code (PCCC) circuit encodes data and detects/corrects errors in forwarded packets. This improves energy efficiency and reliability over the wireless sensor network.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.
Implementation of Joint Network Channel Decoding Algorithm for Multiple Acces...csandit
In this paper, we consider a Joint Network Channel Decoding (JNCD) algorithm applied to a
wireless network consisting to M users. For this purpose M sources desire to send information
to one receiver by the help of an intermediate node which is the relay. The Physical Layer
Network Coding (PLNC) allows the relay to decode the combined information being sent from
different transmitters. Then, it forwards additional information to the destination node which
receives also signals from source nodes. An iterative JNCD algorithm is developed at the
receiver to estimate the information being sent from each transmitter. Simulation results show
that the Bit Error Rate (BER) can be decreased by using this concept comparing to the
reference one which doesn’t consider the network coding.
IMPLEMENTATION OF JOINT NETWORK CHANNEL DECODING ALGORITHM FOR MULTIPLE ACCES...cscpconf
In this paper, we consider a Joint Network Channel Decoding (JNCD) algorithm applied to a wireless network consisting to M users. For this purpose M sources desire to send information
to one receiver by the help of an intermediate node which is the relay. The Physical Layer Network Coding (PLNC) allows the relay to decode the combined information being sent from different transmitters. Then, it forwards additional information to the destination node which receives also signals from source nodes. An iterative JNCD algorithm is developed at the receiver to estimate the information being sent from each transmitter. Simulation results show that the Bit Error Rate (BER) can be decreased by using this concept comparing to the reference one which doesn’t consider the network coding.
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...VIT-AP University
For design methodology of CRC or cyclic redundancy check is very used technique for error checking and shows the transmission reliability we are using the HDLC block. HDLC block is very useful in data communication these block operated in data link layer. For design methodology of CRC is to generate the CRC polynomial using XOR’s gate and shift register these polynomial are implement on software Xilinx Plan Ahead 13.1 and verify for simulation result for random testing of CRC bit on receiver side same result are obtained to show that it is more reliable.
CODING SCHEMES FOR ENERGY CONSTRAINED IOT DEVICESijmnct
This paper investigates the application of advanced forward error correction techniques mainly: lowdensity parity checks (LDPC) code and polar code for IoT networks. These codes are under consideration
for 5G systems. Different code parameters such as code rate and a number of decoding iterations are used
to show their effect on the performance of the network. LDPC is performed better than polar code, over the
IoT network scenario considered in the work, for the same coding rate and the number of decoding
iterations. Considering bit error rate (BER) performance, LDPC with rate1/3 provided an improvement of
up to 2.6 dB for additive white Gaussian noise (AWGN) channel, and 2 dB for SUI-3 (frequency selective
fading channel model). LDPC code gives an improvement in throughput of about 12% as compared to
polar code with a coding rate of 2/3 over AWGN channel. The corresponding values over SUI-3 channel
are about 10%. Finally, in comparison with LDPC, polar code shows better energy saving for large
number of decoding iterations and high coding rates.
CODING SCHEMES FOR ENERGY CONSTRAINED IOT DEVICESijmnct_journal
This paper investigates the application of advanced forward error correction techniques mainly: lowdensity parity checks (LDPC) code and polar code for IoT networks. These codes are under consideration for 5G systems. Different code parameters such as code rate and a number of decoding iterations are used
to show their effect on the performance of the network. LDPC is performed better than polar code, over the IoT network scenario considered in the work, for the same coding rate and the number of decoding iterations. Considering bit error rate (BER) performance, LDPC with rate1/3 provided an improvement of
up to 2.6 dB for additive white Gaussian noise (AWGN) channel, and 2 dB for SUI-3 (frequency selective fading channel model). LDPC code gives an improvement in throughput of about 12% as compared to polar code with a coding rate of 2/3 over AWGN channel. The corresponding values over SUI-3 channel
are about 10%. Finally, in comparison with LDPC, polar code shows better energy saving for large number of decoding iterations and high coding rates.
Performances Concatenated LDPC based STBC-OFDM System and MRC Receivers IJECEIAES
This document presents a study on the performance of a low density parity check (LDPC) coded orthogonal frequency division multiplexing (OFDM) system using space time block coding (STBC) under various digital modulations and channel conditions. The system incorporates a 3/4 rate convolutional encoder and a LDPC encoder. At the receiver, maximum ratio combining is implemented for channel equalization. Simulation results show that the LDPC coded OFDM system outperforms an uncoded system, and provides lower bit error rates under binary phase shift keying modulation in an additive white Gaussian noise channel.
High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
Abstract - High speed low power viterbi decoders for trellis code modulation is well known for the delay consumption in underwater communication. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate and delay using wimax.
High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
Abstract - High speed low power viterbi decoders for trellis code modulation is well known for the delay consumption in underwater communication. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate and delay using wimax.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Implementation of an Embedded System for Software Defined RadioIJECEIAES
In this paper, developing high performance software for demanding real-time embed- ded systems is proposed. This software-based design will enable the software engineers and system architects in emerging technology areas like 5G Wireless and Software Defined Networking (SDN) to build their algorithms. An ADSP-21364 floating point SHARC Digital Signal Processor (DSP) running at 333 MHz is adopted as a platform for an embedded system. To evaluate the proposed embedded system, an implementation of frame, symbol and carrier phase synchronization is presented as an application. Its performance is investigated with an on line Quadrature Phase Shift keying (QPSK) receiver. Obtained results show that the designed software is implemented successfully based on the SHARC DSP which can utilized efficiently for such algorithms. In addition, it is proven that the proposed embedded system is pragmatic and capable of dealing with the memory constraints and critical time issue due to a long length interleaved coded data utilized for channel coding.
Space time block coding is a technique used in wireless communication to transmit multiple copies of a data stream across a number of antennas and to exploit the various received versions of the data to improve the reliability of data transfer. The fact that the transmitted signal must traverse a potentially difficult environment with scattering, reflection, refraction and so on and may then be further corrupted by thermal noise in the receiver means that some of the received copies of the data may be closer to the original signal than others. This redundancy results in a higher chance of being able to use one or more of the received copies to correctly decode the received signal. In fact, space–time coding combines all the copies of the received signal in an optimal way to extract as much information from each of them as possible.
This document summarizes an FPGA implementation of fast error correction for memories using Euclidean geometry low density parity check (EG-LDPC) codes and majority logic decoding. Key points:
- EG-LDPC codes and majority logic decoding provide simple and low-complexity error correction for memories.
- An encoder and parallel majority logic decoder for a (15,7,5) EG-LDPC code were implemented in Verilog on FPGA.
- The decoder uses a control logic that can detect if no errors are present after 3 cycles, stopping decoding early for improved performance.
This document summarizes techniques for error detection and correction in data communication systems. It discusses various error correction techniques including forward error correction using block codes, convolutional codes, and hybrid automatic repeat request. It focuses on convolutional codes and the Viterbi algorithm, describing the algorithm's use of branch metric computation, path metric computation, and traceback to decode data with the minimum accumulated error path. The document concludes that convolutional encoding with Viterbi decoding is an effective method for forward error correction in wireless communication systems.
This document discusses the design of an asynchronous Viterbi decoder using a bundled data protocol to reduce power consumption. Viterbi decoders are commonly used in wireless communications and other applications, but synchronous implementations consume significant power due to global clock distribution. The proposed asynchronous design uses local handshaking signals between blocks rather than a global clock. It employs a 4-phase bundled data protocol to communicate data between units like the branch metric unit, add-compare-select unit, and survivor path memory unit. The goal is to optimize these power-intensive units and achieve lower power operation through an asynchronous, clock-free design approach compared to traditional synchronous Viterbi decoders.
A New Bit Split and Interleaved Channel Coding for MIMO DecoderIJARBEST JOURNAL
Authors:-C. Amar Singh Feroz1, S. Karthikeyan2, K. Mala3
Abstract– In wireless communications, the use of multiple antennas at both the
transmitter and receiver is a key technology to enable high data transmission without
additional bandwidth or transmit power. MIMO schemes are widely used in many
wireless standards, allowing higher throughput using spatial multiplexing techniques.
Bit split mapping based on JDD is designed. Here ETI coding is used for encoding and
Viterbi is used for decoding. Experimental results for 16-QAM and 64 QAM with the
code rate of ½ and 1/3 codes are shown to verify the proposed approach and to elucidate
the design tradeoffs in terms the BER performance. This bit split mapping based JDD
algorithm can greatly improve BER performance with different system settings.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
This document summarizes a research paper that proposes using parallel concatenated turbo codes in wireless sensor networks in an adaptive way. The key points are:
1) Turbo codes can achieve near-Shannon limit performance but decoding is complex, making them difficult to implement on energy-constrained sensor nodes.
2) The proposed approach shifts the complex turbo decoding to the base station while sensor nodes implement encoding and basic error correction.
3) At sensor nodes, a parallel concatenated convolutional code (PCCC) circuit encodes data and detects/corrects errors in forwarded packets. This improves energy efficiency and reliability over the wireless sensor network.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.
Implementation of Joint Network Channel Decoding Algorithm for Multiple Acces...csandit
In this paper, we consider a Joint Network Channel Decoding (JNCD) algorithm applied to a
wireless network consisting to M users. For this purpose M sources desire to send information
to one receiver by the help of an intermediate node which is the relay. The Physical Layer
Network Coding (PLNC) allows the relay to decode the combined information being sent from
different transmitters. Then, it forwards additional information to the destination node which
receives also signals from source nodes. An iterative JNCD algorithm is developed at the
receiver to estimate the information being sent from each transmitter. Simulation results show
that the Bit Error Rate (BER) can be decreased by using this concept comparing to the
reference one which doesn’t consider the network coding.
IMPLEMENTATION OF JOINT NETWORK CHANNEL DECODING ALGORITHM FOR MULTIPLE ACCES...cscpconf
In this paper, we consider a Joint Network Channel Decoding (JNCD) algorithm applied to a wireless network consisting to M users. For this purpose M sources desire to send information
to one receiver by the help of an intermediate node which is the relay. The Physical Layer Network Coding (PLNC) allows the relay to decode the combined information being sent from different transmitters. Then, it forwards additional information to the destination node which receives also signals from source nodes. An iterative JNCD algorithm is developed at the receiver to estimate the information being sent from each transmitter. Simulation results show that the Bit Error Rate (BER) can be decreased by using this concept comparing to the reference one which doesn’t consider the network coding.
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...VIT-AP University
For design methodology of CRC or cyclic redundancy check is very used technique for error checking and shows the transmission reliability we are using the HDLC block. HDLC block is very useful in data communication these block operated in data link layer. For design methodology of CRC is to generate the CRC polynomial using XOR’s gate and shift register these polynomial are implement on software Xilinx Plan Ahead 13.1 and verify for simulation result for random testing of CRC bit on receiver side same result are obtained to show that it is more reliable.
CODING SCHEMES FOR ENERGY CONSTRAINED IOT DEVICESijmnct
This paper investigates the application of advanced forward error correction techniques mainly: lowdensity parity checks (LDPC) code and polar code for IoT networks. These codes are under consideration
for 5G systems. Different code parameters such as code rate and a number of decoding iterations are used
to show their effect on the performance of the network. LDPC is performed better than polar code, over the
IoT network scenario considered in the work, for the same coding rate and the number of decoding
iterations. Considering bit error rate (BER) performance, LDPC with rate1/3 provided an improvement of
up to 2.6 dB for additive white Gaussian noise (AWGN) channel, and 2 dB for SUI-3 (frequency selective
fading channel model). LDPC code gives an improvement in throughput of about 12% as compared to
polar code with a coding rate of 2/3 over AWGN channel. The corresponding values over SUI-3 channel
are about 10%. Finally, in comparison with LDPC, polar code shows better energy saving for large
number of decoding iterations and high coding rates.
CODING SCHEMES FOR ENERGY CONSTRAINED IOT DEVICESijmnct_journal
This paper investigates the application of advanced forward error correction techniques mainly: lowdensity parity checks (LDPC) code and polar code for IoT networks. These codes are under consideration for 5G systems. Different code parameters such as code rate and a number of decoding iterations are used
to show their effect on the performance of the network. LDPC is performed better than polar code, over the IoT network scenario considered in the work, for the same coding rate and the number of decoding iterations. Considering bit error rate (BER) performance, LDPC with rate1/3 provided an improvement of
up to 2.6 dB for additive white Gaussian noise (AWGN) channel, and 2 dB for SUI-3 (frequency selective fading channel model). LDPC code gives an improvement in throughput of about 12% as compared to polar code with a coding rate of 2/3 over AWGN channel. The corresponding values over SUI-3 channel
are about 10%. Finally, in comparison with LDPC, polar code shows better energy saving for large number of decoding iterations and high coding rates.
Performances Concatenated LDPC based STBC-OFDM System and MRC Receivers IJECEIAES
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srivastava2018.pdf
1. 1
Abstract— Optical communication has proven its capabilities
in fulfilling the ever increasing global desire for higher data rates
for long as well as short distance communication. In order to
achieve reliable communication several error detection
mechanisms have so far been implemented using conventional
electronics which do not match with the pace of optical
processing of digital bits. In this research, implementation of the
encoding of (7, 4) Cyclic Redundancy Check (CRC) code using
optical method has been shown. The CRC encoder has been
designed using Lithium Niobate (LiNbO3) waveguide based
Mach-Zehnder Interferometers (MZI). The structure simulated
using beam propagation method has shown accurate encoding of
the CRC code. The design parameters as well as the performance
parameters have been described briefly.
I. INTRODUCTION
High data rate is needed to fulfill the increasing demand of
the broadband services. To achieve high data rate, large
bandwidth is required but it is difficult to achieve using
conventional electronic circuits. Some researchers have found
that optical devices seem to be a good alternate solution.
Optical communication devices use optical switches for high
speed signal routing. Optical switches are the key components
of optical networks which can execute essential signal
processing function such as switching, regeneration, and
header recognition processing at photonic nodes [1], [2].
Different types of optical switches have been proposed like,
semiconductor optical amplifier- Mach-Zehnder
interferometer (SOA-MZI), opto-electronic SOA, quantum
dot - SOA (QD-SOA), bit differential delay technique with
Terahertz Optical Asymmetric Demultiplexers (TOAD) [3],
nonlinear material based intensity encoder [4], semiconductor
optical amplifier (SOA)-assisted Sagnac switch technology
[5], and micro-ring resonator technology [6]. Cross gain and
cross phase effect in SOA limit its speed due to saturation
effect. Bit differential delay techniques have round trip delay
which increase the time-of-flight (TOF) latency. Lithium
niobate based MZI [7] provide promising solution because of
its characteristic features like compact size, thermal stability,
integration potential [8], re-configurability and low power
consumption [9]. With the advancement in the optical
communication, high speed long distance communication has
been made possible. This is because optical communication
* Vivek Kumar Srivastava is pursuing Ph.D from DIT University,
Dehradun, India (srivastava17vivek@ gmail.com).
Amrindra Pal is an Assistant Professor in the Department of Electrical and
Electronics & Communication, DIT University, Dehradun, India (phone: +91
9012195515; amrindra.pal123@gmail.com).
provides ultra-fast switching which enables high speed data
transmission. It also minimizes the losses occurring over long
distances enabling one to use minimal number of repeaters [5].
Lossy channel may change signal intensity for logic 1 at the
output due to which optical circuits consider it as logic 0.
Conversion of bit(s) (1 to 0 or vice-versa) may lead to major
errors [10]. Such errors may be avoided, but up to some extent
only [11]. Hence, there arises a need to detect such errors at
the receiver end. Here comes the role of redundancy, which
although increases the code length but provides an effective
method to recover the original message from the received
contaminated word.
It were the seminal works of Shannon and Hamming which
proved to be a landmark in the field of coding theory [12], [13].
To achieve error free communication over a lossy channel one
needs to add redundant bits to the data in such a way which
enables the receiver to detect the error(s) although they do not
add any new information in the code. Vertical redundancy
check (VRC) is the least expensive mechanism for detecting
errors in the receive codeword. Codewords with a minimum
hamming distance of two can detect all single-bit errors at the
destination. An easy way to detect burst errors (multiple bit-
errors) is to use longitudinal redundancy check (LRC). An n-
bit LRC can detect all burst errors up to length n. Another error
detection method used is checksum, which can detect errors
unnoticed by VRC and LRC [14]. Error detection using
checksum is performed using one’s complement. But, mere
detection of error in the received codeword does not fully solve
the problem. It is important for a reliable communication
system to also detect the position of error bit. The above
discussed methods can only detect error in the received word
but cannot indicate the bit-position of the error [14]. To detect
the position of the bit with error correction tools are employed.
The cyclic code - Cyclic redundancy check (CRC) has proved
to be a powerful tool in error correction mechanisms, having
the capability to correct burst errors [15], [16]. Hardware
implementation of CRC is also not so much difficult which
requires two major components as shift register and modulo-2
adder. Modulo-2 addition as well as subtraction can easily be
achieved using a 2-input XOR gate. CRC codes find their
applications in computer networks like LANs and WANs.
Shreya is pursuing M. Tech at Department of Electrical and Electronics &
Communication, DIT University, Dehradun, India
(shreyadhyani271@gmail.com).
Sandeep Sharma is an Associate Professor in the Department of Electrical
and Electronics & Communication, DIT University, Dehradun, India.
(tek.learn@gmail.com).
Design of Electro-Optical Cyclic Redundancy Check Encoder using
Lithium Niobate waveguide for Reliable Communication*
Vivek Kumar Srivastava, Amrindra Pal, Shreya and Sandeep Sharma, Member, IEEE
Department of Electrical and Electronics & Communication Engineering, DIT University, India
2. Some of the commonly used CRC codes are listed here in
Table I [16].
TABLE I. COMMONLY USED CRC CODES WITH APPLICATIONS
CRC Code Applications
CRC-4 ITU G.704
CRC-8 ATM header
CRC-10 ATM AAL
CRC-16 Bluetooth
CRC-32 LANs
In this paper, (7, 4) CRC encoder for optical
communication systems is proposed which is capable enough
to accurately detect any single bit error in the received word.
The encoder has been designed using electro-optical switches
implemented using Lithium Niobate (LiNbO3) based Mach-
Zehnder Interferometer (MZI) using OptiBPM software based
on the principles of beam propagation method (BPM). The
CRC has further been reviewed in the paper.
Section II gives a short review of cyclic codes. In section
III an MZI design of CRC has been proposed. Section IV
explains the mathematical formulation and MATLAB
simulation results for the proposed device. Next, Section V
consists of BPM simulation results and case study for a few
received codewords.
II. REVIEW OF CYCLIC CODES
A (7,4) block code consists of 4 data bits 1
2
3 ,
, D
D
D and
0
D followed by 3 redundant bits called parity. There can be
sixteen 7-bit codewords formed from 4-bit datawords
0
1
2
3 D
D
D
D
D = . Block codes can broadly be classified as
linear and cyclic codes. Adding two linear codewords results
into another codeword. Cyclic codes are a special class of
linear block codes with a cyclic structure. A cyclic shift in a
codeword will result in another codeword. The cyclic structure
makes them convenient for their practical implementation
[17].
An ( )
k
n, code is designed using a generator polynomial
which is a factor of 1
+
n
x having a maximum power of
( )
k
n − . Therefore, for a (7,4) cyclic code
0
1
2
3
4
5
6 C
C
C
C
C
C
C
C = :
)
1
)(
1
)(
1
(
1 2
3
3
7
+
+
+
+
+
=
+ x
x
x
x
x
x (1)
So the generator polynomial may be taken as either:
1)
+
x
+
(x
)
( 3
=
x
g (2)
or, )
1
(
)
( 2
3
+
+
= x
x
x
g (3)
Here, in this paper the (7, 4) cyclic code has been designed
using )
1
(
)
( 2
3
+
+
= x
x
x
g , which is equivalent to generator
code 1011. Similarly 4 bit dataword can also be written in a
polynomial expression as ( )
x
d . The generator polynomial is
used to divide the expression ( )
x
d
x k
n−
to obtain the ( )
k
n −
bit remainder polynomial ( )
x
r . This remainder polynomial
( )
x
r is appended at the end of the dataword to give the
designed 7 bit CRC codeword polynomial ( )
x
c .
)
(
)
(
)
( x
r
x
d
x
x
c k
n
+
= −
(4)
Using the above description the designed encoder is shown
in Fig. 1. The ‘+’ sign in (1-4) refers to modulo-2 addition,
which is equivalent to XOR of two bits. This makes
implementation of this encoder simpler and easier.
Figure 1. (7, 4) CRC encoder for 1)
+
x
+
(x
)
( 3
=
x
g
The encoder consists of a 3-bit shift register containing the
bits 1
0,C
C and 2
C which are initially cleared. The encoder
works by shifting the bits stored in the shift register at each
pulse cycle t. Starting with MSB, a data-bit enters the encoder
at each pulse cycle. At the same time the data-bits are fed to
the output, generating first 4 code-bits ( 3
4
5
6 C
C
C
C ) of the 7-
bit codeword for t = 1 to 4, as the output switch S1 is connected
to the input data-bit pin. Meanwhile, rest of the 3 code bits are
generated at the end of the 4th
pulse cycle which are extracted
serially. The whole process is explained in the following lines.
During the first 4 pulse cycles switch S2 remains closed; the
data bits and the shifted values stored in 1
0,C
C and 2
C are
XORed and shifted forward to the right. After 4 pulse cycles
the output switch S1 moves to check bits and S2 gets opened
up, subsequently the final generated check bits are transferred
to the output in next 3 pulse cycles [17], [18].
The check bits generation process only for t = 0 to 4 has
been shown here in Table II. Next three cycles are mere
shifting of the check bits generated in pulse cycle 4. A total of
7 pulse cycles are involved in generating the codeword.
TABLE II. CHECK BITS GENERATION CYCLE
Pulse
Cycle
Input Data
Bits
Check Bits
t Di
C0, t
= Di + C2, t-1
C1, t
= C0, t-1 +C0, t
C2, t
= C1, t-1
0 - 0 0 0
1 D3 D3 + C2, 0 C0, 0 + C0, 1 C1, 0
2 D2 D2 + C2, 1 C0, 1 + C0, 2 C1, 1
3 D1 D1 + C2, 2 C0, 2 + C0, 3 C1, 2
4 D0 D0 + C2 , 3 C0, 3 + C0, 4 C1, 3
C0 C1 C2
Generated Check Bits
Design of the (7,4) code using the other generator
polynomial i.e. )
1
(
)
( 2
3
+
+
= x
x
x
g would result in a similar
but different encoder structure.
In Table III, sixteen possible codewords derived from
different data bit combinations of 1
2
3 ,
, D
D
D and 0
D are
3. described. Any single bit change in any of these sixteen
codewords will result in an erroneous word. This one bit
contaminated word will be one among the 27
– 24
= 112 words.
The error position in the codeword can easily be found by
calculating the syndrome for the received word. Syndrome is
an indicator of the bit-error position. A zero value of syndrome
indicates no error in received word, whereas a non-zero value
indicates an error at a particular bit-position. The error position
can be found using a predefined method similar to the
encoding process that has not been described in this paper.
TABLE III. TRUTH TABLE FOR (7,4) CRC, 1)
+
x
+
(x
)
( 3
=
x
g
S.
No.
Dataword Codeword
D3 D2 D1 D0 C6 C5 C4 C3 C2 C1 C0
1 0 0 0 0 0 0 0 0 0 0 0
2 0 0 0 1 0 0 0 1 0 1 1
3 0 0 1 0 0 0 1 0 1 1 0
4 0 0 1 1 0 0 1 1 1 0 1
5 0 1 0 0 0 1 0 0 1 1 1
6 0 1 0 1 0 1 0 1 1 0 0
7 0 1 1 0 0 1 1 0 0 0 1
8 0 1 1 1 0 1 1 1 0 1 0
9 1 0 0 0 1 0 0 0 1 0 1
10 1 0 0 1 1 0 0 1 1 1 0
11 1 0 1 0 1 0 1 0 0 1 1
12 1 0 1 1 1 0 1 1 0 0 0
13 1 1 0 0 1 1 0 0 0 1 0
14 1 1 0 1 1 1 0 1 0 0 1
15 1 1 1 0 1 1 1 0 1 0 0
16 1 1 1 1 1 1 1 1 1 1 1
III. DESIGN OF (7,4) CRC STRUCTURE USING MZI
The encoder circuit depicted in Fig. 1 has here been
implemented using the electro-optical switching characteristic
of LiNbO3 waveguide based MZI (shown in Fig. 2). A
continuous optical wave applied to one of the input ports of an
MZI can be produced at one of the output ports in a controlled
manner by suitable application of appropriate electric potential
on the three electrodes of the MZIs. To apply a bit ‘1’ a
potential of 6.75 volts is applied as the control signal at the
second electrode of each of the MZI. The first and third
electrodes are kept at ground.
In Fig. 2, a continuous optical wave is applied at each of
the first input ports of MZI 1 and MZI 3. In the schematic view
of the proposed structure the check bits are followed by a
subscript containing a number followed by a time unit such as
t
C ,
0 . This representation has been used just to differentiate
between different check bits and their values at different pulse
cycles. As an example, 2
,
0
C represents the check bit 0
C at
pulse cycle t = 2. The text written in red in Fig.2 can be
assumed as optical signals.
MZI 1 and MZI 2 are cascaded to generate the check-bit
t
C ,
0 which is the modulo-2 sum of i
D and ( )
1
,
2 −
t
C . At every
pulse cycle subsequent data bits are applied at MZI 1 as control
signal. The optical output t
C ,
0 is converted to electric signal
using a photo-detector and an amplifier to obtain a potential of
6.75 volts or 0 volts, depending upon the status of the bit t
C ,
0
. This electric signal is applied at MZI 3. MZI 4 carries the bit
( )
1
,
0 −
t
C . MZI 3 and MZI 4 together produce t
C ,
1 bit. The
output 1
C is connected to a unit delay element to produce 2
C in
the next pulse cycle. The check bits generated at each pulse
cycle can be stored using an optical delay flip-flop [19], to
perform shifting of the resultant bits. The status of the optically
generated check-bits at the end of 4 pulse cycles denote the
final remainder . These signals may be captured optically
or may be converted to electric signals as per the requirement
of the user. In this way, the last three bits of the
codeword are obtained, while are already
present with the user in the form of the data bits .
Figure 2. Schematic view of the proposed (7, 4) CRC encoder
IV. MATHEMATICAL FORMULATION AND MATLAB
SIMULATION
Using the equation for power at the output bar port of a
single MZI [20] the normalized power for two cascaded MZIs
to produce XOR output at the second output port can be
derived for the output and .
Δ
Δ
+
Δ
Δ
=
2
cos
2
sin
2
sin
2
cos
2
2
1
2
2
2
1
2
0
MZI
MZI
MZI
MZI
C
P
ϕ
ϕ
ϕ
ϕ
(5)
Δ
Δ
+
Δ
Δ
=
2
cos
2
sin
2
sin
2
cos
4
2
3
2
4
2
3
2
1
MZI
MZI
MZI
MZI
C
P
ϕ
ϕ
ϕ
ϕ
(6)
where,
2
1 i
i
MZIi ϕ
ϕ
ϕ −
=
Δ (7)
for i = 1 to 4.
The output power of the output 2
C will be same as derived
for the output 1
C (6).
The above equations were designed on MATLAB 2014a.
The obtained results are presented below in Fig. 3 in a concise
4. format. The first four waveforms show the 16 possible
combinations of the dataword 0
1
2
3 D
D
D
D
D = . These
combinations are also a representative of the first four code-
bits 3
4
5
6 C
C
C
C . Corresponding generated check bits 0
1
2 C
C
C
are shown in the last three waveforms. In a way the 7
waveforms present the 16 - (7, 4) CRC codewords that were
desired to be generated. The results are in complete agreement
with the codewords present in the truth table (Table III).
Figure 3. MATLAB simulation waveforms for (7, 4) CRC codewords
V. DESIGN OF (7, 4) CRC USING BEAM PROPAGATION
METHOD (BPM)
The proposed structure as designed using beam
propagation method on the platform OptiBPM, Version 12.1,
a product of Optiwave, has been presented in Fig. 4. The
software provides modelling and simulation of various
integrated optical structures such as linear and nonlinear
waveguide based MZI, directional couplers, etc. Propagation
of light may be simulated in 2 dimensional or 3 dimensional
waveguide based devices. Here in this work 2 dimensional
simulation has been performed. Other simulation parameters
of the designed structure have been specified in Table IV.
Figure 4. BPM layout of the designed structure
The structure shows two parallel paths to generate the bits
t
C ,
0 and t
C ,
1 . The structure does not show the generation of
the bit t
C ,
2 , as it is same as the ( )
1
,
1 −
t
C . Hence, it can be
captured from the previous cycle. As discussed earlier, these
generated bits may be stored using a memory element.
TABLE IV. SIMULATION PARAMETERS FOR THE DESIGNED
STRUCTURE
S. N. Design Characteristic Parameter
1 Input optical plane 3400 µm
2 Polarization TM
3 Wafer Dimensions (Length × Width) 95314µm×300µm
4 Substrate LiNbO3
5 Cladding Air
6 Wavelength 1.3 µm
7 Global Refractive Index (Modal) 2.147
8 Engine Finite Difference
The simulation has been carried in accordance with Table
II. The optical outputs for each pulse cycle are shown in Fig.
5 and Fig. 6 along with the check-bit generation tables for the
corresponding data, for two different datawords randomly
chosen from the truth table presented in Table III.
For dataword = 0110:
Figure 5. BPM simulation results for: dataword = 0110
The check-bit generation table for the above case is shown
in Table V showing all the pulse cycles and the corresponding
results.
TABLE V. CHECK BIT GENERATION TABLE FOR DATAWORD=0110
Pulse
Cycle
Input Data
Bit
Check Bits
t
Data=0110
Di
C0, t
= Di + C2, t-1
C1, t
= C0, t-1 +C0, t
C2, t
= C1, t-1
0 - 0 0 0
1 D3 =0 0 + 0 = 0 0 + 0 = 0 0
2 D2 =1 1 + 0 = 1 1 + 0 = 1 0
3 D1 =1 1 + 0 = 1 1 + 1 = 0 1
4 D0= 0 0 + 1 = 1 1 + 1 = 0 0
C0 = 1 C1 = 0 C2 = 0
For dataword = 1010:
Figure 6. BPM simulation results for dataword =1010
5. The check-bit generation results at each pulse cycle for
dataword=1010 are shown in Table VI.
TABLE VI. CHECK BIT GENERATION TABLE FOR DATAWORD=1010
Pulse
Cycle
Input Data
Bit
Check Bits
t
Data=0110
Di
C0, t
= Di + C2, t-1
C1, t
= C0, t-1 +C0, t
C2, t
= C1, t-1
0 - 0 0 0
1 D3 =1 1 + 0 = 1 1 + 0 = 1 0
2 D2 =0 0 + 0 = 0 0 + 1 = 1 1
3 D1 =1 1 + 1 = 0 0 + 0 = 0 1
4 D0 =0 0 + 1 = 1 1 + 0 = 1 0
C0 = 1 C1 = 1 C2 = 0
Each MZI is working as an electro-optical switch
controlled by the bit applied to its electrodes. The input
optical signal reaches first output port i.e. the bar-port if the
bit applied is ‘1’; if the bit applied is ‘0’ the optical signal
propagates to the second output port or as called the cross-
port. The signal outputs that have to be noted in Fig. 5 are
4
,
1
3
,
1 ,C
C and 4
,
0
C which correspond to 1
2,C
C and 0
C ,
respectively.
The BPM results are in complete agreement with the check
bits generation tables presented for every cycle. The optical
field propagation variation at the two input ports and the four
possible output ports for the dataword ‘1010’, at the end of
pulse cycle 4 are presented below in Fig. 7:
(a)
(b)
Figure 7. Variation of Optical Field Propagation at (a) input ports (b)
output ports for dataword = 1010, pulse cycle 4
For all the cases the input ports are applied with a
continuous optical wave of 1 milli watt power. Fig. 7 (a) and
(b) show the YZ slice of the wafer at X-cut = 3400 which is
the input plane of the structure and at X-cut = 95314, the
output port, respectively. The check bit 0
C is generated at the
output port 2 of MZI 2 and 1
C at the output port 2 of MZI 4.
It can be seen from Fig. 7 (b) that some finite output is present
at the output port 1 of MZI 2 and MZI 4.
To calculate the performance of the cyclic code encoder,
some parameters like Contrast Ratio (CR) and extinction
ration (ER) are measured from the simulated output.
Extinction ratio is defined as:
= 0
max
1
min
log
10
)
(
P
P
dB
ER (8)
where 1
min
P is the minimum value of output power for logic
‘1’ and 0
max
P is the maximum output power for logic ‘0’
state.
A high value of ER is desirable for high speed switching of
an optical device and better sensitivity of the receiver [6],
[21].
Contrast Ratio (CR) is a significant factor for an optical
switching device that describes its overall performance
criterion, calculated as:
=
0
1
log
10
)
(
mean
mean
P
P
dB
CR (9)
where 1
mean
P is the mean value of output power for output
logic ‘1’ and 0
mean
P is the mean output power for output logic
‘0’ [22] . CR should be as high as possible. The CR value
obtained for the proposed structure presented in this paper is
above 20 dB.
Fig. 8 shows variation of extinction ratio vs. wavelength
and Fig. 9 shows ER vs. coupling ratio. Maximum extinction
ratio of 15.48 dB is achieved at 1.3µm and 0.5 coupling
coefficient.
6. Figure 8. Extinction ratio vs. wavelength
Figure 9. Extinction ratio vs. coupling coefficient
Table VII presents a comparison of ER and CR of few of
the optical switch/device designed using different design
technologies. The last row shows the parameters obtained for
the presented work.
TABLE VII. COMPARISON BETWEEN VARIOUS DESIGN METHODS
Design Method ER (dB) CR (dB) Ref.
Micro-ring resonator based
optical switch
12.1 15.56 [6]
All-optical Flip Flop based on
active MZI
- 11 [19]
Nonlinear photonic crystal ring
resonator
- 5.67 [23]
SOA-MZI (20 Gb/s) 9.22 > 8 [24]
MMI GaAs-GaAlAs 20.6 - [25]
7,4 CRC using LiNbO3 based
MZI (Presented work)
15.48 >20
The obtained parameters for the presented work show
values which are desirable for the successful performance of
the device for a reliable communication system. The design of
the structure is limited for designing of 7 bit codewords for 4-
bit datawords only. The design may easily be modified to
obtain codewords for longer datawords and detection of burst
errors be made possible.
ACKNOWLEDGMENT
The author(s) would like to gratefully acknowledge all the
reviewers for their valuable and constructive suggestions
regarding the paper.
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