The document discusses synchronization in telecommunications networks. It defines key terms like synchronization status message (SSM), synchronization supply unit (SSU), primary reference clock (PRC), and timing loops. It explains that synchronization is important to avoid loss of information and describes the effects of poor synchronization. Slips, which are the deletion or repetition of data blocks, are discussed as well their impact on different traffic types. Maintaining synchronization across networks is necessary to minimize slips.
Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) are standardized multiplexing protocols that transfer multiple digital bit streams over optical fiber using lasers or light-emitting diodes (LEDs). Lower data rates can also be transferred via an electrical interface.
Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) are standardized multiplexing protocols that transfer multiple digital bit streams over optical fiber using lasers or light-emitting diodes (LEDs). Lower data rates can also be transferred via an electrical interface.
In this video, I will explain what is QAM modulation and what is 16QAM.
QAM Stands for Quadrature Amplitude Modulation. QAM is both an analog and a digital modulation method. But here, we are only talking about QAM as a digital modulation.
Quadrature means that two carrier waves are being used, one sine wave and one cosine wave. These two waves are out of phase with each other by 90°, this is called quadrature.
At the receiving end, the sine and cosine wave can be decoded independently, this means that by using both a sine wave and a cosine wave, the communication channel's capacity is doubled comparing to using only one sine or one cosine wave. That is why quadrature is such a popular technique for digital modulation.
QAM modulation is a combination of Amplitude Shift Keying and Phase Shift Keying, both carrier wave is modulated by changing both its amplitude and phase. As shown in this 8QAM waveform, the top is the sine wave carrier, for bit 000, the sin wave has a phase shift of 0°, and an amplitude of 2. While for bit 110, the phase shift is 180°, and the amplitude now is 1. So both phase and amplitude are changed.
In 16QAM, the input binary data is combined into groups of 4 bits called QUADBITS.
As shown in this picture, the I and I' bits are sent to the sine wave modulation path, and the Q and Q' bits are sent to the cosine wave path. Since the bits are split and sent in parallel, so the symbol rate has been reduced to a quarter of the input binary bit rate. If the input binary data rate is 100 Gbps, then the symbol rate is reduced to only 25 Gbaud/second. This is the reason why 16QAM is under hot research for 100Gbps fiber optic communication.
The I and Q bits control the carrier wave's phase shift, if the bit is 0, then the phase shift is 180°, if the bit is 1, then the phase shift is 0°.
The I' and Q' bits control the carrier wave's amplitude, if bit is 0, then the amplitude is 0.22 volt, if the bit is 1, then the amplitude is 0.821 volt.
So each pair of bits has 4 different outputs. Then they are added up at the linear summer. 4X4 is 16, so there is a total of 16 different combinations at the output, that is why this is called 16QAM.
This illustration shows an example of how the QUADBIT 0000 is modulated onto the carrier waves.
Here I and I' is 00, so the output is -0.22 Volt at the 2-to-4-level converter, when timed with the sine wave carrier, we get -0.22sin(2πfct), here fc is the carrier wave's frequency. QQ' is also 00, so the other carrier wave output is -0.22cos(2πfct).
Here is the proof that quadbit 0000 is modulated as a sine wave with an amplitude of 0.311volt and a phase shift of -135°. You can now pause for a moment to study the proof.
This list shows the 16QAM modulation output with different amplitude and phase change for all 16 quadbits. On the right side is the constellation diagram which shows the positions of these quadbits on a I-Q diagram.
You can visit FO4SALE.com f
DELAY ERROR WITH META-STABILITY DETECTION AND CORRECTION USING CMOS TRANSMISS...VLSICS Design
The new technologies are giving the advance systems which are capable to perform multiple operations simultaneously. This all is possible by the scaling technology where the overall chip size get reduced but due to manufacturing and fabrication defects, certain design uncertainty arises thereby affecting the transistor performance by timing related effect. The robust circuit where sufficient margins are given sometime is nothing but a wastage of power to overcome this, hybrid technique called Razor was innovated which scaled the voltage dynamically and automatically detect and correct the timing related defects. This paper proposed a new design for the razor flip flop with CMOS transmission logic. The traditional design used the dynamic logic approach which has the drawback of threshold voltage attenuation which is removed by CMOS transmission logic and the transparency of the logic data at input and output is highly achieved. The overall purpose for such design is to reduce the power and delay of the circuit which is reduced by 0.6mW and 12.11ns respectively and thus increased the overall performance. The complexity of
the circuit is also reduced. The analyses of the circuit is done using Cadence virtuoso tool with 45n technology.
In this video, I will explain what is QAM modulation and what is 16QAM.
QAM Stands for Quadrature Amplitude Modulation. QAM is both an analog and a digital modulation method. But here, we are only talking about QAM as a digital modulation.
Quadrature means that two carrier waves are being used, one sine wave and one cosine wave. These two waves are out of phase with each other by 90°, this is called quadrature.
At the receiving end, the sine and cosine wave can be decoded independently, this means that by using both a sine wave and a cosine wave, the communication channel's capacity is doubled comparing to using only one sine or one cosine wave. That is why quadrature is such a popular technique for digital modulation.
QAM modulation is a combination of Amplitude Shift Keying and Phase Shift Keying, both carrier wave is modulated by changing both its amplitude and phase. As shown in this 8QAM waveform, the top is the sine wave carrier, for bit 000, the sin wave has a phase shift of 0°, and an amplitude of 2. While for bit 110, the phase shift is 180°, and the amplitude now is 1. So both phase and amplitude are changed.
In 16QAM, the input binary data is combined into groups of 4 bits called QUADBITS.
As shown in this picture, the I and I' bits are sent to the sine wave modulation path, and the Q and Q' bits are sent to the cosine wave path. Since the bits are split and sent in parallel, so the symbol rate has been reduced to a quarter of the input binary bit rate. If the input binary data rate is 100 Gbps, then the symbol rate is reduced to only 25 Gbaud/second. This is the reason why 16QAM is under hot research for 100Gbps fiber optic communication.
The I and Q bits control the carrier wave's phase shift, if the bit is 0, then the phase shift is 180°, if the bit is 1, then the phase shift is 0°.
The I' and Q' bits control the carrier wave's amplitude, if bit is 0, then the amplitude is 0.22 volt, if the bit is 1, then the amplitude is 0.821 volt.
So each pair of bits has 4 different outputs. Then they are added up at the linear summer. 4X4 is 16, so there is a total of 16 different combinations at the output, that is why this is called 16QAM.
This illustration shows an example of how the QUADBIT 0000 is modulated onto the carrier waves.
Here I and I' is 00, so the output is -0.22 Volt at the 2-to-4-level converter, when timed with the sine wave carrier, we get -0.22sin(2πfct), here fc is the carrier wave's frequency. QQ' is also 00, so the other carrier wave output is -0.22cos(2πfct).
Here is the proof that quadbit 0000 is modulated as a sine wave with an amplitude of 0.311volt and a phase shift of -135°. You can now pause for a moment to study the proof.
This list shows the 16QAM modulation output with different amplitude and phase change for all 16 quadbits. On the right side is the constellation diagram which shows the positions of these quadbits on a I-Q diagram.
You can visit FO4SALE.com f
DELAY ERROR WITH META-STABILITY DETECTION AND CORRECTION USING CMOS TRANSMISS...VLSICS Design
The new technologies are giving the advance systems which are capable to perform multiple operations simultaneously. This all is possible by the scaling technology where the overall chip size get reduced but due to manufacturing and fabrication defects, certain design uncertainty arises thereby affecting the transistor performance by timing related effect. The robust circuit where sufficient margins are given sometime is nothing but a wastage of power to overcome this, hybrid technique called Razor was innovated which scaled the voltage dynamically and automatically detect and correct the timing related defects. This paper proposed a new design for the razor flip flop with CMOS transmission logic. The traditional design used the dynamic logic approach which has the drawback of threshold voltage attenuation which is removed by CMOS transmission logic and the transparency of the logic data at input and output is highly achieved. The overall purpose for such design is to reduce the power and delay of the circuit which is reduced by 0.6mW and 12.11ns respectively and thus increased the overall performance. The complexity of
the circuit is also reduced. The analyses of the circuit is done using Cadence virtuoso tool with 45n technology.
Design of Real-time Self Establish Wireless Sensor For Dynamic NetworkIJTET Journal
Abstract— Wireless sensor network in the recent trend engaged with high speed responsive real time system. This type of real time system requires reliable and compatible sensor to work in an environment where the sensor is dynamic in nature. Sensor network is to design to perform a set of high level information processing tasks such as detection, tracking or classification. Application of sensor networks is wide ranging and can vary significantly in application requirements, modes of deployment, sensing modality, power supply. Dynamic configuring of wireless sensor involves timing constraints to configure the sensor or to switch an adaptive sensor when working node failure due to energy, data rate, packet loss and range of the sensor. So the network, with such dynamic nature needs a background sensor which is able to be switched when the active sensor has a problem and improper functioning due to the network deploy environment. The background sensor lies inactive inside the range of the active sensor; ensure that the sensor is about to die and make sure the last data transfer successful find delay time to switch. Fault tolerance is achieved by switching the background sensor with the active sensor, where the background sensor self establish themselves in the network and perform similar routing metrics and configure them self with the network as soon they are switched. Once, the actual sensor retained back to the active condition then the background sensor will go to inactive state during this switching process the sensor will not loss data packet.
A continuous time adc and digital signal processing system for smart dust and...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
why time synchronization is important in power generation, transmission and ...Mohd Amir
Meinberg products make frictionless power transportation possible. By accurately synchronizing your IT-Network and reliably monitoring your power line frequency
Introduction
Background
WSN Design Issues: MAC Protocols, Routing Protocols, Transport Protocols
Performance Modeling of WSNs: Performance Metrics, Basic Models, Network Models
Case Study: Simple Computation of the System Life Span
Practical Example.
The numerically controlled oscillator (NCO) is one of the digital oscillator
signal generators. It can generate the clocked, synchronous, discrete
waveform, and generally sinusoidal. Often NCOs care utilized in the
combinations of digital to analog converter (DAC) at the outputs for creating
direct digital synthesizer (DDS). The network on chips (NOCs) are utilized
in various communication systems that are fully digital or mixed signals
such as synthesis of arbitrary wave, precise control for sonar systems or
phased array radar, digital down/up converters, all the digital phase locked
loops (PLLs) for cellular and personal communication system (PCS) base
stations and drivers for acoustic or optical transmissions and multilevel
phase shift keying/frequency shift keying (PSK/FSK) modulators or
demodulators (modem). The basic architecture of NCO will be enhanced
and improved with less hardware for facilitating complete system level
support to various sorts of modulation with minimum FPGA resources. In
this paper design and memory optimization of hybrid gate diffusion input
(GDI) numerically controlled oscillator based on field programmable gate
array (FPGA) is implemented. compared with NCO based 8-bit microchip,
memory optimization of hybrid GDI numerically controlled oscillator based
on FPGA gives effective outcome in terms of delay, metal-oxidesemiconductor field-effect transistors (MOSFET’s) and nodes.
There is a pressing need to distribute accurate timing, i.e., frequency and/or Time of Day (ToD), across Packet Switched Networks (PSNs) for applications such as cellular backhaul. This paper reviews the main issues involved in timing over packet (ToP) demarcation and provides best practices for ToP demarcation and performance monitoring.
Configuring the communication on FlexRay: the case of the static segmentNicolas Navet
N. Navet, M. Grenier, L. Havet, "Configuring the communication on FlexRay: the case of the static segment", Proc. of the 4th European Congress Embedded Real Time Software (ERTS 2008), Toulouse, France, January 29 - February 1, 2008.
DSP Based Implementation of Scrambler for 56kbps ModemCSCJournals
Scrambler is generally employed in data communication systems to add redundancy in the transmitted data stream so that at the receiver end, timing information can be retrieved to aid the synchronization between data terminals. Present paper deals with simulation and implementation of the scrambler for 56Kbps voice-band modem. Scrambler for the transmitter of 56kbps modem was chosen as a case study. Simulation has been carried out using Simulink of Matlab. An algorithm for the scrambling function has been developed and implemented on Texas Instrument’s based TMS320C50PQ57 Digital Signal Processor (DSP). Signalogic DSP software has been used to compare the simulated and practical results.
Similar to Synchronization and timing loop presentation -mapyourtech (20)
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...Levi Shapiro
Letter from the Congress of the United States regarding Anti-Semitism sent June 3rd to MIT President Sally Kornbluth, MIT Corp Chair, Mark Gorenberg
Dear Dr. Kornbluth and Mr. Gorenberg,
The US House of Representatives is deeply concerned by ongoing and pervasive acts of antisemitic
harassment and intimidation at the Massachusetts Institute of Technology (MIT). Failing to act decisively to ensure a safe learning environment for all students would be a grave dereliction of your responsibilities as President of MIT and Chair of the MIT Corporation.
This Congress will not stand idly by and allow an environment hostile to Jewish students to persist. The House believes that your institution is in violation of Title VI of the Civil Rights Act, and the inability or
unwillingness to rectify this violation through action requires accountability.
Postsecondary education is a unique opportunity for students to learn and have their ideas and beliefs challenged. However, universities receiving hundreds of millions of federal funds annually have denied
students that opportunity and have been hijacked to become venues for the promotion of terrorism, antisemitic harassment and intimidation, unlawful encampments, and in some cases, assaults and riots.
The House of Representatives will not countenance the use of federal funds to indoctrinate students into hateful, antisemitic, anti-American supporters of terrorism. Investigations into campus antisemitism by the Committee on Education and the Workforce and the Committee on Ways and Means have been expanded into a Congress-wide probe across all relevant jurisdictions to address this national crisis. The undersigned Committees will conduct oversight into the use of federal funds at MIT and its learning environment under authorities granted to each Committee.
• The Committee on Education and the Workforce has been investigating your institution since December 7, 2023. The Committee has broad jurisdiction over postsecondary education, including its compliance with Title VI of the Civil Rights Act, campus safety concerns over disruptions to the learning environment, and the awarding of federal student aid under the Higher Education Act.
• The Committee on Oversight and Accountability is investigating the sources of funding and other support flowing to groups espousing pro-Hamas propaganda and engaged in antisemitic harassment and intimidation of students. The Committee on Oversight and Accountability is the principal oversight committee of the US House of Representatives and has broad authority to investigate “any matter” at “any time” under House Rule X.
• The Committee on Ways and Means has been investigating several universities since November 15, 2023, when the Committee held a hearing entitled From Ivory Towers to Dark Corners: Investigating the Nexus Between Antisemitism, Tax-Exempt Universities, and Terror Financing. The Committee followed the hearing with letters to those institutions on January 10, 202
Introduction to AI for Nonprofits with Tapp NetworkTechSoup
Dive into the world of AI! Experts Jon Hill and Tareq Monaur will guide you through AI's role in enhancing nonprofit websites and basic marketing strategies, making it easy to understand and apply.
Embracing GenAI - A Strategic ImperativePeter Windle
Artificial Intelligence (AI) technologies such as Generative AI, Image Generators and Large Language Models have had a dramatic impact on teaching, learning and assessment over the past 18 months. The most immediate threat AI posed was to Academic Integrity with Higher Education Institutes (HEIs) focusing their efforts on combating the use of GenAI in assessment. Guidelines were developed for staff and students, policies put in place too. Innovative educators have forged paths in the use of Generative AI for teaching, learning and assessments leading to pockets of transformation springing up across HEIs, often with little or no top-down guidance, support or direction.
This Gasta posits a strategic approach to integrating AI into HEIs to prepare staff, students and the curriculum for an evolving world and workplace. We will highlight the advantages of working with these technologies beyond the realm of teaching, learning and assessment by considering prompt engineering skills, industry impact, curriculum changes, and the need for staff upskilling. In contrast, not engaging strategically with Generative AI poses risks, including falling behind peers, missed opportunities and failing to ensure our graduates remain employable. The rapid evolution of AI technologies necessitates a proactive and strategic approach if we are to remain relevant.
Honest Reviews of Tim Han LMA Course Program.pptxtimhan337
Personal development courses are widely available today, with each one promising life-changing outcomes. Tim Han’s Life Mastery Achievers (LMA) Course has drawn a lot of interest. In addition to offering my frank assessment of Success Insider’s LMA Course, this piece examines the course’s effects via a variety of Tim Han LMA course reviews and Success Insider comments.
How to Make a Field invisible in Odoo 17Celine George
It is possible to hide or invisible some fields in odoo. Commonly using “invisible” attribute in the field definition to invisible the fields. This slide will show how to make a field invisible in odoo 17.
2024.06.01 Introducing a competency framework for languag learning materials ...Sandy Millin
http://sandymillin.wordpress.com/iateflwebinar2024
Published classroom materials form the basis of syllabuses, drive teacher professional development, and have a potentially huge influence on learners, teachers and education systems. All teachers also create their own materials, whether a few sentences on a blackboard, a highly-structured fully-realised online course, or anything in between. Despite this, the knowledge and skills needed to create effective language learning materials are rarely part of teacher training, and are mostly learnt by trial and error.
Knowledge and skills frameworks, generally called competency frameworks, for ELT teachers, trainers and managers have existed for a few years now. However, until I created one for my MA dissertation, there wasn’t one drawing together what we need to know and do to be able to effectively produce language learning materials.
This webinar will introduce you to my framework, highlighting the key competencies I identified from my research. It will also show how anybody involved in language teaching (any language, not just English!), teacher training, managing schools or developing language learning materials can benefit from using the framework.
Synthetic Fiber Construction in lab .pptxPavel ( NSTU)
Synthetic fiber production is a fascinating and complex field that blends chemistry, engineering, and environmental science. By understanding these aspects, students can gain a comprehensive view of synthetic fiber production, its impact on society and the environment, and the potential for future innovations. Synthetic fibers play a crucial role in modern society, impacting various aspects of daily life, industry, and the environment. ynthetic fibers are integral to modern life, offering a range of benefits from cost-effectiveness and versatility to innovative applications and performance characteristics. While they pose environmental challenges, ongoing research and development aim to create more sustainable and eco-friendly alternatives. Understanding the importance of synthetic fibers helps in appreciating their role in the economy, industry, and daily life, while also emphasizing the need for sustainable practices and innovation.
Palestine last event orientationfvgnh .pptxRaedMohamed3
An EFL lesson about the current events in Palestine. It is intended to be for intermediate students who wish to increase their listening skills through a short lesson in power point.
The Roman Empire A Historical Colossus.pdfkaushalkr1407
The Roman Empire, a vast and enduring power, stands as one of history's most remarkable civilizations, leaving an indelible imprint on the world. It emerged from the Roman Republic, transitioning into an imperial powerhouse under the leadership of Augustus Caesar in 27 BCE. This transformation marked the beginning of an era defined by unprecedented territorial expansion, architectural marvels, and profound cultural influence.
The empire's roots lie in the city of Rome, founded, according to legend, by Romulus in 753 BCE. Over centuries, Rome evolved from a small settlement to a formidable republic, characterized by a complex political system with elected officials and checks on power. However, internal strife, class conflicts, and military ambitions paved the way for the end of the Republic. Julius Caesar’s dictatorship and subsequent assassination in 44 BCE created a power vacuum, leading to a civil war. Octavian, later Augustus, emerged victorious, heralding the Roman Empire’s birth.
Under Augustus, the empire experienced the Pax Romana, a 200-year period of relative peace and stability. Augustus reformed the military, established efficient administrative systems, and initiated grand construction projects. The empire's borders expanded, encompassing territories from Britain to Egypt and from Spain to the Euphrates. Roman legions, renowned for their discipline and engineering prowess, secured and maintained these vast territories, building roads, fortifications, and cities that facilitated control and integration.
The Roman Empire’s society was hierarchical, with a rigid class system. At the top were the patricians, wealthy elites who held significant political power. Below them were the plebeians, free citizens with limited political influence, and the vast numbers of slaves who formed the backbone of the economy. The family unit was central, governed by the paterfamilias, the male head who held absolute authority.
Culturally, the Romans were eclectic, absorbing and adapting elements from the civilizations they encountered, particularly the Greeks. Roman art, literature, and philosophy reflected this synthesis, creating a rich cultural tapestry. Latin, the Roman language, became the lingua franca of the Western world, influencing numerous modern languages.
Roman architecture and engineering achievements were monumental. They perfected the arch, vault, and dome, constructing enduring structures like the Colosseum, Pantheon, and aqueducts. These engineering marvels not only showcased Roman ingenuity but also served practical purposes, from public entertainment to water supply.
2. ITU Recommendations
G.781 –Synchronization layer functions
G.783 –Characteristics of synchronous digital hierarchy (SDH) equipment functional
blocks
G.810 –Definition and Terminology of Synchronous Networks
G.811 –Timing Characteristics of Primary Reference Clocks
G.812 –Timing requirements of slave clocks suitable for use as node clocks in
synchronization networks
G.813 –Timing characteristics of SDH equipment slave clocks (SEC)
G.822 –Controlled Slip Rate Objectives on an international digital connection
G.823 –The control of jitter and wander within digital networks which are based on
the 2048 kbit/s hierarchy
G.824 –The control of jitter and wander within digital networks which are based on
the 1544 kbit/s hierarchy
G.825 –The control of jitter and wander within digital networks which are based on
the synchronous digital hierarchy (SDH)
2email:sanjay.yadav@mapyourtech.com
3. Introduction
The introduction of digital 64 kb/s circuit switches (end office and tandem switching systems)
and digital cross-connect systems in the late 1970s and early 1980s drove the need for network
synchronization.
Synchronization in telecommunications networks is the process of aligning the time scales of
transmission and switching equipment so equipment operations occur at the correct time and in
the correct order. Synchronization requires the receiver clock to acquire and track the periodic
timing information in a transmitted signal.
The transmitted signal (Fig. 1a) consists of data that is clocked out at a rate determined by the
transmitter clock. Signal transitions between zero and peak values contain the clocking
information and detecting these transitions allows the clock to be recovered at the receiver (Fig.
1b). The recovered clock is used to write the received data into a buffer, also called elastic store
or circular shift register, to reduce jitter (jitter is discussed later in this section). The data is then
read out of the buffer onto a digital bus for further multiplexing or switching (Fig. 1c).
Fig. 1a – Transmitter and Receiver Clocks
The received signal is processed by the clock recovery circuit, and the clock is then used to recover the
data. The transmitter and receiver circuits for both directions are identical. The receiver on the right is
shown in slightly more detail.Fig.1a is as below.
3email:sanjay.yadav@mapyourtech.com
4. Synchronization
The synchronization network is a network that shall be able to provide all types of telecommunication traffic
networks with reference timing signals of required quality. The objective for the traffic networks, for example
switching, transport, signaling, mobile, is to not lose information. Loss of information is often caused by poor
synchronization. This can be avoided by properly connecting the traffic network to an adequate
synchronization network (how to connect to a synchronization network is normally called network
synchronization).In the best case, poor synchronization causes only limited inconvenience to the traffic
network. In the worst case, it can make the entire telecommunication network stop passing traffic.
Poor synchronization causes loss of information in varying degrees. Examples of
results of poor synchronization are:
• degraded traffic throughput;
• inhibition of set-up of calls (#7 signaling) due to re-transmission;
• re-sending of files;
• corrupt fax messages;
• degraded speech quality;
• freeze-frames on video;
• disconnection of calls during hand-over in mobile networks;
• partial or complete traffic stoppage.
The results for network operators providing poor synchronization to their networks are: reduced short and
long term income, decreased customer satisfaction, low network availability and low traffic throughput.
4email:sanjay.yadav@mapyourtech.com
5. Basic Terminology
Synchronization Status Message (SSM)
It is defined in EN 300 417-6-1 [3]. This is a signal that is passed over a synchronization interface to indicate the
Quality-Level of the clock sourcing the synchronization signal. This signal was originally defined for use over
STM-N interfaces in the S1 byte. It has since been proposed for use over 2 Mbit/s interfaces as well.
The SSM code transmitted reflects the quality of the clock that the interface is ultimately traceable to; i.e. the
grade-of clock to which it is synchronized directly or indirectly via a chain of network element clock's (the
synchronization trail),or how long this chain of clocks is. For example, the clock-source quality-level may be a
Primary Reference Clock (PRC) complying with EN 300 462-6-1 [9], or it may be a Slave Clock in holdover-mode,
complying with ETSI EN 300 462-4-1 [7], or an EN 300 462-5-1 [8] Clock in holdover or free-run.
The clock-source quality-level is essentially, therefore, an indication only of the long-term accuracy of the
network element clock.
In a fully synchronized network all sources should be ultimately traceable to a PRC and this should be indicated
using a '0010' code. The "Do Not Use for Synchronization" code is used to prevent timing loops and is
transmitted in the opposite direction on interfaces used to synchronize an equipment's clock. The "Quality
Unknown" code was originally proposed for connection to equipment that did not use SSM codes. ETSI has
proposed that this coding is not used as it cannot be sensibly used in a quality based selection algorithm.
5email:sanjay.yadav@mapyourtech.com
6. Synchronization Supply Unit (SSU):This unit is a high quality slave clock deployed in the
synchronization network.
The SSU gives two key benefits: it filters out short term phase noise (jitter) and short term wander and
provides a highly accurate clock if there is a failure of synchronization supply from the PRC. There are a number
of different SSU implementations, these are usually differentiated on their Frequency Accuracy in holdover
mode. They vary from more expensive Rubidium based oscillators to cheaper Quartz oscillators. There are also
a number of Higher Quality Quartz Oscillators which use improved techniques to reduce the temperature and
ageing effects of Quartz.
Stand Alone Synchronization Equipment (SASE): this is a piece of synchronization equipment
that contains an SSU. This term is used to differentiate from the SSU clock function itself which can be located
within another piece of equipment for instance an SDH DXC or 64 kbit/s switch.
Timing Loops: timing loops are created when a clock is directly or indirectly synchronized to itself.
Timing loops must be prevented because all clocks in a timing loop are isolated from a Primary Reference Clock
and are subject to unpredictable frequency instabilities. There is no simple way of detecting Timing loops as no
alarms are generated on their creation. They can go undiscovered until service is effected by poor slip or error
performance leading to an investigation which will eventually locate the timing loop.
Primary Reference Clock (PRC): these are the highest quality Clocks in a network and are usually
based on a freerunning Caesium Beam oscillator giving a very accurate clock performance.
Global Positioning System (GPS): system using a number of Satellites orbiting the earth, these
satellites are primarily intended to give positioning information for navigation but can also be used to derive a
highly accurate timing source of PRC Quality. To use GPS an antenna and a post processing unit are required.
6email:sanjay.yadav@mapyourtech.com
7. SLIPS
The deletion and repetition of a data block is called a slip. If the block consists of only one bit, it is called a bit slip
or clock slip. If the block consists of an entire data frame (for example, the 192 payload bits in a DS1 frame), it is
called a frame slip. If the slip occurs at the frame boundary and the framing bit is not lost, it is called a controlled
slip. On the other hand, an uncontrolled slip means that identification of the frame boundary was lost and there
was a Change Of Frame Alignment (COFA). An uncontrolled slip is more serious because meaningful transmission
is interrupted (the receiver is unable to accurately read bit values) until framing is re-established.
The overall object of network synchronization is to minimize controlled slips and eliminate uncontrolled slips.
This can be achieved only by synchronizing all equipment clocks in all nodes to the same master clock or to a
number of master clocks that operate plesiochronously (very closely matched).Frame slips have different effects
on different traffic types. Table 1 shows the effects of a single frame slip on an individual 64 kb/s (DS-0) channel.
The slip rate between plesiochronous networks can be calculated from Eq. 1.
SR = Δf FR 86,400⋅ ⋅ Eq. 1
where
SR = Slip rate (frame slips/day)
Δf = Frequency accuracy difference
FR = Frame rate (frames/second) [Note: All telecommunications systems operate at 8,000 frames/second]
86,400 = Number of seconds/day
As an example, consider two networks that are synchronized by different clocks. One clock has
an accuracy of +1x10–11 and the other has an accuracy of –1x10–11. The accuracy difference in
this case is 2x10–11. Therefore, the slip rate is 2x10–11 x 8,000 frames/second x 86,400
seconds/day = 0.0138 frame slips/day, or 72.3 days/frame slip.
7email:sanjay.yadav@mapyourtech.com
8. SLIPS…….
Since decided by the opposite end, the external source signal speed needs to be converted into the speed of
the local switching equipment before entering digital switching network. This is called Retiming, and is realized
through the buffer memory. The clock extracted from the source signals acts as the writing clock, which will
write bit flow into the buffer memory at the speed extracted from the source clock, then the clock of the
receiving equipment (local clock), acting as the reading clock, will read the bit flow out from the buffer. Thus
the source signal speed is converted into the local clock speed, as shown in Figure below.
When the write clock frequency disaccords with the read clock frequency, the buffer memory will overflow or
underflow, and a group of bits will be reread or unread, which we call it Slip. Since the buffer memory capacity
is generally greater than the data quantity of one frame (the typical value is of two frames' length), a frame of
data will be unread or reread when slip occurs. Such kind of slip which only rereads or leaves out a complete
frame, but does not disturb the frame structure, is called Controlled Slip or Frame Slip.
8email:sanjay.yadav@mapyourtech.com
10. Reference input signals:
T1, derived from:
STM-N (ITU-T Recommendation G.707 [18])
34 368 kbit/s with 125μs frame structure
139 264 kbit/s with 125μs frame structure
T2, derived from:
2 048 kbit/s (EN 300 166 [1])
T3, derived from:
2 048 kHz (EN 300 166 [1])
2 048 kbit/s (EN 300 166 [1]) with SSM according to (ITU-T Recommendation G.704 [16]).
Output signals:
T4: External reference signal,
2 048 kHz (ITU-T Recommendation G.703 [15]) (after physical interface)
2 048 kbit/s (EN 300 166 [1]) with SSM according to (ITU-T Recommendation G.704 [16]) (after
physical interface).
NOTE: The main application of 2 048 kbit/s signals with SSM is the exchange of synchronization status
information between an SSU and an SDH network element within a node.
T0: Timing signals for equipment-internal signal processing and for generating outgoing SDH traffic signals:
Frequencies are implementation-specific.
Basic properties for T0:
Frequency Accuracy: ± 4,6 × 10-6
Holdover: 5 × 10-8 (initial frequency offset)
2 × 10-6 (temperature)
1 × 10-8/day (aging)
10email:sanjay.yadav@mapyourtech.com
11. What are some timing/sync rules of thumb
1. A node can only receive the synchronization reference signal from another node
that contains a clock of equivalent or superior quality (Stratum level).
2. The facilities with the greatest availability (absence of outages) should be selected
for synchronization facilities.
3. Where possible, all primary and secondary synchronization facilities should be
diverse, and synchronization facilities within the same cable should be minimized.
4. The total number of nodes in series from the stratum 1 source should be
minimized. For example, the primary synchronization network would ideally look like a
star configuration with the stratum 1 source at the center. The nodes connected to
the star would branch out in decreasing stratum level from the center
5. No timing loops may be formed in any combination of primary
11email:sanjay.yadav@mapyourtech.com
12. Working Mode of the Clock Monitoring Module
The clock monitoring module can be configured to work in one of the following two modes:
Manual Mode
In this mode, the clock source is configured manually. The clock monitoring module does not switch the clock
source automatically, but just tracks the primary reference source. If the primary reference source is lost, the
clock monitoring module enters a holdover state.
Auto Mode
In auto mode, the clock source is selected by the system automatically. When the primary clock source is lost
or not available, the clock monitoring module selects another clock source based on the following rules:
If SSM level is not activated, the clock source is decided by reference source priority. If two
reference sources have the same priority, the one with the smaller reference source number (1 to 18) is
selected. When the reference source with the highest priority is lost, the next available reference source with
the highest priority is selected. When the former clock source becomes available, the system switches to that
clock again.
If SSM is activated, the clock source is decided by the SSM level. If two reference sources have the
same SSM level, the reference source priority takes effect, in the way described above.
Note:
The following clock sources are excluded in clock selection (when SSM is activated):
Clock sources whose signals are lost;
Clock sources whose priority is 255.
Clock sources whose SSM level is DNU (DoNotUse).
12email:sanjay.yadav@mapyourtech.com
13. Free Running Mode
An operating condition of a clock, the output signal of which is strongly influenced by
the oscillating element and not controlled by servo phase-locking techniques. In this
mode the clock has never had a network reference input, or the clock has lost external
reference and has no access to stored data, that could be acquired from a previously
connected external reference. Free-run begins when the clock output no longer
reflects the influence of a connected external reference, or transition from it. Free run
terminates when the clock output has achieved lock to an external reference.
An operating condition of a clock (a slave clock or a primary reference clock), where
the output signal’s frequency is not controlled with servo phase-locking to an external
reference and is, therefore, determined exclusively by an internal oscillator. In this
mode the clock has never had an external reference or, in the case of a slave clock,
the clock has lost the external reference and has no access to stored data acquired
from a previously connected external reference.
13email:sanjay.yadav@mapyourtech.com
14. Locked Mode
An operating condition of a slave clock in which the output signal is controlled by an
external input reference such that the clock’s output signal has the same long
term average frequency as the input reference, and the time error function
between output and input is bounded. Locked mode is the expected mode of
operation of a slave clock.
14email:sanjay.yadav@mapyourtech.com
15. Holdover Mode
An operating condition of a clock which has lost its controlling reference input and is
using stored data, acquired while in locked operation, to control its output. The
stored data are used to control phase and frequency variations, allowing the
locked condition to be reproduced within specifications. Holdover begins when
the clock output no longer reflects the influence of a connected external
reference, or transition from it. Holdover terminates when the output of the clock
reverts to locked mode condition.
An operating condition of a slave clock which has lost its controlling input and is
using stored data, acquired while in locked operation, to control its output. The
stored data is used to control frequency, attempting to reproduce locked mode
performance. Holdover begins when the clock output no longer reflects the
current behaviour of the external reference, or transition from it.
15email:sanjay.yadav@mapyourtech.com
16. Holdover Mode…
The system changes to the holdover mode when it loses all its external reference sources. Holdover performance controls the
maximum wander at the output in holdover mode.
The maximum fractional frequency offset Y(S) for the output signal is
Where x(S) is the output phase drift over the period of S seconds. The output Y(S) for Stratum 1 and Stratum 2 in the holdover mode
must meet the requirements in following table.
For Stratum 3 holdover as below in table
Time Interval (s) Average Frequency Deviation
0 < S 5000
The output signal phase in the first 5000 seconds meets the
requirements specified in 3.4.11 Phase Transient.
5000 < S 86400 1.5E-11
86400 < S 259200 2.5E-11
259200< S 604800 3E-11
Holdover Interval Average Frequency Deviation
1 day 1E-10
3 days 5E-10
16email:sanjay.yadav@mapyourtech.com
17. Why is Holdover Important?
Holdover is critical to ensuring service continuity as well as keeping the operator's OPEX to a minimum (e.g. elimination
of emergency truck rolls to the BTS site). In certain geographical areas where GPS signals are received only
intermittently, holdover is crucial for the operation of base stations. Holdover technologies are also necessary to
maintain sync during GPS outages caused by external events, such as in 2007 in San Diego when the US Air Force's
wide-scale denial of GPS caused a major GPS outage. Criminals can also jam GPS signals locally, given the commercial
availability of GPS jammers, and environmental factors such as sun spots also contribute to GPS disruptions. Out-of-
sync base stations dramatically increase the operator's OPEX. Further, if telecommunications regulations such as E911
requirements are violated, the operator may incur additional expenses of reporting outages and carrying out audits.
Holdover Requirements and Technologies
Holdover is achieved by equipping base stations transceivers with oscillators that temporarily "hold over" sync
signals. Holdover capability can range from several hours to several days depending on the quality of the BTS's
oscillator. Holdover requirements are not standard; they vary depending on the type, complexity, and operator'
requirements. LTE TDD networks have stringent timing requirement, + 1.5 microseconds.
17email:sanjay.yadav@mapyourtech.com
18. Timing Loop
For the reliable operation of synchronization network, there are usually two or more
reference signals used as active and standby signals for the clocks in hierarchical
master-slave synchronization network. When the active reference signal fails or
transmission link is disconnected, the clock reference signal will be switched to
standby signal. When timing signals are transferred via active/standby reference
transmission link, a timing loop may form, that is, a clock may receive the timing signal
sent from itself via a specific link.
When a timing loop is formed, clocks in the loop form a self-feedback loop, and after a
period of time, the frequencies of respective clocks will gradually deviate from the
reference clock frequency, resulting in the deterioration of signal quality.
So special consideration is required to prevent the forming and existing of timing loop
in synchronization network design and planning.
A timing loop is a situation where a portion of the normal timing distribution structure
inadvertently feed timing to itself. In a worst case scenario, a timing loop can cause a traffic
outage. Networks must be designed to avoid timing loops at all costs.
When designing a network, the designer must first work through the potential traffic paths of
all the timing signals and identify possible potential loop points. Once the location of these
critical points is known, a few different methods of preventing these loops can be used
18email:sanjay.yadav@mapyourtech.com
19. Timing loop…
. Two approaches are described here:
Create a table for each NE listing every potential timing source. NEs that may
potentially send looping timing signals must not be included. Timing signals from NE
sources not included in the table are ignored.
The timing source table includes a quality/priority ranking for each timing source. Timing
signals from better-quality/higher-priority sources are preferred to timing signals from
poorer-quality/lower-priority sources.
The highest quality timing source is given first priority. Secondary priority is given to the
alternative timing sources. These alternative sources are automatically used as backup
sources if the primary timing source goes down. Up to four levels of timing sources can
be defined for each NE. The NE automatically reverts to the highest quality timing
source currently available. This means that as higher-quality timing sources are
restored, the NE automatically gives preference to the highest-quality timing signal
received.
Each NE can automatically send a Do Not Use (DNU) message back to every other
direct source NE from which it receives a timing signal. This ensures that the source
NEs do not receive back their own timing signals from the current NE.
19email:sanjay.yadav@mapyourtech.com
20. Simple timing loop and prevention of timing loops through use of DNU messages
20email:sanjay.yadav@mapyourtech.com
21. Example of timing loop generation
Here each of the two external timing nodes (node with external timing) can be synchronized, either by is
external clock or via any of the 2 lines. In case of failure of the active external clock in timing node 1, this node
selects its fourth priority, which carries the timing generated by itself. This is a timing loop situation.
21email:sanjay.yadav@mapyourtech.com
22. QualityOrder Priority
Level Code
(within S1 byte)
Highest 1 G.811 (PRC) 0010
2 G.812T (SSU transit) 0100
3 G.812L (SSU local) 1000
4 G.813 (SEC) 1011
Lowest 5 Do not use1)
1111
Quality unknown 0000
1)
This signal should not be used for synchronization. It is automatically
transmitted in the backward direction of the port, which is selected as clock
reference. This is done to prevent synchronization loops.
22email:sanjay.yadav@mapyourtech.com
23. Timing Impairments
Jitter and Wander already have been described as any kind of phase noise or fluctuations of the recovered timing
signal along the time axis. The phase noise can be generated by the transmission system, in the clock recovery
circuits of an interface, and at the outputs of synchronization supply units (SSU).
Jitter and wander is described in time units such as seconds (seconds, microseconds, nanoseconds , picoseconds) ,
phase angle (radians) or unit interval (UI). The most common unit is the Unit Interval, which is equal to the pulse
period (reciprocal of the interface bit rate). For example, 1 UI at the DS-1 rate corresponds to (1 ÷ 1,544,000 b/s)
648 ns; therefore, a peak-to peak jitter of 0.1 UI at a DS-1 interface is the same as 64.8 ns.
Jitter tolerance requirements that apply to the input of Stratum 2, 3E, 3 and 4 clocks are given in ANSI T1.102. A
DS-1 timing output interface shall not generate more than 0.05 UI peak-to-peak jitter (per ANSI T1.101 Annex G).
The effect of transmission cables on wander is in the order of
• ~ 80 ps/km/°C for fiber optic cables
• ~ 725 ps/km/°C for metallic twisted pair cables
Time Interval Error (TIE) is the variation in time delay of a timing signal over a particular observation period
relative to an ideal timing signal (or a very high quality reference signal). If the timing signal has a fixed frequency
offset, the TIE will increase linearly over time with no upper bound – the longer the observation period the higher
the TIE. If the timing signal phase delay varies during the observation period it will have some maximum value, or
Maximum TIE (MTIE), during that period. MTIE is specified to ensure that slip performance is properly bounded
particularly during loss and rearrangement of reference timing sources
23email:sanjay.yadav@mapyourtech.com
24. Time Deviation (TDEV) is a measure of the expected time variation of a timing signal as a function of integration
time. It provides information about the spectral content of the timing signal’s phase noise. It is calculated from a
sequence of time error samples and is expressed in time units (usually nanoseconds). A constant frequency offset
does not affect TDEV. In the case of linear frequency drift (linear increase in frequency offset), TDEV is proportional
to the square of the observation period. TDEV gives more information on timing signal noise than MTIE.
MTIE and TDEV are specified as a function of measurement (observation) period because clocks have different
observed behavior depending on the observation period. As previously mentioned, the output circuits of all
telecommunications clocks use high quality quartz crystal oscillators to provide short-term stability. Crystal
oscillators age and drift over time and are sensitive to temperature variations so they are steered by atomic clock
generators (cesium or rubidium), which have very good long-term stability but relatively poor short-term stability.
The combination of a high quality crystal oscillator and atomic clock generator provides the necessary stability over
all observation periods.
24email:sanjay.yadav@mapyourtech.com
26. Troubleshooting Synchronization Issues
The following tips may be helpful when diagnosing synchronization issues:
Be careful with loopbacks. A local loopback placed on a source in the hierarchy can
cause a timing loop. In addition, a remote loopback towards a source on the hierarchy
of another NE can cause a loopback.
Synchronization alarms as defined in the Network Time Protocols (NTPs) can be
used to find synchronization-related problems. Other alarms that often accompany
synchronization problems include:
PDH port input and output buffer alarms
Loss of pointer alarms
Loss of frame alarms
AU and TU pointer justification events can be measured through performance
monitoring.
26email:sanjay.yadav@mapyourtech.com
28. The Network Elements (NE) within SDH networks have to be synchronized to a central clock.
A hierarchical structure of clock generators with different qualities is used to distribute the clock reference
signal through the entire network:
PRC
The high precision Primary Reference Clock (PRC), according to ITU-T recommendation G.811, builds up the
highest level of the synchronization hierarchy and provides clock reference signals for the NEs within the
network.
It should be redundant in the synchronization network.
SSU
The second level is represented by the Synchronization Supply Unit (SSU), according to ITU-T recommendation
G.812. It filters the incoming clock reference signal and provides the network with a high quality clock
reference signal in case of a loss of the PRC reference.
The SSU can be a separate equipment or part of a SDH NE.
Max. 10 SSU are allowed in a chain.
SEC
The third and last level of synchronization is realized by the SDH Equipment Clock (SEC) according to ITU-T
recommendation G.813.
It is normally part of the NE and provides the NE with an holdover capability for at least 24 hours.
Max. 20 SEC are allowed one after the other and max 60 SEC in a chain between two SSU or after a PRC.
28email:sanjay.yadav@mapyourtech.com
29. General principles Hierarchy of the synchronization clocks
Primary reference clock (PRC)
Frequency accuracy greater than 1 part in 10-11
Cesium tube
GPS receiver
Compliant to ITU-T Recommendation G.811
Synchronization supply unit (SSU)
Holdover mode : frequency drift lower than 2 x 10-10
/day
Compliant to ITU-T Recommendation G.812
SDH equipment slave clocks (SEC)
Holdover mode : frequency drift lower than 7 x 10-12
/minute
Frequency accuracy not greater than 4.6 ppm under free-running conditions
Compliant to ITU-T Recommendation G.813
29email:sanjay.yadav@mapyourtech.com
30. International Synchronization Standards
Clock designation
Proposed ITU-
T
reference
Free-run
accuracy
Holdover initial slip-rate
(max.)
Pull-in range Application
Stratum 1, PRS, PRC G.811 1.0 x 10-11 ≤1 Slip in 72 days NA Network Master
Stratum 2 G.812 Type II 1.6 x 10-8 1 slip per 14 days +/- 1.6 x 10-8 Stratum 2 BITS
ETSI
DE/TM-03017-4
G.812 Type I --- 1 slip in first 24 hours +/- 1.0 x 10-8 Type I SSU
Transit node clock (TNC) G.812 Type V NS 1 slip in first 24 hours NS TNC BITS, TNC SSU
Stratum 3E G.812 Type III 4.6 x 10-6 8 slips in first 24 hours +/- 4.6 x 10-6 Stratum 3E BITS
Local node clock (LNC) G.812 Type I NS 17 slips in first 24 hours NS LNC SSU
Stratum 3 G.812 Type VI 4.6 x 10-6 255 slips in first 24 hours +/- 4.6 x 10-6
Stratum 3 BITS,
Stratum 3 NE
SDH equipment clock (SEC) G.813 Option 1 4.6 x 10-6 1643 slips in first 24 hours +/- 4.6 x 10-6
SDH
Equipment Clock
SONET
minimum clock (SMC)
G.813 Option 2 20 x 10-6 3520 slips in first 24 hours +/- 20 x 10-6
SONET
Equipment
Stratum 4 NA 32 x 10-6
22118 slips in
first 24 hours
+/- 32 x 10-6 Stratum 4 NE, CPE
30email:sanjay.yadav@mapyourtech.com
In ITU-Recommendation G.811 (Timing Characteristics of Primary Reference Clocks) a network clock stability of 1 x 10 E-11 for the Primary Reference Clock (RPC) is recommended. This accuracy is derived from 1 acceptable slip in a 2 MBit/s transmission in an observation time of 72 days. 1 (frame) = 125 us 125 us / 72 d x 24 h/d x 3600 s/h = 2 x 10 E –11 or+-1 x 10 E-11 This clock stability can be generated by atomic clocks only! NA = Not Applicable NS = Not Specified NE = Network Element CPE = Customer Premises Equipment