The document describes the design of a digital stopwatch circuit using integrated circuits. The circuit uses a pulse generator to create a 1Hz clock signal, a counter integrated circuit to count the pulses and track seconds and decades, and display driver integrated circuits to show the time on 7-segment displays. With minor modifications, the circuit could be adapted for applications like photo counting, people counting, timers, and alarms. Building the circuit provided learning experiences in pulse generation, troubleshooting circuits, using displays and drivers, and soldering circuits on PCBs.
Digital clock (mod counters)using DSCH (DIGITAL SCHEMATIC) by Gaurav RaikarGauravRaikar3
The DSCH program is a logic editor and simulator. DSCH provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design and validation of complex logic structures.
Modulus counters, or simply MOD counters, are defined based on the number of states that the counter will sequence through before returning back to its original value.
Digital clock (mod counters)using DSCH (DIGITAL SCHEMATIC) by Gaurav RaikarGauravRaikar3
The DSCH program is a logic editor and simulator. DSCH provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design and validation of complex logic structures.
Modulus counters, or simply MOD counters, are defined based on the number of states that the counter will sequence through before returning back to its original value.
A digital clock is a type of clock that displays the time digitally (i.e. in numerals or other symbols), as opposed to an analog clock, where the time is indicated by the positions of rotating hands.
Registers - Serial in serial out, Serial in Parallel out, Parallel in serial out, Parallel in Parallel
out registers, Bidirectional shift registers, universal shift registers.
Counters - Synchronous and asynchronous counters, UP/DOWN counters, Modulo-N
Counters, Cascaded counter, Programmable counter, Counters using shift registers, application
of counters.
It Defines what is Programmable Logic Array(PLA) also explains it in easy wording with syntax and Example...
It also cover what is Combinational & Sequential Logic Circuit and the Difference b/w these both. :)
UNIT III BASEBAND TRANSMISSION
Properties of Line codes- Power Spectral Density of Unipolar / Polar RZ & NRZ – Bipolar NRZ - Manchester- ISI – Nyquist criterion for distortionless transmission – Pulse shaping – Correlative coding - Mary schemes – Eye pattern – Equalization
Full custom digital ic design of priority encoderVishesh Thakur
The enhancement on a simple encoder circuit, in terms of handling all possible input combinations has lead to the development of special circuits known as Priority Encoders. These circuits facilitate in compressing several inputs into numerous small outputs. The quality feature of these encoders is encoding the inputs just to make sure that only highest order lines are encoded. The result or output of the priority encoder should be a binary representation of ordinal numbers articulated in BCD format. In addition, these also manage interrupt requests through high priority request. Whenever there is more than one active input at same time, then highest priority input will be given more preference. One can find priority encoders in standard or normal IC form such as TTL 74LS147 or TTL 74LS148. Basically, the former encodes 9 datelines to 4 lines as in (8-4-2-1) BCD. And the latter expresses 8 datelines to 3 lines as in 4-2-1 (octal) binary. In order to provide octal expansion with no requirement of external circuitry, one needs Cascading Circuitry. Data inputs and data outputs are active even at low levels. Priority encoders find wide range of applications as in keyboard encoding, range selection,
Bit level encoding, code converters and generators.
A digital clock is a type of clock that displays the time digitally (i.e. in numerals or other symbols), as opposed to an analog clock, where the time is indicated by the positions of rotating hands.
Registers - Serial in serial out, Serial in Parallel out, Parallel in serial out, Parallel in Parallel
out registers, Bidirectional shift registers, universal shift registers.
Counters - Synchronous and asynchronous counters, UP/DOWN counters, Modulo-N
Counters, Cascaded counter, Programmable counter, Counters using shift registers, application
of counters.
It Defines what is Programmable Logic Array(PLA) also explains it in easy wording with syntax and Example...
It also cover what is Combinational & Sequential Logic Circuit and the Difference b/w these both. :)
UNIT III BASEBAND TRANSMISSION
Properties of Line codes- Power Spectral Density of Unipolar / Polar RZ & NRZ – Bipolar NRZ - Manchester- ISI – Nyquist criterion for distortionless transmission – Pulse shaping – Correlative coding - Mary schemes – Eye pattern – Equalization
Full custom digital ic design of priority encoderVishesh Thakur
The enhancement on a simple encoder circuit, in terms of handling all possible input combinations has lead to the development of special circuits known as Priority Encoders. These circuits facilitate in compressing several inputs into numerous small outputs. The quality feature of these encoders is encoding the inputs just to make sure that only highest order lines are encoded. The result or output of the priority encoder should be a binary representation of ordinal numbers articulated in BCD format. In addition, these also manage interrupt requests through high priority request. Whenever there is more than one active input at same time, then highest priority input will be given more preference. One can find priority encoders in standard or normal IC form such as TTL 74LS147 or TTL 74LS148. Basically, the former encodes 9 datelines to 4 lines as in (8-4-2-1) BCD. And the latter expresses 8 datelines to 3 lines as in 4-2-1 (octal) binary. In order to provide octal expansion with no requirement of external circuitry, one needs Cascading Circuitry. Data inputs and data outputs are active even at low levels. Priority encoders find wide range of applications as in keyboard encoding, range selection,
Bit level encoding, code converters and generators.
1 PageAlarm Clock Design Using PIC18F45E.docxmercysuttle
1 | Page
Alarm Clock Design Using PIC18F45
ELEC 310
Submitted by: Maria AlKadhem
Contents
Detailed Specification: 2
Input: 2
LCD display: 2
Microcontroller: 4
Clocking Choice 5
Working theory: 5
Pin out of the device: 6
LCD interfacing: 6
Final comments: 7
Introduction:
The major purpose of the project is to get familiar with the PIC18FXX series microcontrollers. We are ought to design an alarm clock which will be able to display the time on an LCD as well as we can give input through the dip switches. The dip switches will be able to increment the hours and minutes. We will go through the detailed design a bit later in the document.
In order to implement the alarm clock we had to make external circuitry as well which was necessary for the following functions.
· Input
· Buzzer
· Display at LCD.
The pith of the alarm clock is to run the clock of MCU in counter mode. When the counter is set the MCU starts counting till the number and then when the threshold is generated the output signal is used to start a buzzer. At the same time there is an LCD used in the circuit which will be responsible for displaying the three things.
· Current time.
· Alarm time
· Remaining time.
For setting the alarm there are two DIP switches. One for adjusting the hours and other is used for adjusting the minutes. For clearing the alarm we simply will be pressing both at a time. The corresponding ports of the MCU will be used in the INPUT mode.Detailed Specification:
Let’s discuss the detailed specifications of this device.Input:
The input of the alarm clock consists of two DIP switches. One switch will be used for adjusting the hours. The second switch will be used for the adjustment of the minutes.
Each time a button is at high logic there will be an increase in the corresponding variable of alarm.
When both of the buttons are pressed there will be a reset of clock making the value to 0.0. It will be the off state of the clock as well.LCD display:
We are using a 16x 2 display screen which is of 16 pin. The device is TRULY LCD MODULE MTC-C162DPRN-2N. It is capable of displaying 16 characters in 2 lines at a time. Making overall 32 characters.
The pin Details are given below for the LCD module.
Pin NO. Symbol Level Description
1 VSS 0V Ground
2 VDD 5.0V Supply voltage for logic
3 VO --- Input voltage for LCD
4 RS H/L H : Data, L : Instruction code
5 R/W H/L H : Read mode, L : Write mode
6 E H, H →L Chip enable signal
7 DB0 H/L Data bit 0
8 DB1 H/L Data bit 1
9 DB2 H/L Data bit 2
10 DB3 H/L Data bit 3
11 DB4 H/L Data bit 4
12 DB5 H/L Data bit 5
13 DB6 H/L Data bit 6
14 DB7 H/L Data bit 7
15 NC --- No Connection
16 NC --- No Connection
The VSS is kept at ground.
Last 2 pins are not included in the design they are not used at all.
Microcontroller:
The selected microcontroller is PIC18F452 because of the following reasons.
This powerful 10 MIPS (100 nanosecond instruction execution) yet easy-to-program (only 77 single word instructio ...
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Monitoring Java Application Security with JDK Tools and JFR Events
Digital stop watch
1. DIGITAL STOP WATCH
- K. Sai Malleswar
Referances;
1. www.diy-electronic-projects.com
2. CONTENTS
1. Aim
2. Components
3. Circuit description (proposed)
i. Pulse generator
ii. Counter
iii. Display unit
iv. Modifications*
v. Schematic of proposed circuit
vi. Schematic of modified circuit
4. Details of ICs [ from Datasheets]
5. Applications of the circuit
6. Project details
i. Experiences of the project work
3. 1. AIM
Aim: To make a digital stop watch circuit that can count from 0 to 99 seconds,
which can also be used for different applications like photo counter, person
counter, count down timer, alarm clock etc. with small modifications.
2. COMPONENTS USED
1. ICs:
i. CD4060BM – 14 stage ripple carry binary counter - 1
ii. CD4040BM – 12 stage ripple carry binary counter - 1
iii. NE555 – Timer - 1
iv. MC14518B - BCD counter -1
v. MC14511B - BCD to seven segment display drivers - 2
2. Other components:
i. 1 kilo ohm resistors – 16, 10 kilo ohm resistors - 2, 1 mega ohm resistor - 1,
330 ohm resistor -1,220 ohm resistor -1
ii. 100 kilo ohm potentiometer-1
iii. On/off switches- 2
iv. 4.2 megahertz crystal-1
v. 1N4007 diodes– 2
vi. 22pf capacitors – 2, 10uf capacitor-1, 0.01uf capacitor-1
vii. Common anode 7 segment displays - 2
viii. +5V DC power supply
ix. Bread board - 1
4. 3. CIRCUIT DESCRIPTION
The circuit can be mainly divided into three parts. One is generator which produces
the pulse of the desired frequency. The other parts are the counter that does the
actual counting of the seconds and the display unit.
i. PULSE GENERATOR:
The generator of the circuit comprises of the integrated circuits CD4040CM and
CD4060CM. We use a crystal which oscillates at a frequency of 4,194,304 Hz. It is
obvious that this frequency is completely useless, as it is too big to be used as it is
to our circuit. What we should is divide this frequency, in a way that in its final
form, the pulse will have a frequency of 1Hz, which is the desirable frequency.
Initially we use the integrated CD4060, which divides the imported frequency in its
input, by forces of 2. As we can see on the integrated circuit the outputs are
marked as Q4, Q5,…,Qn. By importing a pulse in the CLK input of the 4060, with
a frequency f Hz, we take out of output Qn, a signal which has a frequency equal to
f/2n. So, by exporting the signal out of Q14, knowing that the imported signal has
a frequency of 4,194,304 Hz, we take a signal, which has a frequency of 256Hz.
By importing this signal, to 4040 and by exporting the signal through Q8 we
have finally taken an inverted signal, at the frequency of 1Hz. The fact that the
signal is inverted, doesn‘t affect the proper function of our circuit. This inversion
just causes the circuit to be triggered with a logical 0.
By putting a LED on the same output, we have a visual of the counting, as in each
positive pulse the diode polarizes positively, and a current passes through it.
ii. COUNTER:
The signal of 1Hz, which we have taken from the generator, is imported to a BCD
counter MC14518. This integrated circuit adds a logical 1 at each pulse, on its
output. The MC14518 is virtually divided into two segments. One counts the units
of the seconds, while the other the decades. The generators pulse is imported to the
part which counts the units. This is very logical, as we want in each second the
number of the display to be raised by 1.
5. On the other hand, we want the first display to raise by 1, every 10 seconds. This is
why, we ground the CLK input, and we use the signal of Q3 to the CKE input.
By using this means, we make sure that the first display will be triggered, only
when we have a decreasing signal on Q3; that is, only when the signal drops from
logical 1 to logical 0.The first display increments every 10 seconds, which means
that after 9 on the second display (1001 on the output of the BCD counter) the first
display must be set to zero, while the first must be set to +1. That is that from 1001
to 0000, and we have a descending pulse, as the last digit descends from logical 1
to logical 0 and triggers the BCD counter of the decades. When the decades display
becomes 9 then the circuit goes to the next state, which is zero, and the counting
begins once more.
iii. DISPLAY UNIT:
The integrated circuits MC14511 are BCD to 7 segment drivers. As its name
clearly state, their sole purpose is to translate the BCD information of MC14518, to
a code understandable by the 7 segment displays. The inputs LE, BL‘ and LT‘ are
used to test the LEDs of the display and pulse-modulate the brightness of the
display. In this case we these inputs to logical 0, as we don‘t need them. The LE
input (Latch Enable) is used to keep the number of the displays while the pulse still
runs. It is a HOLD function similar to the one of the modern stopwatches. In
addition, at any given moment we can restart the counting, by pressing the reset
switch. By this means we set the RST input of the MC14518 to logical 1, which
resets the counting to 0000.
iv. MODIFICATIONS:
The circuit which we described above for the 1Hz pulse generation using crystal of
resonant frequency 4.2 MHz is accurate than any other pulse generators. But the
crystal was not obtained. So we designed different 1 Hz pulse generating circuits.
Finally the circuit using NE555 could satisfy the requirements of the project. The
circuit has been tuned exactly tuned to 1Hz by changing the potentiometer‘s
resistance. The comparison has been made by blinking an led with 1Hz clock pulse
on digital trainer kit and blinking another led with the pulse produced from the
circuit designed using NE555. The 1Hz pulse generated has been given as clock
input to the second BCD counter of MC14511.
8. 4. Details of ICs used
1. MC14518B:
The MC14518B dual BCD counter and the MC14520B dual binary counter are
constructed with MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Each consists of two identical, independent, internally
synchronous 4–stage counters. The counter stages are type D flip–flops, with
interchangeable Clock and Enable lines for incrementing on either the positive–
going or negative–going transition as required when cascading multiple stages.
Each counter can be cleared by applying a high level on the Reset line. In addition,
the MC14518B will count out of all undefined states within two clock periods.
These complimentary MOS up counters find primary use in multi–stage
synchronous or ripple counting applications requiring low power dissipation and/or
high noise immunity.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0Vdc to 18Vdc
• Internally Synchronous for High Internal and External Speeds
• Logic Edge–Clocked Design — Incremented on Positive Transition
Of Clock or Negative Transition on Enable
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
Pin diagram:
9. 2. MC14511B:
The MC14511B BCD–to–seven segment latch/decoder/driver is constructed
with complementary MOS (CMOS) enhancement mode devices and NPN bipolar
output drivers in a single monolithic structure. The circuit provides the functions
of a 4–bit storage latch, an 8421 BCD–to–seven segment decoder, and an output
drive capability. Lamp test (LT), blanking (BI), and latch enable (LE) inputs are
used to test the display, to turn–off or pulse modulate the brightness of the display,
and to store a BCD code, respectively.
It can be used with seven–segment light–emitting diodes (LED),
incandescent, fluorescent, gas discharge, or liquid crystal readouts either
directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display driver,
computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses.
• Low Logic Circuit Power Dissipation
• High–Current Sourcing Outputs (Up to 25 mA)
• Latch Storage of Code
• Blanking Input
• Lamp Test Provision
• Lamp Intensity Modulation Capability
• Time Share (Multiplexing) Facility
• Supply Voltage Range = 3.0 V to 18 V
Pin diagram:
10. 3. CD4040BM and CD4060BM:
These are 12 staged and 14 staged ripple carry binary counters respectively. The
Counters are advanced one count on the negative transition of each clock pulse.
The counters are set to zero state by a logical ‗1‘ at the reset input independent of
clock.
Pin diagrams:
CD4040BM:
CD4060BM:
11. 4. NE555:
The NE555 IC has three operating modes:
1. Mono stable mode: in this mode, the 555 functions as a "one-shot".
Applications include timers, missing pulse detection, bounce free switches,
touch switches, frequency divider, capacitance measurement, pulse-width
modulation (PWM) etc.
2. Astable - free running mode: the 555 can operate as an oscillator. Uses
include LED and lamp flashers, pulse generation, logic clocks, tone
generation, security alarms, pulse position modulation, etc.
3. Bi-stable mode or Schmitt trigger: the 555 can operate as a flip-flop, if the
DIS pin is not connected and no capacitor is used. Uses include bounce free
latched switches, etc.
Pin diagram:
12. 5. Applications of the circuit
The main purpose of the circuit is to use it as a stop watch that can be used in
organizing athletics, quizzes etc. With small modifications, the circuit can be used
for many counting purposes.
The flip-flops in the counter MC14518 are edge triggered. So if we give a single
pulse, the count increments by 1. So if we replace 1Hz pulse generator circuit with
a photo sensor, the count increments by 1 only when a pulse is received. So the
circuit can be used as photo counter. It can be kept inside a table‘s desk. Whenever
the desk is opened, the count increments by 1.So a person can find how many
times the table has been opened in his absence and reset the counter.
The circuit can also be used as person counter with the help of two IR sensors.
One is to manage the count of the persons. Other is to find, whether the person is
entering the room or leaving. When a person enters or leaves the room, he will cut
the light ray produce by IR leds. So the count increments by 1, when a person
enters the room and decrements by 1, when a person leaves the room. It can be
reset, whenever it is required.
If we replace up counter with down counter, it can be used as countdown timer or
alarm clock by attaching a buzzer for sounding.
If the 1Hz pulse generator circuit is replaced with a Pressure sensor, the circuit can
be used for counting the number of persons walked through a way. This can made
useful for practical purposes by increasing the no. of counters and seven segment
displays, thus increasing the maximum possible count.
13. 6. PROJECT DETAILS
i. Experiences of the project work:
1. We searched for the crystal of 4.2 MHz in many electronic shops, since it
is the most accurate pulse generator. We could not find it.
2. So, we started designing different 1Hz pulse generator circuits. We could
learn troubleshooting the circuits while implementing each on the bread
board and testing for the accuracy of the output.
3. We could understand the basic circuit used in manufacturing stopwatches,
counters, digital clocks etc.
4. We could learn using Seven Segment displays and using their driver ICs
for displaying digital data.
5. We made the schematic of the 1Hz Pulse generator using ―PSPICE‖
software.
6. We could learn Soldiering electronic circuits on the General Purpose PCB
by making a proper floor plan of the circuit.
CONCLUSION:
The project of making ―DIGITAL STOP WATCH‖, which can count from 0 to 99
seconds and has Hold and Reset capabilities has been completed. The circuit has
been implemented on bread board and soldiered on General Purpose PCB.