This document presents a digital wave formulation (DWF) method for solving the quasi-static partial element equivalent circuit (PEEC) method in the time domain. The standard PEEC model is transformed into a wave digital network by using wave variables and defining wave digital circuit elements corresponding to inductors, capacitors, resistors, sources, and connections. This allows the PEEC model to be solved as a wave digital network using a digital wave simulator (DWS). A numerical example compares the proposed DWF-PEEC solver to a standard SPICE solver, showing the DWF-PEEC method provides accurate results with significant speed-up in computation time.

1. Digital Wave Formulation of Quasi-Static Partial
Element Equivalent Circuit Method
Piero Belforte
Independent Researcher
Via G. C. Cavalli 28bis, 10138 Turin, Italy
Email: piero.belforte@gmail.com
Luigi Lombardi, Daniele Romano and Giulio Antonini
Dipartimento di Ingegneria Industriale
e dell’Informazione e di Economia
Universit`a degli Studi dell’Aquila
Via G. Gronchi 18, 67100, L’Aquila, Italy,
Email: giulio.antonini@univaq.it
Abstract—This paper presents a digital wave formulation
(DWF) of the quasi-static Partial Element Equivalent Circuit
formulation. Through the use of a pertinent change of variables
and the choice of a specific implementation of PEEC cell elements
in the Digital Wave domain, the standard PEEC model is
transformed into and solved as a wave digital network. The
example reported shows the accuracy and the significant speed-
up of the proposed DWF-based PEEC solver when compared to
the standard Spice solution.
I. INTRODUCTION
One well-known approach for generating accurate circuit
models for 3-D electromagnetic structures is the partial el-
ement equivalent circuit (PEEC) approach [1]. The PEEC
method is based on the mixed potential integral equation
(MPIE) and the continuity equation. It provides a circuit
interpretation of the electric field integral equation (EFIE)
and continuity equation [2] in terms of partial elements,
namely resistances, partial inductances and coefficients of
potential. Hence, the resulting equivalent circuit can be directly
embedded in a circuit environment like SPICE-like circuit
solvers [3] and the entire problem can be described by means
of the circuit theory and solved in both the time and frequency
domain. Time domain solutions are especially advantageous
and the unique possibility, if there are nonlinearities in the
circuit environment. Over the years, several improvements of
the PEEC method have been performed allowing to handle
complex problems involving both circuits and electromagnetic
fields [1], [4]–[14].
Introduced originally by Fettweis [15], wave digital filters
(WDFs) and scattering methods have been widely used for
numerical simulations [16] and applied to numerical methods
quite popular in the community of applied electromagnetics.
In particular, they have been applied to transmission lines and
their basic idea is strictly related to the the Transmission Line
Matrix (TLM) method [17], [18]. Starting from the mid 70’s
several generations of circuit simulation tools based on DWF
have been developed and applied mainly for the state-of-art
signal and power integrity applications in the field of high-
speed digital systems [19]–[21]. Despite its generality, the
digital wave formulation (DWF) has been mainly applied to
differential methods, where the interactions are local leading
to sparse matrices. Aim of this work is to apply DWF to
integral-equation based techniques. Among the others, the
PEEC method, especially for its capability to translate an elec-
tromagnetic problem into a circuit form, is the best candidate
to be combined with the DWF method.
The paper is organized as follows. Section II briefly sum-
marizes the PEEC method. The wave digital elements are
introduced in Section III in both the scalar and multidi-
mensional case. The resulting PEEC-digital wave simulator
(PEEC-DWS) is briefly described in Section IV. A numerical
example is presented in Section V where the PEEC-DWS
method is compared with a standard Spice solver in terms
of accuracy and cpu-time requirements. The conclusions are
drawn in Section VI.
II. BASIC PEEC FORMULATION FOR CONDUCTIVE
MATERIALS
The standard PEEC method is based on the equation of the
electric field and the continuity equation. Using a pertinent
spatial discretization of currents flowing in conductors and di-
electrics and charges located on their surfaces, the application
of the Galerkin’s process allows to identify topological entities,
namely nodes and branches, and equivalent circuit elements.
Figure 1 shows an example of PEEC circuit where the electric
field coupling is represented in terms of current controlled
current sources (CCCS) and the magnetic field coupling in
terms of current controlled voltage sources (CCVS).
The enforcement of Kirchoff Voltage Law (KVL) and
Kirchoff Current Law (KCL) leads to the following set of
ordinary differential equations in the MNA form:
C
𝑑x(𝑡)
𝑑𝑡
= −Gx(𝑡) + Ku(𝑡) (1)
where
C =
[
0 L 𝑝
C 𝑠 0
]
(2a)
G =
[
A R
G𝑙𝑒 −A 𝑇
]
(2b)
K =
[
ℐ 0
0 ℐ
]
(2c)
x(𝑡) = [𝜙(𝑡) i(𝑡)]
𝑇
(2d)
u(𝑡) =
[
−v 𝑠(𝑡)
i 𝑠(𝑡)
]
. (2e)
where A is the connectivity matrix, L 𝑝 is the partial in-
ductance matrix, C 𝑠 = P−1
is the short circuit capacitance
matrix, R the resistance matrix, G𝑙𝑒 is the lumped memoryless
elements matrix.

2. 1
𝑃11
𝑅1 𝐿 𝑝11
𝐼 𝐿1
+
−
𝐼1
1
𝑃22
𝑅2 𝐿 𝑝22
𝐼 𝐿2
+
−
𝐼2
1
𝑃33
𝐼3
+ +
𝑠𝐿 𝑝,21 𝐼 𝐿1𝑠𝐿 𝑝,12 𝐼 𝐿2 𝑉01 𝑉02
321
Fig. 1. Example of a PEEC circuit.
III. WAVE DIGITAL ELEMENTS AND CONNECTIONS
A. Wave variables
For a port with voltage v and a current i, voltages waves
are defined by
𝑎 = 𝑣 + 𝑖𝑅0 (3a)
𝑏 = 𝑣 − 𝑖𝑅0 (3b)
It is straightforward to extend wave digital filtering pric-
niples to the vector case. For a 𝑞-component vector one
port element voltage v = [𝑣1, 𝑣2, ⋅ ⋅ ⋅ , 𝑣 𝑞] 𝑇
, and current
i = [𝑖1, 𝑖2, ⋅ ⋅ ⋅ , 𝑖 𝑞] 𝑇
, it is possible to define wave variables
a and b by
a = v + iR0 (4a)
b = v − iR0 (4b)
B. Wave digital elements
We will now present the wave digital equivalents of the
circuit elements mentioned in the previous Section II, namely
inductances, capacitance, resistances, current sources and volt-
age sources.
Under the bilinear transform, the steady state equation for
an inductor becomes
ˆ𝑣 =
2𝐿
𝑇
(
1 − 𝑧−1
1 + 𝑧−1
)
ˆ𝑖 (5)
or, in the discrete-time domain
𝑣 (𝑛) + 𝑣 (𝑛 − 1) =
2𝐿
𝑇
(𝑖 (𝑛) − 𝑖 (𝑛 − 1)) (6)
If we apply the definition of wave variables (3), we get, in the
time domain
𝑎(𝑛) + 𝑏(𝑛) + 𝑎(𝑛 − 1) + 𝑏(𝑛 − 1) =
=
2𝐿
𝑅 𝐿 𝑇
(𝑎(𝑛) − 𝑏(𝑛) − 𝑎(𝑛 − 1) + 𝑏(𝑛 − 1) (7)
where 𝑅 𝐿 is the reference resistance for the inductance 𝐿.
If we make the choice
𝑅 𝐿 =
2𝐿
𝑇
(8)
then (7) simplifies to
𝑏 𝐿 (𝑛) = −𝑎 𝐿(𝑛 − 1) (9)
Hence, the input wave 𝑎 undergo a time-step delay 𝑇 and sign
inversion before it is output as 𝑏.
The construction of the wave digital one-ports correspond-
ing to the resistor and capacitor is similar. It leads to
𝑏 𝐶 (𝑛) = 𝑎 𝐶(𝑛 − 1) (10)
for the capacitor, assuming a reference resistance 𝑅 𝐶 = 𝑇/2𝐶
and
𝑏 𝑅 (𝑛) = 0 (11)
for the resistance, assuming a reference resistance 𝑅 𝑅 = 𝑅.
C. Vector wave digital elements
In PEEC models, magnetic and electric coupling is de-
scribed by full matrices, namely partial inductance matrix L 𝑝
and short circuit capacitance matrix C 𝑠. In vector form their
constitutive relations read
v 𝐿(𝑡) = L 𝑝
𝑑
𝑑𝑡
i 𝐿(𝑡) (12a)
i 𝐶(𝑡) = C 𝑠
𝑑
𝑑𝑡
v 𝐶(𝑡) (12b)
Partial inductances can be discretized through the use of
trapezoid rule applied directly to the vector equation (12a);
in terms of wave variables defined by (4), we get
b 𝐿(𝑛) = −a 𝐿(𝑛 − 1) R 𝐿 =
2L 𝑝
𝑇
(13)
which is the direct generalization of (9). Similarly, for the
short circuit capacitances, we get
b 𝐶(𝑛) = a 𝐶(𝑛 − 1) R 𝐶 = 𝑇 (2C 𝑠)
−1
=
𝑇
2
P (14)
Finally, for the resistances, we have
b 𝑅(𝑛) = 0 R 𝑅 = R (15)
IV. DIGITAL WAVE SIMULATOR
Several approaches can be adopted to convert a PEEC model
into a digital wave network by the Digital Wave Simulator
(DWS) [21]–[23]. For the sake of simplicity, a simple 3-node
PEEC model is considered as described in Fig. 2 where the
mutual inductances and capacitances are not shown to simplify
the explanation.
The 2-port inductors are converted into a series adaptor with
a grounded inductor connected at its third port. As known, this
𝑇/2-long shorted stub model is numerical equivalent to the
trapezoidal rule of integration. In a similar way, the grounded
capacitors are mapped into a one-port 𝑇/2 long open stub
model. The connecting nodes are implemented by 2 or 3-ports

3. parallel adaptors. The resulting wave model shown in Fig. 4
can be affected by the delay free loop (DFL) issue unless
proper values of port reference impedance are chosen.
Starting from the source and termination ends, the port
impedances are defined in order to avoid reflections and to
open the DFLs. This implies an order of reference impedance
calculation starting from the ends until a root element (AS2)
is found. In a similar way the wave calculation is scheduled
starting from the leaf elements until the root is found for the
incident wave and then back from the root to the leafs for the
reflected wave. In case of residual DFLs after the scheduling,
the remaining network will be automatically solved using a
sparse matrix solver. DWS implements a calculation scheduler
following a rule similar to that shown in Fig. 2.
𝑣 𝑠
𝑅 𝑠
𝑁0
𝐿1
𝑁1
𝐶1
𝐿2
𝑁2
𝐶2
𝐿3
𝐶3
𝑁3
𝑅 𝑇
Fig. 2. Simple lossless PEEC model.
𝑣 𝑠
𝑅 𝑠
𝑁1
𝐴𝑆1
𝐿1
𝑁1
𝐶1
𝐴𝑆2
𝐿2
𝑁2
𝐶2
𝐴𝑆3
𝐿3
𝑁3
𝐶2
𝑅 𝑇
Fig. 3. DWS converted PEEC model.
𝑁0
𝑣 𝑠
2
𝐴𝑆1
T
−1
𝑁1
T
𝐴𝑆2(root)
backward
forward
T
−1
𝑁2
T
𝐴𝑆3
T
−1
𝑁3
0
T
Fig. 4. Wave digital network for the PEEC model in Fig. 2.
V. NUMERICAL RESULTS
As a first application example of DWS simulation of a
PEEC model a simple microstrip has been chosen as test
configuration. The microstrip cross-section is shown in Fig.
5. The total length of the microstrip is 𝐿 = 116 mm and
the relative permittivity of the dielectric is 4.9. The other
dimensions of the cross-section are in Fig. 5. The PEEC model
of this microstrip has been extracted by using the 3Dpeec
application [24] that analyses 3D planar structures, as typically
found in multilayer printed circuits boards (PCB), and creates
an electrical equivalent circuit that can be simulated with
Spice-like electrical simulators, including DWS. The reference
structure managed by 3Dpeec is constituted by three different
layers of homogeneous and isotropic dielectric material having
arbitrary thickness; inside each layer the user can add, in
Fig. 5. Microstrip cross-section.
any position, rectangular or polygonal conductors. On both
the top and bottom faces of the PCB two ideal endless and
perfectly conductive ground planes can be placed. Conductive
areas are mapped into a mesh of cells and the capacitive and
inductive (self and mutual) contribution respect to infinite and
respect to each other cell of the structure are evaluated. These
contributions together form an equivalent circuital model that
is described a Spice subcircuit.
The microstrip is divided into 50, 100, 2x100 and and
2X200 elementary cells on the microstrip, each each 2.32
mm, 1.16 mm, 1.16mm long respectively. A radius of 50
mm has been chosen to include all the electric and magnetic
couplings of a cell with the others. Outside this spherical
region, the coupling is neglected. A lossless situation is
analyzed. Once defined, the physical structure is converted
into the Spice-like netlist in a fraction of a second using
a Intel Quad-Core i7-2630QM 2.00 GHz CPU. The output
netlist contains only the magnetic coupling coefficients 𝐾 and
the coupling capacitances exceeding a user-defined minimum
value. A minimum value of 1e-5 and 1e-5 pF have been set
for the magnetic coupling coefficients and for capacitances,
respectively. This model is stressed using a free oscillation
configuration to pinpoint numerical issues like stability and
solver losses. The microstrip is driven by a voltage ramp with
rise time 100 ps, 𝑅 𝑠 = 0 Ω and terminated on a 𝑅 𝑇 = 1𝑒10 Ω
resistance. To achieve comparable accuracies, Spice option
TMAX (maximum allowable time step) was set equal to DWS
TSTEP (200fs). Persistent oscillatory results are shown in Fig.
6 and are almost undistinguishable as confirmed by the error
shown in Fig. 7 for the case of a the microstrip divided using
50 cells.
The performances of the standard PEEC-Spice solution and the
proposed PEEC-DWS solver are reported in Table I exhibiting
an increasing speed-up of the DWS solver with the complexity
of the equivalent circuit compared with the Ngspice [25]
solution.
TABLE I
PERFORMANCE COMPARISON OF PEEC-SPICE AND PEEC-DWS
N cells Ngspice [𝑠] DWS [𝑠] Speed-up
50 335 36 9.3
100 3580 238 15
2x100 11400 456 25
2x200* 5940 131.8 45
* with reduced simulation time window 0-10 ns
VI. CONCLUSIONS
In this paper, a digital wave formulation of the Partial Ele-
ment Equivalent Circuit has been presented. The use of wave

4. 90 92 94 96 98 100
Time [ns]
-2
0
2
4
6
8
Outputvoltage[V]
PEEC-DWS
PEEC-Ngspice
Fig. 6. Output voltage of the microstrip (50 PEEC cells).
90 92 94 96 98 100
Time [ns]
-0.02
-0.01
0
0.01
0.02
0.03
Error[V]
Fig. 7. Error on the output voltage of the microstrip (50 PEEC cells).
variables instead of the standard voltages and currents and the
application of the bilinear transformation allows to generate
a wave digital network. A pertinent choice of the reference
resistances for resistances, inductances and capacitances and
an appropriate scheduling of the wave updating equations,
leads to a semi-explicit scheme implemented by DWS which
exhibits high stability, accuracy and significant speed-up when
compared to the standard Spice analysis. Furthermore, the
DWF is completely compatible with delayed PEEC models.
Several DW implementation schemes can be conceived for
the basic PEEC cell regarding partial inductance integration
methods and the use of controlled sources to model couplings.
Coupling delays can be also added to the basic DW cell as well
lossy elements. Each implementation scheme has a significant
impact on accuracy, stability and size of the residual matrix.
These alternatives and their impact on simulation results will
be presented in forthcoming works.
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