Frequency domain Vector Fitting (VF) is a well known technique to generate circuital models of a spatially discretized lossy transmission lines from theoretical formulation of losses. The sub-picosecond time steps required by multi-gigahertz bandwidths and short transmission lines included in the models, determine long Spice simulation times. A 100X speedup can be gained using the Digital Wave Simulator (DWS) instead of Spice. DWS processes the waves of a Digital Network built up connecting together scattering blocks (circuit elements, nodes and S-parameter multi-ports) coming from a Spice-like description. Being a DSP wave processor instead of a classical nodal equations solver, DWS is computationally very fast and numerically stable. Comparisons with commercial simulators like Microcap11 and CST Cable Studio show a good matching of results. A further 10-100X simulation speedup is obtained if Piecewise-Linear Fitting (PWLF) is used to describe the time-domain behaviors of Scattering Parameters. Single or multiple cell Behavioral Time Models (BTM) can be extracted by PWLF from TDR/TDT measurements and processed by DWS fast convolution algorithms. A setup de-embedding can be performed by pwl breakpoints optimization to fit actual measurements. A RG58 coaxial cable is analyzed and its VF-derived eye-diagrams are compared to PWLF measurement-derived results. At multi-gigabit rates significant differences, due to cable physical implementation effects, are observed. The modeling/simulation alternatives (VF/Spice, VF/DWS and PWLF/DWS) are compared together and the advantages of PWLF/DWS in term of simplicity, stability and speed are highlighted.
Digital Wave Simulation of Lossy Lines for Multi-Gigabit ApplicationsPiero Belforte
Frequency domain Vector Fitting (VF) is a well known technique to generate circuital models of a spatially discretized lossy transmission lines from theoretical formulation of losses. The sub-picosecond time steps required by multi-gigahertz bandwidths and short transmission lines included in the models, determine long Spice simulation times. A 100X speedup can be gained using the Digital Wave Simulator (DWS) instead of Spice. DWS processes the waves of a Digital Network built up connecting together scattering blocks (circuit elements, nodes and S-parameter multi-ports) coming from a Spice-like description. Being a DSP wave processor instead of a classical nodal equations solver, DWS is computationally very fast and numerically stable. Comparisons with commercial simulators like Microcap11 and CST Cable Studio show a good matching of results. A further 10-100X simulation speedup is obtained if Piecewise-Linear Fitting (PWLF) is used to describe the time-domain behaviors of Scattering Parameters. Single or multiple cell Behavioral Time Models (BTM) can be extracted by PWLF from TDR/TDT measurements and processed by DWS fast convolution algorithms. A setup de-embedding can be performed by pwl breakpoints optimization to fit actual measurements. A RG58 coaxial cable is analyzed and its VF-derived eye-diagrams are compared to PWLF measurement-derived results. At multi-gigabit rates significant differences, due to cable physical implementation effects, are observed. The modeling/simulation alternatives (VF/Spice, VF/DWS and PWLF/DWS) are compared together and the advantages of PWLF/DWS in term of simplicity, stability and speed are highlighted.
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...Piero Belforte
This paper describes PWLFIT+, an extension to the frequency domain ofPWLFIT, a new paradigm in time-domain macromodel ing for linear multiportsystems, based on a piecewise-linea r (PWL) behavioral representation of the S-parameters step response.
PERFORMANCE ANALYSIS OF QOS PARAMETERS LIKE PSNR, MAE & RMSE USED IN IMAGE TR...Journal For Research
Wireless designers constantly seek to improve the spectrum efficiency/capacity, coverage of wireless networks and link reliability. In this direction, Space-time wireless technology that uses multiple antennas along with appropriate signaling and receiver techniques that offers a powerful tool for improving the wireless performance is used in this thesis work. A special version of STBC called ‘Alamouti code’ is used. PSK modulation scheme is used for modulation of data. In this thesis work, the Space-Time Block Codes (STBC) is used in WLAN wireless network that uses multiple numbers of antennas at both transmitter and receiver. The STBC which includes the Alamouti Scheme for 2 transmit antenna and a different number of receiving antenna has been studied, simulated and analyzed. The simulation has been done in MATLAB. Throughput and several parameter performance has been analyzed using the MATLAB.A sample image is transmitted to compare the performance of various parameters like RMSE, PSNR, MAE etc. All the parameters are plotted against SNR (in dB) values ranging from -18 to 30. Various observations being made for the improvement in various parameters with increasing SNR and/or with changing diversity scheme. AWGN channel is used here for communication of sampled image data.
Spatial multiplexing ofdmoqam systems with time reversal techniqueijwmn
Orthogonal Frequency Division Multiplexing with Offset Quadrature Amplitude Modulation (OFDM/OQAM) is a multicarrier modulation scheme that can be considered as an alternative to the conventional Orthogonal Frequency Division Multiplexing (OFDM) with Cyclic Prefix (CP) for transmission over multipath fading channels. In this paper, we investigate the combination of the OFDM/OQAM with Multiple Input Multiple Output (MIMO) system with Time Reversal (TR) technique.
TR can be viewed as a precoding scheme which can be combined with OFDM/OQAM and easily carried out in a MIMO context using spatial data multiplexing.
We present the simulation results of the performance of OFDM/OQAM system in SISO case compared with the conventional CP-OFDM system and the performance of the combination MIMO-OFDM/OQAM with TR compared to MIMO-CP-OFDM. The performance is derived by computing the Bit Error Rate (BER) as a function of the transmit signal-to-noise ratio (SNR).
Capsulization of Existing Space Time TechniquesIJEEE
In this paper, we explore the fundamental
concepts behind the emerging field of space-time coding for
wireless communication system. A space–time code (STC)
is a method which employed to increase the reliability of
data transmission in the wireless communication
systems using multiple transmit antennas.
Digital Wave Simulation of Lossy Lines for Multi-Gigabit ApplicationsPiero Belforte
Frequency domain Vector Fitting (VF) is a well known technique to generate circuital models of a spatially discretized lossy transmission lines from theoretical formulation of losses. The sub-picosecond time steps required by multi-gigahertz bandwidths and short transmission lines included in the models, determine long Spice simulation times. A 100X speedup can be gained using the Digital Wave Simulator (DWS) instead of Spice. DWS processes the waves of a Digital Network built up connecting together scattering blocks (circuit elements, nodes and S-parameter multi-ports) coming from a Spice-like description. Being a DSP wave processor instead of a classical nodal equations solver, DWS is computationally very fast and numerically stable. Comparisons with commercial simulators like Microcap11 and CST Cable Studio show a good matching of results. A further 10-100X simulation speedup is obtained if Piecewise-Linear Fitting (PWLF) is used to describe the time-domain behaviors of Scattering Parameters. Single or multiple cell Behavioral Time Models (BTM) can be extracted by PWLF from TDR/TDT measurements and processed by DWS fast convolution algorithms. A setup de-embedding can be performed by pwl breakpoints optimization to fit actual measurements. A RG58 coaxial cable is analyzed and its VF-derived eye-diagrams are compared to PWLF measurement-derived results. At multi-gigabit rates significant differences, due to cable physical implementation effects, are observed. The modeling/simulation alternatives (VF/Spice, VF/DWS and PWLF/DWS) are compared together and the advantages of PWLF/DWS in term of simplicity, stability and speed are highlighted.
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...Piero Belforte
This paper describes PWLFIT+, an extension to the frequency domain ofPWLFIT, a new paradigm in time-domain macromodel ing for linear multiportsystems, based on a piecewise-linea r (PWL) behavioral representation of the S-parameters step response.
PERFORMANCE ANALYSIS OF QOS PARAMETERS LIKE PSNR, MAE & RMSE USED IN IMAGE TR...Journal For Research
Wireless designers constantly seek to improve the spectrum efficiency/capacity, coverage of wireless networks and link reliability. In this direction, Space-time wireless technology that uses multiple antennas along with appropriate signaling and receiver techniques that offers a powerful tool for improving the wireless performance is used in this thesis work. A special version of STBC called ‘Alamouti code’ is used. PSK modulation scheme is used for modulation of data. In this thesis work, the Space-Time Block Codes (STBC) is used in WLAN wireless network that uses multiple numbers of antennas at both transmitter and receiver. The STBC which includes the Alamouti Scheme for 2 transmit antenna and a different number of receiving antenna has been studied, simulated and analyzed. The simulation has been done in MATLAB. Throughput and several parameter performance has been analyzed using the MATLAB.A sample image is transmitted to compare the performance of various parameters like RMSE, PSNR, MAE etc. All the parameters are plotted against SNR (in dB) values ranging from -18 to 30. Various observations being made for the improvement in various parameters with increasing SNR and/or with changing diversity scheme. AWGN channel is used here for communication of sampled image data.
Spatial multiplexing ofdmoqam systems with time reversal techniqueijwmn
Orthogonal Frequency Division Multiplexing with Offset Quadrature Amplitude Modulation (OFDM/OQAM) is a multicarrier modulation scheme that can be considered as an alternative to the conventional Orthogonal Frequency Division Multiplexing (OFDM) with Cyclic Prefix (CP) for transmission over multipath fading channels. In this paper, we investigate the combination of the OFDM/OQAM with Multiple Input Multiple Output (MIMO) system with Time Reversal (TR) technique.
TR can be viewed as a precoding scheme which can be combined with OFDM/OQAM and easily carried out in a MIMO context using spatial data multiplexing.
We present the simulation results of the performance of OFDM/OQAM system in SISO case compared with the conventional CP-OFDM system and the performance of the combination MIMO-OFDM/OQAM with TR compared to MIMO-CP-OFDM. The performance is derived by computing the Bit Error Rate (BER) as a function of the transmit signal-to-noise ratio (SNR).
Capsulization of Existing Space Time TechniquesIJEEE
In this paper, we explore the fundamental
concepts behind the emerging field of space-time coding for
wireless communication system. A space–time code (STC)
is a method which employed to increase the reliability of
data transmission in the wireless communication
systems using multiple transmit antennas.
Performance Analysis of DV-Hop Localization Using Voronoi ApproachIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
Multi carrier equalization by restoration of redundanc y (merry) for adaptive...IJNSA Journal
This paper proposes a new blind adaptive channel shortening approach for multi-carrier systems. The
performance of the discrete Fourier transform-DMT (DFT-DMT) system is investigated with the proposed
DST-DMT system over the standard carrier serving area (CSA) loop1. Enhanced bit rates demonstrated
and less complexity also involved by the simulation of the DST-DMT system.
Bit Error Rate Performance of MIMO Spatial Multiplexing with MPSK Modulation ...ijsrd.com
Wireless communication is one of the most effective areas of technology development of our time. Wireless communications today covers a very wide array of applications. In this, we study the performance of general MIMO system, the general V-BLAST architecture with MPSK Modulation in Rayleigh fading channels. Based on bit error rate, we show the performance of the 2x2 schemes with MPSK Modulation in noisy environment. We also show the bit error rate performance of 2x2, 3x3, 4x4 systems with BPSK modulation. We see that the bit error rate performance of 2x2 systems with QPSK modulation gives us the best performance among other schemes analysed here.
Efficient FPGA implementation of high speed digital delay for wideband beamfor...journalBEEI
In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.
Error Rate Analysis of MIMO System Using V Blast Detection Technique in Fadin...IJERA Editor
Wireless communication system with multi- antenna arrays has been a field of intensive analysis on the last years. The appliance of multiple sending antennas and Receiving Antennas either side will considerably enhance the data rate and rate. The review of the performance limitations of MIMO system becomes vital since it will provide lot ideas in understanding and planning the important life MIMO systems. Vertical Bell Laboratories layered space Time (V-BLAST). The thought behind Multiple Input and Multiple Output system is that the signals on the transmitter antennas at one finish and also the receiver antennas at the opposite finish are correlative in such how that the performance (Bit Error Rate or BER) or the info rate (bits/sec) of the wireless communication system for every MIMO subscriber are improved. During this paper we tend to are proposing a technique that evaluates the performance of V-BLAST MIMO system in several thought of Rayleigh attenuation surroundings to urge higher performance of the system. In V- BLAST MIMO system a number of linear detection techniques will be used for interference cancellation. At this point we are using MMSE-IC for the same. Our expected system provide higher error rate performance with the used of matched filter at receiver aspect .The projected system compared within the presence of AWGN. Now matched filter applied on V- BLAST MIMO with MMSE-IC system in fading diversity surroundings.
Performance analysis of DWT based OFDM over FFT based OFDM and implementing o...VLSICS Design
Growth in technology has led to unprecedented demand for high speed architectures for complex signal processing applications. In 4G wireless communication systems, bandwidth is a precious commodity, and service providers are continuously met with the challenge of accommodating more users with in a limited allocated bandwidth. To increase data rate of wireless medium with higher performance, OFDM (orthogonal frequency division multiplexing) is used. Recently DWT (Discrete wavelet transforms) is adopted in place of FFT (Fast Fourier transform) for frequency translation. Modulation schemes such as 16-QAM, 32-QAM, 64-QAM and 128-QAM (Quadrature amplitude modulation) have been used in the developed OFDM system for both DWT and FFT based model. In this paper we propose a DWT-IDWT based OFDM transmitter and receiver that achieve better performance in terms SNR and BER for AWGN channel. It proves all the wavelet families better over the IFFT-FFT implementation. The OFDM model is developed using Simulink, various test cases have been considered to verify its performance. The DWTOFDM using Lifting Scheme architecture is implemented on FPGA optimizing hardware, speed & cost. The wavelet filter used for this is Daubechies (9, 7) with N=2. The RTL code is written in Verilog-HDL and simulated in Modelsim. The design is then synthesized in Xilinx and implemented on Virtex5 FPGA board and the results were validated using ChipScope.
MIMO System Performance Evaluation for High Data Rate Wireless Networks usin...IJMER
Space–time block coding is used for data communication in fading channels by multiple
transmit antennas. Message data is encoded by applying a space–time block code and after the encoding
the data is break into ‘n’ streams of simultaneously transmitted strings through n transmit antennas. The
received signal at the receiver end is the superposition of the n transmitted signals distorted due to noise
.For data recovery maximum likelihood decoding scheme is applied through decoupling of the signals
transmitted from different antennas instead of joint detection. The maximum likelihood decoding scheme
applies the orthogonal structure of the space–time block code (OSTBC) and gives a maximum-likelihood
decoding algorithm based on linear processing at the receiver. In this paper orthogonal space–time
block codes based model is developed using Matlab/Simulink to get the maximum diversity order for a
given number of transmit and receive antennas subject with a simple decoding algorithm.
The simulink block of orthogonal space coding block with space–time block codes is applied with and
without gray coding. The OSTBC codes gives the maximum possible transmission rate for any number of
transmit antennas using any arbitrary real constellation such of M-PSK array. For different complex
constellation of M- PSK space–time block codes are applied that achieve 1/2 and 3/4 of the maximum
possible transmission rate for MIMO transmit antennas using different complex constellations.
VECTOR VS PIECEWISE-LINEAR FITTING FOR SIGNAL AND POWER INTEGRITY SIMULATIONPiero Belforte
The basic concepts of two fitting methods suitable for signal and power integrity simulation up to multi-gigabit/sec rates are presented. The traditional method is based on Vector Fitting (VF), a well known technique to approximate complex functions of frequency by a rational polynomial expression in terms of poles and residues. The second is a full time-domain approach mainly based on behavioral models supported by the Digital Wave Simulator.
PWLFIT/DWS advantages over VECTFIT/Spice can be summarized with the 3S acronym: SIMPLICITY, STABILITY and SPEED.
SIMPLICITY because the pwl fitting of a time-domain behavior is a very fast, explicit and intuitive process that doens't need the solution of implicit equations as required by Vector fitting. Time-domain S-parameter of actual devices in matched conditions shows simpler behaviors than the corresponding impedance in the frequency domain.
STABILITY because the use of Digital Wave processing is intrinsically very stable. Extracted pwl behaviors processed by fast convolution within DWS are unconditionally stable if the source behavior is stable. This means that NO numerical conditioning is required. As known Vector Fitting often require numerical conditioning to get stable results.
SPEED: time-domain pwl fitting is a very fast process. DWS simulations are also very fast even at very small time steps required by multigigabit system analysis. DWS/SPICE typical speedups are 100X for traditional VF derived RLC-TL circuits and up to 10000X when using pwl Behavioral Models in time domain.
Performance Analysis of DV-Hop Localization Using Voronoi ApproachIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
Multi carrier equalization by restoration of redundanc y (merry) for adaptive...IJNSA Journal
This paper proposes a new blind adaptive channel shortening approach for multi-carrier systems. The
performance of the discrete Fourier transform-DMT (DFT-DMT) system is investigated with the proposed
DST-DMT system over the standard carrier serving area (CSA) loop1. Enhanced bit rates demonstrated
and less complexity also involved by the simulation of the DST-DMT system.
Bit Error Rate Performance of MIMO Spatial Multiplexing with MPSK Modulation ...ijsrd.com
Wireless communication is one of the most effective areas of technology development of our time. Wireless communications today covers a very wide array of applications. In this, we study the performance of general MIMO system, the general V-BLAST architecture with MPSK Modulation in Rayleigh fading channels. Based on bit error rate, we show the performance of the 2x2 schemes with MPSK Modulation in noisy environment. We also show the bit error rate performance of 2x2, 3x3, 4x4 systems with BPSK modulation. We see that the bit error rate performance of 2x2 systems with QPSK modulation gives us the best performance among other schemes analysed here.
Efficient FPGA implementation of high speed digital delay for wideband beamfor...journalBEEI
In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.
Error Rate Analysis of MIMO System Using V Blast Detection Technique in Fadin...IJERA Editor
Wireless communication system with multi- antenna arrays has been a field of intensive analysis on the last years. The appliance of multiple sending antennas and Receiving Antennas either side will considerably enhance the data rate and rate. The review of the performance limitations of MIMO system becomes vital since it will provide lot ideas in understanding and planning the important life MIMO systems. Vertical Bell Laboratories layered space Time (V-BLAST). The thought behind Multiple Input and Multiple Output system is that the signals on the transmitter antennas at one finish and also the receiver antennas at the opposite finish are correlative in such how that the performance (Bit Error Rate or BER) or the info rate (bits/sec) of the wireless communication system for every MIMO subscriber are improved. During this paper we tend to are proposing a technique that evaluates the performance of V-BLAST MIMO system in several thought of Rayleigh attenuation surroundings to urge higher performance of the system. In V- BLAST MIMO system a number of linear detection techniques will be used for interference cancellation. At this point we are using MMSE-IC for the same. Our expected system provide higher error rate performance with the used of matched filter at receiver aspect .The projected system compared within the presence of AWGN. Now matched filter applied on V- BLAST MIMO with MMSE-IC system in fading diversity surroundings.
Performance analysis of DWT based OFDM over FFT based OFDM and implementing o...VLSICS Design
Growth in technology has led to unprecedented demand for high speed architectures for complex signal processing applications. In 4G wireless communication systems, bandwidth is a precious commodity, and service providers are continuously met with the challenge of accommodating more users with in a limited allocated bandwidth. To increase data rate of wireless medium with higher performance, OFDM (orthogonal frequency division multiplexing) is used. Recently DWT (Discrete wavelet transforms) is adopted in place of FFT (Fast Fourier transform) for frequency translation. Modulation schemes such as 16-QAM, 32-QAM, 64-QAM and 128-QAM (Quadrature amplitude modulation) have been used in the developed OFDM system for both DWT and FFT based model. In this paper we propose a DWT-IDWT based OFDM transmitter and receiver that achieve better performance in terms SNR and BER for AWGN channel. It proves all the wavelet families better over the IFFT-FFT implementation. The OFDM model is developed using Simulink, various test cases have been considered to verify its performance. The DWTOFDM using Lifting Scheme architecture is implemented on FPGA optimizing hardware, speed & cost. The wavelet filter used for this is Daubechies (9, 7) with N=2. The RTL code is written in Verilog-HDL and simulated in Modelsim. The design is then synthesized in Xilinx and implemented on Virtex5 FPGA board and the results were validated using ChipScope.
MIMO System Performance Evaluation for High Data Rate Wireless Networks usin...IJMER
Space–time block coding is used for data communication in fading channels by multiple
transmit antennas. Message data is encoded by applying a space–time block code and after the encoding
the data is break into ‘n’ streams of simultaneously transmitted strings through n transmit antennas. The
received signal at the receiver end is the superposition of the n transmitted signals distorted due to noise
.For data recovery maximum likelihood decoding scheme is applied through decoupling of the signals
transmitted from different antennas instead of joint detection. The maximum likelihood decoding scheme
applies the orthogonal structure of the space–time block code (OSTBC) and gives a maximum-likelihood
decoding algorithm based on linear processing at the receiver. In this paper orthogonal space–time
block codes based model is developed using Matlab/Simulink to get the maximum diversity order for a
given number of transmit and receive antennas subject with a simple decoding algorithm.
The simulink block of orthogonal space coding block with space–time block codes is applied with and
without gray coding. The OSTBC codes gives the maximum possible transmission rate for any number of
transmit antennas using any arbitrary real constellation such of M-PSK array. For different complex
constellation of M- PSK space–time block codes are applied that achieve 1/2 and 3/4 of the maximum
possible transmission rate for MIMO transmit antennas using different complex constellations.
VECTOR VS PIECEWISE-LINEAR FITTING FOR SIGNAL AND POWER INTEGRITY SIMULATIONPiero Belforte
The basic concepts of two fitting methods suitable for signal and power integrity simulation up to multi-gigabit/sec rates are presented. The traditional method is based on Vector Fitting (VF), a well known technique to approximate complex functions of frequency by a rational polynomial expression in terms of poles and residues. The second is a full time-domain approach mainly based on behavioral models supported by the Digital Wave Simulator.
PWLFIT/DWS advantages over VECTFIT/Spice can be summarized with the 3S acronym: SIMPLICITY, STABILITY and SPEED.
SIMPLICITY because the pwl fitting of a time-domain behavior is a very fast, explicit and intuitive process that doens't need the solution of implicit equations as required by Vector fitting. Time-domain S-parameter of actual devices in matched conditions shows simpler behaviors than the corresponding impedance in the frequency domain.
STABILITY because the use of Digital Wave processing is intrinsically very stable. Extracted pwl behaviors processed by fast convolution within DWS are unconditionally stable if the source behavior is stable. This means that NO numerical conditioning is required. As known Vector Fitting often require numerical conditioning to get stable results.
SPEED: time-domain pwl fitting is a very fast process. DWS simulations are also very fast even at very small time steps required by multigigabit system analysis. DWS/SPICE typical speedups are 100X for traditional VF derived RLC-TL circuits and up to 10000X when using pwl Behavioral Models in time domain.
Digital Wave Formulation of Quasi-Static Partial Element Equivalent Circuit M...Piero Belforte
This presentation shows a digital wave formulation
(DWF) of the quasi-static Partial Element Equivalent Circuit
formulation. Through the use of a pertinent change of variablesand the choice of a specific implementation of PEEC cell elementsin the Digital Wave domain, the standard PEEC model istransformed into and solved as a wave digital network. The
example reported shows the accuracy and the significant speedup up to 627X of the proposed DWF-based PEEC solver when compared to the standard Spice solution.
Presented at SPI2016, Turin, May 2016.
Digital Wave Simulation of Quasi-Static Partial Element Equivalent Circuit Me...Piero Belforte
This is an extended version of the paper published on IEEE Transactions on EMC, October 2016. PEEC modeling is a well established technique for obtaining a circuit equivalent for an electromagnetic problem. The time domain solution of such models is usually performed using nodal voltages and branch currents, or sometimes charge and currents. The present paper describes a possible alternative approach which can be obtained expressing and solving the problem in the waves domain. The digital wave theory is used to find an equivalent representation of the PEEC circuit in the wave domain. Through a pertinent continuous to discrete time transformation, the constitutive relations for partial inductances, capacitances and resistances are translated in an explicit form. The combination of such equations with Kirchhoff laws allows to achieve a semi-explicit resolution scheme. Three different physical configurations are analyzed and their extracted Digital Wave PEEC models are simulated at growing sizes using the general-purpose Digital Wave Simulator (DWS). The results are compared to those obtained by using standard SPICE simulators in both linear and nonlinear cases. When the size of the model is manageable by SPICE, an excellent accuracy and a speed-up factor of up to three orders of magnitude are observed with much lower memory requirements. PEEC model sizes manageable by DWS are also an order of magnitude larger than SPICE. A comparative analysis of results including the effect of parameters like the simulation time step choice is also presented.
Automated Piecewise-Linear Fitting of S-Parameters step-response (PWLFIT) for...Piero Belforte
An innovative full time-domain macromodeling
technique for general, linear multiport systems is described. The
methodology is defined in a digital wave framework and timedomain
simulations are performed via an efficient method called
Segment Fast Convolution (SFC). It is based on a piecewiseconstant
(PWC) model of the impulse response of scattering
parameters, computed starting from a piecewise-linear fitting
of their step response (PWLFIT). Such step response is directly
available from time-domain reflectometer measurements
(TDR/TDT) or equivalent simulations. The model-building phase
is performed in a fast automated framework and an analytic
formulation of computational efficiency of the SFC with respect to
the standard time-domain convolution is given. Two application
examples are used to verify the PWLFIT performance and to
perform a comparison with macromodeling methods defined in
the frequency-domain, such as Vector Fitting (VF).
Index Terms—Digital wave models, time-domain macromodeling,
S-parameters, step response.
FPGA IMPLEMENTATION OF EFFICIENT VLSI ARCHITECTURE FOR FIXED POINT 1-D DWT US...VLSICS Design
In this paper, a scheme for the design of area efficient and high speed pipeline VLSI architecture for the computation of fixed point 1-d discrete wavelet transform using lifting scheme is proposed. The main focus of the scheme is to reduce the number and period of clock cycles and efficient area with little or no overhead on hardware resources. The fixed point representation requires less hardware resources compared with floating point representation. The pipelining architecture speeds up the clock rate of DWT and reduced bit precision reduces the area required for implementation. The architecture has been coded in verilog HDL on Xilinx platform and the target FPGA device used is Virtex-II Pro family, XC2VP7- 7board. The proposed scheme requires the least computing time for fixed point 1-D DWT and achieves the
less area for implementation, compared with other architectures. So this architecture is realizable for real time processing of DWT computation applications.
This paper discusses the time-frequency transform based fault detection and classification of STATCOM (Static synchronous compensator) integrated single circuit transmission line. Here, fast-discrete S-Transform (FDST) based time-frequency transformation is proposed for evaluation of fault detection and classification including STATCOM in transmission line. The STATCOM is placed at mid-point of transmission line. The system starts processing by extracting the current signals from both end of current transformer (CT) connected in transmission line. The current signals from CT’s are fed to FDST to compute the spectral energy (SE) of phase current at both end of the line. The differential spectral energy (DSE) is evaluated by subtracting the SE obtained from sending end and SE obtained from receiving end of the line. The DSE is the key indicator for deciding the fault pattern detection and classification of transmission line. This proposed scheme is simulated using MATLAB simulink R2010a version and successfully tested under various parameter condition such as fault resistance (Rf),source impedance (SI), fault inception angle (FIA) and reverse flow of current. The proposed approach is simple, reliable and efficient as the processing speed is very fast to detect the fault within a cycle period of FDT (fault detection time).
DELAY ERROR WITH META-STABILITY DETECTION AND CORRECTION USING CMOS TRANSMISS...VLSICS Design
The new technologies are giving the advance systems which are capable to perform multiple operations simultaneously. This all is possible by the scaling technology where the overall chip size get reduced but due to manufacturing and fabrication defects, certain design uncertainty arises thereby affecting the transistor performance by timing related effect. The robust circuit where sufficient margins are given sometime is nothing but a wastage of power to overcome this, hybrid technique called Razor was innovated which scaled the voltage dynamically and automatically detect and correct the timing related defects. This paper proposed a new design for the razor flip flop with CMOS transmission logic. The traditional design used the dynamic logic approach which has the drawback of threshold voltage attenuation which is removed by CMOS transmission logic and the transparency of the logic data at input and output is highly achieved. The overall purpose for such design is to reduce the power and delay of the circuit which is reduced by 0.6mW and 12.11ns respectively and thus increased the overall performance. The complexity of
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The execution of today's correspondence frameworks is exceedingly subject to the utilized Analog-to-Digital converters (ADCs), and with a specific end goal to give more flexibility and exactness to the developing correspondence innovations, superior-ADCs are needed. In this respect, the time-interleaved operation of an exhibit of ADCs (TI-ADC) might be a sensible result. A TI-ADC can build its throughput by utilizing M channel ADCs or sub converters in parallel and examining the data motion in a period-interleaved way. In any case, the execution of a TI-ADC gravely suffers from the bungles around the channel ADCs. In this paper we survey the advancement in the configuration of low-intricacy advanced remedy structures and calculations for time-interleaved ADCs in the course of the most recent five years. We devise a discrete-time model, state the outline issue, and finally infer the calculations and structures. Specifically, we examine proficient calculations to outline time-differing remedy filters and additionally iterative structures using polynomial based filters. Thusly, the remuneration structure may be utilized to repay time-differing recurrence reaction befuddles in time-interleaved ADCs, and in addition to remake uniform examples from nonuniformly tested indicators. We examine the recompense structure, research its execution, and exhibit requisition zones of the structure through various illustrations. At long last, we give a standpoint to future examination questions.
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Implementation of Wide Band Frequency Synthesizer Base on DFS (Digital Frequ...IJMER
Wide Band Frequency Synthesizer has become essential components in wireless communication
systems. They are used as frequency synthesizers with precise and convenient digital control in both traditional
electronics, such as televisions and AM/FM radios, and modern consumer products among which cellular
mobile phone is a striking example.
IC fabrication technology advances have made monolithic integration possible. More and more
electronic devices can be put on the same chip to reduce the number of external components and then the costs.
Therefore, on a single chip we can accomplish many functions for which we might need to make several chips
work together a few years ago. A monolithic wide-band PLL is of great interests to wireless communication
applications due to both its low cost and convenience to switch between different communication standards.
The focus of this work is to implement a wide-band Frequency Synthesizer using as few as possible building
blocks and also as simple as possible structure.
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IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
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DIGITAL WAVE SIMULATION OF LOSSY LINES FOR MULTI-GIGABIT APPLICATION
1. 1
Abstract Frequency domain Vector Fitting (VF) is a well known
technique to generate circuital models of a spatially discretized
lossy transmission lines from theoretical formulation of losses.
The sub-picosecond time steps required by multi-gigahertz
bandwidths and short transmission lines included in the models,
determine long Spice simulation times. A 100X speedup can be
gained using the Digital Wave Simulator (DWS) instead of
Spice. DWS processes the waves of a Digital Network built up
connecting together scattering blocks (circuit elements, nodes
and S-parameter multi-ports) coming from a Spice-like
description. Being a DSP wave processor instead of a classical
nodal equations solver, DWS is computationally very fast and
numerically stable. Comparisons with commercial simulators like
Microcap11 and CST Cable Studio show a good matching of
results. A further 10-100X simulation speedup is obtained if
Piecewise-Linear Fitting (PWLF) is used to describe the time-
domain behaviors of Scattering Parameters. Single or multiple
cell Behavioral Time Models (BTM) can be extracted by PWLF
from TDR/TDT measurements and processed by DWS fast
convolution algorithms. A setup de-embedding can be
performed by pwl breakpoints optimization to fit actual
measurements. A RG58 coaxial cable is analyzed and its VF-
derived eye-diagrams are compared to PWLF measurement-
derived results. At multi-gigabit rates significant differences,
due to cable physical implementation effects, are observed. The
modeling/simulation alternatives (VF/Spice, VF/DWS and
PWLF/DWS) are compared together and the advantages of
PWLF/DWS in term of simplicity, stability and speed are
highlighted.
Index Terms— Behavioral Time Modeling (BTM), , Digital
Wave Network (DWN), Digital Wave Simulator (DWS), Device
Under Test (DUT), Eye Diagrams (ED), Fast Fourier Transform
(FFT), Inter-Symbol Interference (ISI), Nodal Analysis (NA),
Printed Circuit Board (PCB), Piece-Wise Linear (PWL), Pseudo
Random Bit Sequence (PRBS), Signal Integrity (SI), Time-
Domain Reflectometer (TDR), Time-Domain Transmission
(TDT), Transmission Line (TL), Vector Fitting (VF), Vector
Network Analyzer (VNA), Wave Digital Filter (WDF), Worst
Case Eye Diagram (WCED).
I. DIGITAL WAVE SIMULATION: HISTORICAL
BACKGROUND
The application of digital wave algorithms to high-speed
circuit simulations started at CSELT Labs (Turin, Italy) in the
early '70s [1],[2]. This activity was inspired by prof. Alfred
Fettweis [2] early works on Wave Digital Filters (WDF).
While WDF work was focused on a class of digital filters able
to mimic the behavior of analog filters, the aim of CSELT
researchers was to build up a digital wave model of
interconnects among high-speed integrated circuits. The
digital wave equivalent of a Transmission Line (TL) was the
key element of a modular wave network used in the early
simulation program ETA (Easy Transient Analysis) [1]. The
I/O models of active devices were extracted from TDR
measurements and automatically fitted by simulation to
predefined lumped/distributed (RLC-TL) electrical models.
Measurements, model fitting and simulation programs ran on
the same HP9821 desktop computer as shown in Fig.1 [2]. In
the following decade a new version of the simulator called
APICE (Advanced Program for Interconnect Circuital
Evaluation) was developed with extension to lossy
interconnects [4], crosstalk analysis and Worst Case Eye
Diagram (WCED) calculations [5]. In the following years
started the development of a simulation program for general
topology linear and nonlinear circuits. It was conceived with a
Spice-like netlist syntax and its proprietary algorithms
developed by P. Belforte and G. Guaschino included the
solution of the well known DFL (Delay Free Loop) WDF
topology problem. Multi-port S-parameters blocks, piecewise
-linear description of time-domain behaviors, fast convolution
algorithms and nonlinear/time varying resistors were other
features of SPRINT (Simulation Program of Response of
Integrated Network Transients). The companion application
SIGHTS (Standard Interface for Graphic Handling of
Transient Signals) included simulated waveform plotting and
post-processing. WCED, FFT and graphic PWL extraction.
SPRINT and SIGHTS were produced by HDT (High Design
Technology), the company founded in 1988 by P. Belforte
and G.Guaschino. Signal and Power Integrity analysis
included multi-port nonlinear IBIS-like macromodels of
driver/receivers [6], [7]. A collection of state-of-the art
applications was presented at the HP Digital Design
Symposium in 1993 [7] while an application to Multi-Chip
Modules lossy interconnects is reported in [8]. Starting from
the mid '90s, the HDT tools were included in THRIS
(Telecom Hardware Robustness Inspection System) developed
within a CSELT-HDT cooperation [9]. Simulation of radiated
emissions (EMIR) was added in the mid '90s [10]. After
HDT's end of activity in 2001, the founders developed DWS
(Digital Wave Simulator) [11] and DWV (Digital Wave
Viewer) [12]. In 2012 started a cooperation with Ischematics
[13] for developing the cloud-based version of DWS called
Spicy SWAN. A more detailed story of DWS is available in
reference [14].
Digital Wave Simulation of Lossy Lines for
Multi-Gigabit Applications
Piero Belforte, Member, IEEE
2. 2
Fig.1. CSELT LABS, Turin, year 1975: An early application of first-
generation Digital Wave simulator ETA in the design of a .5Gbps high-speed
Multichip Module. The 500Mhz simulated clock waveforms are plotted as eye
diagrams to evaluate jitter and skews.
II. VECTOR VS PIECEWISE-LINEAR FITTING
TECHNIQUES
The basic concepts of two fitting techniques for system
identification suitable for both signal and power integrity
simulation are discussed. Both methods can deal with both
mono and two-dimensional signal propagation related to
lossy interconnects (cables, traces etc.) and power
distribution planes of printed circuit boards. The traditional
method is based on Vector Fitting (VF) [16], [17], a well
known technique to approximate complex functions of
frequency by a rational polynomial expression in terms of
poles and residues. The second is a full time-domain approach
mainly based on behavioral models (BTM) supported by
DWS [6], [7], [8], [9], [11], [12]. DWS processes the waves
of a Digital Network built up connecting together scattering
blocks (traditional circuit elements, nodes and S-parameter
blocks) coming from a Spice-like description. The two
methods are schematically compared in the flow of Fig. 2.
A. The traditional way: Frequency domain Vector Fitting
and Spice simulation
Vector Fitting modeling flow is shown at the left side of
Fig. 2. In case of mono-dimensional propagation, as applies
to lossy interconnects, the physical line is discretized
according to a chosen spatial pitch in several equal
segments (unit cells) connected in cascade. The pitch is
related to the required model bandwidth. Each cell can be
implemented as a ZY-TL circuit where Z is a series
impedance, Y a parallel admittance, both frequency
dependent, and TL is an ideal Transmission Line (TL) as
shown in Fig. 3. Starting from the geometrical and physical
crossection data, TL characteristic impedance Z0 is obtained
from theoretical formulations related to the specific cross-
section. TL delay time is the ratio between the spatial pitch
and the propagation velocity. Z(ω) and Y(ω) are obtained
from the theoretical expressions of skin effect and dielectric
losses versus frequency respectively.
Fig.2 . General modeling/simulation flow: on the left the classical method
based on impedance Vector Fitting , on the right the full time-domain
approach based on S-parameters and DWS processing.
Z()
Y()
TL Z0, td
Z0,td*Delt
Fig.3 . ZY-TL unit cell related to a spatial segmentation pitch
Using the VECTFIT code [17] applied to theoretical
frequency behaviors, unit-cell poles and zeros can be extracted
and then mapped into RL or RLC circuits leading to a Spice-
like cellular model of the interconnect. This ZY-TL model
can be simulated in time domain using a conventional Nodal
Analysis solver like Spice. A careful choice of Spice version is
needed because the presence of several electrically "short"
Transmission Lines requires both an accurate TL model and
the ability to work at small (picosecond or even
subpicosecond) fixed time step. Only a subset of commercial
Spice versions is able to satisfy the previous conditions, while
other versions could lead to inaccurate results or convergence
problems. MicroCap11 (MC11) by Spectrum Software [19]
is a Spice versions able to deal with this class of circuits.
B. An alternative way: Frequency-domain Vector Fitting
and DWS processing
DWS can be conveniently used to replace MC11 to
simulate the ZY-TL models because it requires typically
1/100 of the simulation time working at the same time step.
This means that sub-picosecond time steps can be used to get
accurate results in short times.
3. 3
C. The unconventional way: Time-domain PWL Fitting and
DWS processing
This method can be applied when the time-domain S-
parameters step responses of the DUT are available. Sources
of such responses are TDR/TDT measurements, analytical
formulas [32], or 2D/3D field solvers. In case of measurement,
a setup de-embedding is needed to extract the required
intrinsic DUT S-parameters. Modern TDR and VNA can
directly perform this task, otherwise a de-embedding loop
procedure can be performed by DWS simulation, as shown in
Fig.2. A Behavioral Time-domain Model (BTM) [7], [8] can
be created directly from the files containing the samples of the
de-embedded S-parameters using the FILE mode description
supported by DWS. A more computationally efficient way is
to use the piecewise linear fitting (PWLF) of S-parameter
behaviors as shown in Fig.1. This task can be done manually
on the plotted waveforms using the MCS (Model Capture
System) facility [7] included in DWV [12], the DWS graphic
postprocessor, online tools, or even automatically on the
imported files coming from measurements or simulations. In
case of spatial segmentation in several BTM cells connected in
cascade (micro-behavioral model) [24], [25], [30] pwl
breakpoint optimization can be performed by comparing the
simulated result of the whole cascade of cells to
measurements or to imported simulations. At the end of this
optimization process a de-embedded model of the DUT is
obtained. A similar procedure can be applied to 2D BTM
models of p.c.b power distribution planes [7]. Thanks to the
fast convolution algorithm included in DWS, the processing
time of PWL BTM models is 10 to 100 times shorter than the
time required using the circuital model.
III. COAXIAL CABLE CASE STUDY
A RG58 coaxial cable was chosen as a case study to
compare together modeling methods and simulation tools.
The results coming this study can be extended to lossy lines
with different geometries like other cables and PCB
interconnects.
Time-domain pulse response of coaxial cables has been
deeply studied and several papers have been written in the past
on this topic. Significant papers on pulse response of coaxial
cable are available in [21],[22]. Several documents regarding
the comparisons between measurements and simulations
related to the RG58 coaxial cable have been written by P.
Belforte and S. Caniggia in recent years [23], [24], [25].
According to these documents, the fully terminated 1.83m
long cable interconnect of Fig.4 has been analyzed. A perfect
cylindrical shape, like that considered by CST Cable Studio,
has been considered for the cable cross section, assuming the
conductors made by solid and homogeneous copper. The
geometrical and electrical parameters used for computing
Z(ω) and Y(ω) taking into account respectively skin effect and
dielectric losses are shown in Fig. 4, where εr is the relative
permittivity and tan δ the loss factor of the dielectric. The
related formulas can be found at chapter 7 of the book [18]. In
order to compare the results, tan is set to the default value
used by CST Cable Studio for the RG58 cable. This value is
8e-4, four times the nominal values for polyethylene (2e-4).
The coaxial cable is segmented adopting a 3cm ZY_TL unit
cell physical length (. The equivalent circuits of Z() and
Y() have been extracted by S. Caniggia by means of the
VECTFIT code [17] using 8 poles each. Two series and
parallel RL networks have been respectively synthesized to
map the 8 poles in frequency domain. TL characteristic
impedance Z0 and delay TD are obtained from the well known
coaxial cable formulas. For a 3cm unit cell length TD resulted
to be 151.7608895659 ps. This delay value will be rounded or
interpolated according to the chosen simulation time step and
DWX option. The DWS netlist of this unit cell is shown on
the right side of Fig.5. A cascade of 61 ZY-TL 3 cm long
cells is used to model the 1.83m long cable.
Fig. 4. RG58 coaxial cable theoretical crossection (CST data) and matched
interconnection schematic.
A. Comparative simulations of the unit cell using Spice and
DWS
Several simulations have been carried out using both
DWS and the evaluation version of MicroCap 11 (MC11)
[19]. These comparative benchmarks have been performed to
compare Digital Wave and Nodal Analysis methods in linear
and nonlinear transmission line situations requiring fixed time
step to get accurate results.
As a significant example of comparison, the 3cm ZY-TL unit
cell related to RG58 coaxial cable has been chosen. To stress
the numerical stability of both simulators a fully mismatched
configuration was selected as benchmark circuit. The
SpicySWAN [13] schematic of this configuration is shown in
Fig.5. A DWS cascadable cell (RG58_3CM) is used to
describe the ZY-TL circuit. Serial adaptors (AS) and
grounded inductors are used to calculate two-port inductors
with the trapezoidal rule [11]. A 2V ideal step generator V0 is
connected to the port P2 of the ZY-TL cell while the port P1 is
open terminated by a 50Gohm resistor R0. The generator V0
stimulates the ZY-TL cell with a 2V step having total rise-
time of 10 femtoseconds. The voltage step propagates along
the circuit and when reaches the port P1 is reflected back by
the open termination. At port P2 the signal is inverted and
reflected back by the near zero impedance of generator V0. In
this way a free oscillation voltage pattern is generated at port
P1. At each oscillation the waveform edges are slowed down
by an increasing dispersion due to cell losses modeled by the
ZY network. Fig. 5 shows the simulated voltage waveform at
port P1 for the first 5ns. To get an accurate result a simulation
time step of 1 femtosecond has been chosen for both
SpicySWAN and MC11. This implies the calculation of 10
Million samples on the 10ns window for both simulators.
Z0=50Ω, tpd=5.058ns/m,
L=1.83m50Ω 50Ω
tr
Vg
Vi Vo
0
2V
Conductor
radius=0.395mm
Shield inner radius
=1.397mm, εr=2.3,
tanδ=0.8x10
-3
4. 4
Fig. 5. ZY-TL unit cell related to a 3cm RG58 coaxial cable segment in a free
oscillation test configuration. DWS cell description on the bottom.
The maximum difference resulted to be about 1 microvolt
peak to peak, confirming a good match between the simulator
responses. The time required for a 10ns simulation on an Intel
Quad-Core i7-2630QM 2.00GHz CPU is about 52 minutes for
MC11 and 35 seconds for DWS.
Fig.6. Simulated voltages at port P1 on a 5ns time window. DWS and
MicroCap11 results at 1Femtosecond time step (solid lines) and differences
(DELTA, dotted line).
B. Effects of simulation time step
The circuit of Fig.4 has been simulated using a cascade of
61 ZY-TL 3cm cells to model the 1.83m long cable. Two
ramp rise-times (tr) of 100ps and 1ps respectively have been
used for the input ramp to evaluate the effect of DWS
simulation time-step choice on the output waveform. The
results are shown in Fig. 7. Time step dependence is more
significant with the faster 1ps rise-time input. A significant
error occurs with a 5ps time step. A slight difference on the
edge foot is still visible between the responses related to 0.5ps
and 1ps time steps. This difference is negligible with the
100ps ramp input. From previous results, a good tradeoff
between simulation speed and accuracy is to choose a 1ps
simulation time step for input rise times in the order of 10ps.
Fig. 7. Cable output voltage related to the schematic of Fig. 4 using the 61
ZY-TL model at 3 different DWS simulation time steps: .5ps (solid line), 1ps
(dash dot line), 5ps (dotted line), 1ps and 100ps rise-time input ramps
C. Effects of spatial segmentation pitch
The effect of line length segmentation on digital bandwidth
has been evaluated in terms of Worst Case Eye Diagram inner
profile. Exploiting the DWS computational speed a
comparison has been carried out between a 61-cell (3 cm unit
length) and a 610-cell ZYTL (3 mm unit length) models in the
configuration of Fig. 4. The chosen input transition time is
17ps (20%-80%) with an erfc shape. The result in terms of
inner WCED contours is shown in Fig.8.
Fig. 8. 20 Gbps WCED inner contours comparison for a 3cm and 3mm ZYTL
cell length. 17ps transition time of erfc input signal. DWS simulation time
step=500 femtosec.
The difference between the two WCEDs is relatively small.
This means that the more computationally efficient 61 ZY-TL
cell model can be used at least up to 20-30Gbps getting a
slightly optimistic result in terms of eye opening.
D. DWS versus CST/Cable Studio comparison
A larger bandwidth eye-diagram comparison between
CST/CS 2014 and DWS was performed using a 40Gbps 255-
bit PRBS (25ps bit-time) input sequence..
In this case the time step was set to 1ps for both simulators
in order to achieve a good result accuracy taking into account
the 10ps (total) linear edges of the input signal. CST CS 2014
has been used with modal model and 40Ghz bandwidth
settings. The eye-diagram comparison is shown in Fig. 9. The
eye diagrams look similar in terms of both opening and ISI
jitter despite the high bit-rate used for this comparison. This
happens because also CST Cable Studio uses a VF-derived
ZY-TL cascade of cells to model the cable. The Y portion that
5. 5
models the dielectric losses is implemented by CST using a
RC instead of the RL network of Fig.5 used with DWS.
Fig. 9. 40 Gbps 255-bit PRBS eye diagrams at cable output: upper CST/CS
2014, lower DWS, 10ps input ramp total transition time, time window=20ns,
Time step=1ps for both simulators.
A remarkable difference between the two simulators is the
CPU time required to get the eye diagrams of Fig.9 starting
from the calculated models. An Intel Quad-Core i7-2630QM
2.00GHz CPU requires 12 min with 4 CPU working in parallel
for CST/CS2014 while about 4 sec with a single CPU
engaged is required by DWS. The observed DWS/CST-
CS2014 speedup factor is 720X.
D. Experimental characterization of an actual cable
A RG58/CU 1.83m long actual cable has been
characterized using the setup shown in Fig. 10. The chosen
sample is manufactured by Tasker company. The internal
conductor is composed by 19x0.18mm stranded tinned copper
wires while the 3mm diameter shield is composed by tinned
copper wires with 98% covering. The dielectric is
polyethylene while the 5mm diameter sheath is made in PVC.
The manufacturer gives also these data: 40milliohm/m DC
resistance, 66% relative propagation velocity, and a 6 values
of insertion loss vs frequency from 50Mhz to 1Ghz. At
50Mhz the attenuation is 9.7 dB/100m while at 1Ghz it is 51.8
dB/100m. The TDR/TDT setup is shown in Fig. 10. In order
to get maximum simplicity and minimum cost, the
launch/termination semi-rigid cables are soldered to the DUT
by means of short (1-2mm) splices. The outer conductors of
the same 60mm long SMA semi-rigid cables and those of the
RG58 cable are all soldered to a common ground plane of a
small metalized board. The 22ps (10%-90%) SD24 head
pulse rise-time is fast enough to get significant measurement
up to about 30Ghz. No particular calibration procedure is
required.
Fig. 10. CSA803C/SD24 TDR/TDT measurement setup for the RG58 CU
TASKER cable (l=1.83m) with details of connecting fixture (lower left) and
RG58 cable tip (lower right).
E. S-parameters de-embedding
An accurate mixed BTM-circuital model of the whole setup
has been developed on the basis of actual TDR response of
the setup alone. This model, shown in Fig.11, includes the
actual SD24 pulse generator waveform , the SMA connectors,
the semi-rigid cables connected to DUT and the soldered
connections. The soldered connections, modeled by 115-
ohm 20ps TLs, acts as markers on the measured waveform
simplifying the measurement of actual cable delay [23].
Fig.11 SpicySWAN schematic of the TDR/TDT setup of Fig.10 used for the
de-embedding of S21 pwl breakpoints
Fig.12 shows the measured S11 waveform on a 50 ns
window. Cable impedance micro-discontinuities due to
crossection variations (Fig. 19) are visible as well the narrow
impedance peaks due to soldered joints. S22 measurement
doesn't coincide with S11 due to the asymmetric effect of these
discontinuities. Fig.12 also shows an example of manually
extracted pwl approximation of S11. High frequency
impedance discontinuities are averaged to limit the number of
breakpoints. The narrow peaks due to reflections at soldered
joints are discarded.
6. 6
Fig. 12. Example of PWL approximation of the measured S11 for the 1.83 m
RG58 CU TASKER coaxial cable (CSA 803C setup of Fig. 10).
The measured S21 rising edge is slowed down by the
setup effects. The S21 behavior de-embedding is performed
starting from the pwl samples taken on the measured
waveform. This first approximated set of breakpoints is used
in the DWS simulative model of the whole setup (Fig. 11).
Breakpoint coordinates are then adjusted by iterations of the
optimization loop shown in Fig. 2. A comparison between the
measured S21 rising edge and the simulated edge including
the setup effects at the end of the fitting process is shown in
Fig. 13. The agreement is very good. The DWS netlist of the
extracted BTM cell and related optimized breakpoints is
shown in Fig.14.
Fig. 13. Measured S21 (edge, solid line) using the setup of Fig.11 vs the
fitted BTM model including the setup effects (dotted line). 50ohm
terminations
Fig.14. DWS netlist of the de-embedded single-cell model of the 1.83m
RG58 coaxial cable
The de-embedded S21 waveform has a faster rising edge
with respect the measured one. A total of 18 breakpoints are
required for S11 and 21 breakpoints for S21. The model of
Fig. 15 is supposed symmetrical for simplicity reasons. The
extracted BTM model has been also simulated configuring the
circuit of Fig.11 with TERM1 node connected to open
termination. The result is compared to the actual one-port
TDR measurement of the open cable. This comparison is
reported in Fig. 15 and shows a good agreement between
measurement and simulation with the exception of a slight
overestimation of reflected edge between 20ns and 23ns.
Fig.15. Measured TDR (solid line) vs simulated waveform (dotted line)
including the setup of the RG58 cable open terminated.
The extracted pwl model of S-parameters is then used in
a circuit simulating an ideal TDR (1ps pulse rise-time) to get
the intrinsic response of the cable. In Fig.16 the 61-cell ZY-
TL theoretical model and the measurement-derived BTM
model of the RG58/CU cable are compared together with and
without setup effects.
Fig.16 Comparison of simulated S11 (upper) and S21 (lower) ZY-TL and
BTM models of the 1.83m RG58/CU cable. Both waveforms with and
without setup effects are shown.
Fig.16 points out significant differences between the two
models. The average magnitude of measurement-derived S11
is about 3 times larger than the value coming up from the
theoretically determined ZY-TL model. The measurement-
derived S21 intrinsic rise-time (20%-80% , without setup) is
55ps, about twice the corresponding 30ps rise-time of the ZY-
TL model. A delay difference of 255ps between the intrinsic
model responses is also shown in Fig.16.
F. Circuital versus Behavioral model comparison
S21 rise-time difference has a substantial impact on high
bit-rate eye-diagrams as shown in Fig.17 for a 255-bit PRBS.
At 20Gbps the eye diagram is about closed using the
measurement-based BTM model and nearly open using the
theory-derived ZY-TL model. The impact of S11 model
differences is not significant at the cable output , but becomes
remarkable in case of not fully terminated or bi-directional
transmission configurations [4].
7. 7
Fig.17. Measurement-based BTM vs ZY-TL simulated eye diagrams for
a 20Gbps PRBS-255 bit sequence of the 1.83m RG58 coaxial cable (DWS).
Input risetime:17ps, erfc waveform.
An Intel Quad-Core i7-2630QM 2.00GHz CPU requires
about 0.4 sec to calculate the 100K samples of the BTM eye
diagram alone while about 30 sec are required for the
simultaneous simulation of both models. A comparative eye
diagram evaluation between RG58 and RG223 coaxial cables
using measurement-derived models is reported in [33].
G. Attenuation versus frequency
Cable attenuation in dB/m has been obtained by
simulating the response of the RG58 models at various
frequencies and compared to manufacturer data in Fig.18.
Fig.18 Comparison of specific cable attenuation in dB/m, 50 MHz to 40 Ghz
(upper) and 50Mhz to 1Ghz (lower).
A fair agreement between BTM model and manufacturer data
(up to 1Ghz) is pointed out, while the attenuation produced by
the ZY-TL model is underestimated. The difference between
BTM and ZY-TL diverges for frequencies higher than 2Ghz
and becomes greater than 10dB beyond 20Ghz. The
differences observed at high frequencies can be explained
considering that the actual cable shown in Fig. 19 is made
using tinned copper stranded conductors. Tin has a resistivity
7 times higher than copper. At 10 Ghz the skin effect depth
for tin is in the order of 2 um and becomes comparable to tin
plating thickness.
Fig.19. a) Actual cross-section of the measured RG58 coaxial cable b)
detailed view of the tinned inner conductors
At higher frequencies (30-40Ghz), the current flows
practically only on the tinned conductor surface. This explain
the attenuation difference considering that tin conductor
resistance is 7 times higher than copper, corresponding to a 17
dB higher attenuation. Other sources of different behaviors
can be conductor stranding and proximity effect not
considered in the ZY-TL model.
IV PERFORMANCE COMPARISON
The matrix depicted in Fig. 20 shows the performance
comparison among the three fitting and simulation
alternatives.
Fig. 20. Relative speedup matrix ( simulator vs fitting method)
DWS simulations run typically 100X faster than MC1, while
the fast convolution applied to process PWLF behavioral time
models achieves a further 10-100X speedup. PWLF
combined with DWS processing offers several advantages
with respect VF combined with NA simulation. It is known
that time-domain S-parameters in matched conditions have
simpler behaviors than the corresponding frequency-domain
impedance behaviors [27]. This means that few pwl (tens)
breakpoints can approximate these behaviors with small
errors. To fit the equivalent impedances in frequency domain
a large number of poles and zeros could be required, leading
to potential numerical stability problems. These stability
problems can be corrected by conditioning in some way the
VF data. On the contrary the well known stability and
passivity of Digital Wave processing [15] doesn't require any
conditioning of PWL description to prevent numerical
instability. Circuital models coming from Vector Fitting,
BTM models and even s-plane/z-plane descriptions can be
mixed to IBIS models of active devices in very complex
networks containing hundreds of thousands scattering
elements [31]. Thanks to a linear growth of simulation time
versus network complexity, these models can be processed by
DWS in times that are more than 4 orders of magnitude
lower than those required by NA simulators. More BTM
modeling applications to p.c.b. interconnects, coupled traces
and p.c.b. power planes are reported in [29] and [30].
8. 8
ACKNOWLEDGEMENT
The author thanks Mr. Spartaco Caniggia for the useful
discussions and for the calculated ZY-TL unit-cell data.
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Piero Belforte Born in Turin in 1947, he
received his Laurea degree in Electronics
Engineering summa cum laude in 1970 from
the Politecnico of Turin. From 1970 to 2000
he worked in CSELT, the Research Center of
Telecom Italia as Head of Switching
Techniques Department and then as Head of
Hardware Qualification Department. His
main activity was focused to state-of-the-art
digital switching systems and qualification
tools for the Telecom network.
In 1975 he started the development of
several generations of high-speed modeling and simulation tools using
innovative DSP algorithms for fast computer simulation of high-speed
electronic systems. These tools have been utilized from the beginning up to
present for the design of both state-of-the-art prototypes and commercial
products. In 1988 he founded and directed the company HDT (High Design
Technology) for the development of state-of.-the art CAE tools for SI/PI/EMC
prediction based on digital wave simulation. In the last years of his activity in
CSELT he also created the hardware quality project THRIS involving several
high tech companies and Universities.. From 2001 to present he continues his
research activity as Independent Researcher. In 2012 he started the
development of Spicy SWAN, cloud-based circuit simulation application in
partnership with Ed Pataky founder of Ischematics. He is author of several
publications and international patents in the field of digital electronics with
reference to digital switching systems and techniques for telecom networks,
high-speed electronics, signal and power integrity, circuital modeling and
simulation, electromagnetic compatibility and test equipment for high
performance digital systems.
Email: piero.belforte@gmail.com
Sites: https://www.linkedin.com/in/pierobelforte
https://www.researchgate.net/profile/Piero_Belforte