Ponniranjan Basker is seeking full-time opportunities in digital/ASIC design and verification starting in June 2018. He has an M.S. in Electrical and Computer Engineering from Portland State University and a B.E. in Electrical and Communication Engineering from Anna University in India. He has skills in SystemVerilog, UVM verification methodology, C++, QuestaSim, Cadence Virtuoso, Synopsys Design Compiler, and Python. His projects include designing and verifying an AMBA AXI3 bus protocol, developing an ISA-level PDP-11 simulator in Python, verifying a PDP-8 architecture in SystemVerilog, and simulating an 8-way

1. PONNIRANJAN BASKER
https://www.linkedin.com/in/ponniranjan-basker | +19717129722 | pbasker@pdx.edu
Objective
Seeking full-time opportunities in the field of Digital/ASIC Design and Verification starting from June ’2018
Education
 M.S, Electrical and Computer Engineering
Portland State University, Portland, OR June’2018
Coursework: Digital Integrated Circuits, ASIC Design and timing, Cache and Memory, Pipelining and Hazards,
Constrained based Random verification, Systemverilog concepts, Low power concepts and Formal verification
 B.E, Electrical and Communication Engineering
Anna University, Chennai, India May’2016
Skills
● HDL: System Verilog, System Verilog Assertions, Verilog
● Verification Methodology: UVM
● Programming Language: C++
● Computer-Based tools: Questa-Sim, Cadence Virtuoso, Synopsys Design Compiler, Veloce Emulator
● Scripting Language: Python
● Bus Protocols: AMBA AXI3
● Architecture: MIPS
Projects
 Design and Verification of AMBA AXI3 Bus protocols – Systemverilog, Veloche Fall’2017
 Designed and verified AMBA AXI3 protocol with one master and two slaves
 Emulated the design in TBX mode of Veloce to attain hardware acceleration
 Instruction Set Architecture (ISA) Level Simulator – Python Spring’2017
● Designed and implemented Fetch-Decode-Execute framework of PDP11 instructions
● Recorded all memory accesses into a trace file and performed exhaustive testing of all instructions
 Verification of PDP – 8 Architecture – Systemverilog Spring’2017
 Developed test bench using SystemVerilog to check the PDP-8 Architecture
 Implemented code coverage and identified the bugs in the circuit through assertions and checker
 Simulation of 8 way set Associative cache – Verilog Winter’2017
● Designed and simulated a 16MB, 8 way set associative cache applying write allocate policy
● Verified the working of true LRU replacement and MESI protocols through exhaustive test cases
 Digital Standard Cell Characterization in Cadence Virtuoso Winter’2017
● Designed ALU with fan-outs and simulations were performed to find rise & fall time, delay
● Physical verification using LVS, DRC and PEX to get parasitic properties from layout
 ASIC Design and Timing Analysis - Systemverilog – Synopsys DC Fall’2016
● Designed and verified sequence detector, pacemaker, traffic controller and n bit iterative comparator
● Performed critical and false path analysis, generated net-list and analyzed the timing reports for the above
 Infrared Based Non-Invasive Glucometer with Insulin Calculator – Arudino IDE- C++ Summer’2015
 Found the glucose level of a person through non-invasive method of measuring the acetone level in breath
 Stored the data in cloud and the amount of insulin to be taken is calculated and displayed
Certifications
 SoC Verification using SystemVerilog - https://www.udemy.com/certificate/UC-R4SMOYTE