Resume

1. Lavina Chandwani
lchandwa@andrew.cmu.edu 412-330-9398 www.linkedin.com/in/lavinachandwani
EDUCATION
Carnegie Mellon University Pittsburgh, PA
Master of Science in Electrical and Computer Engineering December 2019
Current Coursework: How to Write Fast Code, Wireless Sensor Networks, Introduction to Hardware Security
Previous Coursework: Foundations of Computer Systems, Introduction to Embedded Systems
Birla Institute of Technology & Science, Pilani Goa, India
Master of Science (Honors) in Chemistry July 2017
Bachelor of Engineering (Honors) in Electrical and Electronics Engineering July 2017
Relevant Coursework: Analog & Digital VLSI Design, Digital Design, Microprocessors Programming and Interfacing, Programming
for Everybody (Coursera)
SKILLS
Software: MATLAB, Cadence
Programming Experience: C (experienced), Java (learning), Python (learning), Verilog (experienced), System Verilog
(experienced), Assembly language for ARM processors (experienced)
ACADEMIC PROJECTS
Carnegie Mellon University Pittsburgh, PA
Multicore optimization using OpenMP Spring 2019
• Applied OpenMP 4-core optimization on sequential versions of Matrix Multiplication and K-Means algorithm.
• Added SIMD vectorization using AVX2 intel intrinsic for 8x speedup.
Real-time kernel with task scheduling, thread management and synchronization Fall 2018
• Implemented context store and swap with IRQ interrupts and a rate monotonic scheduler.
• Built support for mutex lock and unlock under Highest Locker Priority protocol.
Motor Control in Linux Fall 2018
• Developed Loadable Kernel Modules for user-space applications to alter the speed and direction of rotation of a DC motor.
• Devised a PID controller to control the position of motor.
• Added a client-server model to communicate and control one motor using another over the ethernet network.
Dynamic Storage Allocator Fall 2018
• Created a malloc package in C with coalescing to improve memory utilization.
• Achieved a potent throughput with segregated free lists and first fit search algorithm.
HTTP Proxy Server and Cache Simulator Fall 2018
• Developed a sequential cache-based web proxy able to accept connections and satisfy client request.
• Extended the project to thread-safe concurrent proxy to service multiple requests in parallel.
• Developed a cache simulator for multicore systems using LRU for replacement and MSI protocol for cache coherence.
PROFESSIONAL EXPERIENCE
Tejas Networks Ltd. Bangalore, India
R&D Engineer: Packet Optical Transport Product August 2017 – July 2018
• Tested the Circuit Emulation IP for 63 and 24 lines supporting E1 and DS3 data rates respectively using ANT-5 SDH Tester.
• Developed a Verilog model for Kintex-7 Xilinx FPGA to search and sort ECID values reducing process time by 18%.
• Designed an Internal Tester that generated a user defined bit pattern at transmitter side and analyzed it for bit errors on receiver side,
supporting multiple PDH rates to enable remote testing of a network node.
Texas Instruments Pvt. Ltd. Bangalore, India
Project Trainee: Multiphase Converters Team July 2016 – June 2017
• Constructed System Verilog model of an Automated Checker to detect signal characteristics (Overshoot/Undershoot, Slew Rate,
Settling Time, Rise Time/Fall Time).
• Synthesized a finite state machine in Verilog for Voltage and Temperature Fault Detection Block for a multiphase converter.
• Proposed a novel algorithm to determine transistor and resistor sizes of a current mirror for given parameters: Input Current,
Percentage of Output current mismatch in current mirror branches, and maximum voltage headroom.
• Executed the algorithm in MATLAB and achieved 4 times reduction in area for a given output inaccuracy in LBC9 technology.