The document discusses the simulation of a Triple Data Encryption Standard (Triple DES) circuit using VHDL. It provides background on Triple DES, describes the design and structure of the Triple DES circuit in VHDL, and presents the results of testing the encryption and decryption functions of the circuit through simulation. Testing showed the circuit correctly performed encryption and decryption on input data using the Triple DES algorithm. The design utilized some FPGA resources but would require a clock generator and RAM for implementation on an actual FPGA board.

1. Simulation on Triple Data Encryption standard Adviser Aj. Jarern Vongshumyen By Chatsiri Rattana 47221163 Woranart Hasawayukul 47221858

2. Agenda Introduction Theory on Triple DES Design on Triple DES Testing and Result on Triple DES Conclusion

3. Introduction

4. Background Low security of general data transfer. Use encryption system to secure the data communicates. Then we choose Triple-DES. Apply for design digital circuit by using VHDL(VHSIC Hardware Description Language).

5. Objective To learn about Triple-DES(Triple-Data Encryption Standard) algorithm. To learn about VHDL(VHSIC Hardware Description Language) coding. Can design an implementable digital circuit of Triple-DES. Can simulate a circuit that perform result of encryption and decryption.

6. Tools for Development Xilinx Inc.Webpack 8.2i. ModelSim

7. Theory on Triple DES

8. What is DES? DES - Data Encryption Standard Symmetric system - uses the same key to encrypt/decrypt data. Ciphertext Plaintext DES Key Key Encrypt Decrypt

9. DES Algorithm Structure The algorithm consists of: An initial permutation of the input data Sixteen rounds of the same process –the DES round A final inverse initial permutation of the data

10. Step 1: Create 16 subkeys, each of which is 48-bits long.

11. Step 2: Encode each 64-bit block of data The Feistel ( F ) function

12. Mode of 3DES 3 DES – EDE (2 keys 3DES) Keys = 112 bits C = E k1 ( D k2 (E k1 (M)))

13. 3DES-EDE E D E k 1 k 2 k 1 Plaintext Ciphertext D E D k 1 k 2 k 1 Ciphertext Plaintext

14. Design on Triple DES

15. Schematic On Top Module

16. Coding Entity Top module entity test_tdestop is Port ( data_intdes : in std_logic_vector ( 0 to 63 ) ; key1_intdes : in std_logic_vector ( 0 to 63 ) ; key2_intdes : in std_logic_vector ( 0 to 63 ) ; key3_intdes : in std_logic_vector ( 0 to 63 ) ; clock : in std_logic; function_selecttdes : in std_logic; set_out : in std_logic; lddatatdes : in std_logic; ldkeytdes : in std_logic; resettdes : in std_logic; data_outtdes : out std_logic_vector ( 0 to 63 ) ; out_readytdes : out std_logic ) ;

17. Structure on DESCIPHERTOP

18. DESCIPHERTOP 1,2,3 KEYSCHEDULE DES

19. KEYSCHEDULE

20. DESTOP

21. BLOCKTOP

22. E_EXPANSION FUCNTION

23. ADDKEY

24. SBOX

25. PBOX

26. ADDLEFT

27. Device Utilization Summary Logic Utilization Used Available Utilization Slices 1398 4656 30 % Slice FF 1140 9312 12% IOB 305 232 131% GCLKs 1 24 4% MAX CLK 77.548MHz

28. Testing and Result on Triple DES

29. Test by Test Bench and Wave Form Injection Key 1,2,3 and Data to Triple DES Key1<=“DataBit”,Key2<=“DataBit”,Key3<=“DataBit” Use Text I/O Read and Write Data to Triple DES write write(out_data_out,data_outtdes); writeline(logdata_out,out_data_out); read readline(read_inputtest,read_inputtest_line); read(read_inputtest_line,input_temp); Test Bench not permission injection Output

30. Strategy for test Encryption Decryption Text File Text File Data

31. Test Triple DES ( Encryption ) Input Output

32. Test of Triple DES ( Decryption ) Input Output

33. Conclusion

34. Conclusion Can design and simulation circuit . Use function for simulation circuit. Can Applied Algorithm Triple DES . Circuit has delay time and cannot control some gate. Can synthesis on FPGA board but it need clock generator and RAM. Large IOB must has floorplanning to save spaces that use.