CS304PC:Computer Organization and Architecture session 20 Multiplication algorithm.pptx

1. CS304PC:Computer Organization
and Architecture (R18 II(I sem))
Department of computer science and engineering
(AI/ML)
Session 20
by
Asst.Prof.M.Gokilavani
VITS
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2. TEXTBOOK:
• 1. Computer System Architecture – M. Moris Mano, Third Edition,
Pearson/PHI.
REFERENCES:
• Computer Organization – Car Hamacher, Zvonks Vranesic, Safea
Zaky, Vth Edition, McGraw Hill.
• Computer Organization and Architecture – William Stallings Sixth
Edition, Pearson/PHI.
• Structured Computer Organization – Andrew S. Tanenbaum, 4th
Edition, PHI/Pearson.
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3. Unit III
Data Representation: Data types ,Complements, fixed point
Representations, Floating point representation.
Computer Arithmetic: Addition and subtraction,
multiplication Algorithms, Division Algorithms, Floating-point
Arithmetic operations, Decimal Arithmetic unit, Decimal
Arithmetic operations.
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4. Topics covered in session 20
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• Addition and subtraction
• Multiplication Algorithms
• Division Algorithms
• Floating-point Arithmetic operations
• Decimal Arithmetic unit
• Decimal Arithmetic operations.

5. Multiplication Algorithm
• Example:
• In multiplication algorithm, successive bits of the multiplier, least significant bit
first.
• If the multiplier bit is a 1, the multiplicand is copied down, otherwise zero are
copied down.
• The numbers copied down is successive lines are shifted one position to the left
from the previous number. Finally, the numbers are added, and their sum forms the
product.
• The sign of the product is determined from the sign of the multiplicand and
multiplier.
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6. Hardware Implementation for Signed Magnitude Data
• First, instead of providing register to store and add simultaneously as
many binary numbers as there are bits in the multiplier, it is
convenient to provide an adder for the summation of only binary
numbers and successively accumulated the partial products in
registers.
• Second, instead of shifting the multiplicand to the left, the partial
product is shifted to the right, which results in leaving the partial
product and the multiplicand in the required relative position.
• Third when the corresponding bit of the multiplier is 0, there is no
need to add all zeros to the partial product since it will not alter its
value.
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8. Working of Hardware Implementation
• Initially, the multiplicand is in register B and the multiplier in Q.
• The sum of A and B forms a partial product which is transferred to the
EA register. Both partial product and multiplier are shifted to the right.
This shift will be denoted by the statement shr EAQ to designate the
right shift depicted.
• The least significant bit of A is shifted into the most significant
position of Q, the bit from E is shifted into the most significant
position of A, and 0 is shifted into E.
• After the shift, one bit of the partial product is shifted into Q, pushing
the multiplier bits one position to the right.
• Rightmost flip-flop in register Q, designated by Qn, will hold the bit
of the multiplier, which must be inspected next.
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10. Booth Multiplication Algorithm
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11. Rules For Booth Algorithm
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14. Array Multiplier
• Checking the bits of the multiplier one at a time and forming partial
products is a sequential operation that requires a sequence of add and
shift micro operations.
• The multiplication of two binary numbers can b done with one micro
operation by means of a combinational circuit that forms the product
bits all at once.
• An array multiplier requires a large number of gates, and integrated
circuits.
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15. Array Multiplier
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18. Topics to be covered in next session 21
• Division Algorithm
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Thank you!!!